1 // SPDX-License-Identifier: GPL-2.0-only
3 * Fault injection for both 32 and 64bit guests.
5 * Copyright (C) 2012,2013 - ARM Ltd
6 * Author: Marc Zyngier <marc.zyngier@arm.com>
8 * Based on arch/arm/kvm/emulate.c
9 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
10 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
13 #include <hyp/adjust_pc.h>
14 #include <linux/kvm_host.h>
15 #include <asm/kvm_emulate.h>
17 #if !defined (__KVM_NVHE_HYPERVISOR__) && !defined (__KVM_VHE_HYPERVISOR__)
18 #error Hypervisor code only!
21 static inline u64 __vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
25 if (__vcpu_read_sys_reg_from_cpu(reg, &val))
28 return __vcpu_sys_reg(vcpu, reg);
31 static inline void __vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
33 if (__vcpu_write_sys_reg_to_cpu(val, reg))
36 __vcpu_sys_reg(vcpu, reg) = val;
39 static void __vcpu_write_spsr(struct kvm_vcpu *vcpu, u64 val)
41 write_sysreg_el1(val, SYS_SPSR);
44 static void __vcpu_write_spsr_abt(struct kvm_vcpu *vcpu, u64 val)
47 write_sysreg(val, spsr_abt);
49 vcpu->arch.ctxt.spsr_abt = val;
52 static void __vcpu_write_spsr_und(struct kvm_vcpu *vcpu, u64 val)
55 write_sysreg(val, spsr_und);
57 vcpu->arch.ctxt.spsr_und = val;
61 * This performs the exception entry at a given EL (@target_mode), stashing PC
62 * and PSTATE into ELR and SPSR respectively, and compute the new PC/PSTATE.
63 * The EL passed to this function *must* be a non-secure, privileged mode with
64 * bit 0 being set (PSTATE.SP == 1).
66 * When an exception is taken, most PSTATE fields are left unchanged in the
67 * handler. However, some are explicitly overridden (e.g. M[4:0]). Luckily all
68 * of the inherited bits have the same position in the AArch64/AArch32 SPSR_ELx
69 * layouts, so we don't need to shuffle these for exceptions from AArch32 EL0.
71 * For the SPSR_ELx layout for AArch64, see ARM DDI 0487E.a page C5-429.
72 * For the SPSR_ELx layout for AArch32, see ARM DDI 0487E.a page C5-426.
74 * Here we manipulate the fields in order of the AArch64 SPSR_ELx layout, from
77 static void enter_exception64(struct kvm_vcpu *vcpu, unsigned long target_mode,
78 enum exception_type type)
80 unsigned long sctlr, vbar, old, new, mode;
83 mode = *vcpu_cpsr(vcpu) & (PSR_MODE_MASK | PSR_MODE32_BIT);
85 if (mode == target_mode)
86 exc_offset = CURRENT_EL_SP_ELx_VECTOR;
87 else if ((mode | PSR_MODE_THREAD_BIT) == target_mode)
88 exc_offset = CURRENT_EL_SP_EL0_VECTOR;
89 else if (!(mode & PSR_MODE32_BIT))
90 exc_offset = LOWER_EL_AArch64_VECTOR;
92 exc_offset = LOWER_EL_AArch32_VECTOR;
94 switch (target_mode) {
96 vbar = __vcpu_read_sys_reg(vcpu, VBAR_EL1);
97 sctlr = __vcpu_read_sys_reg(vcpu, SCTLR_EL1);
98 __vcpu_write_sys_reg(vcpu, *vcpu_pc(vcpu), ELR_EL1);
105 *vcpu_pc(vcpu) = vbar + exc_offset + type;
107 old = *vcpu_cpsr(vcpu);
110 new |= (old & PSR_N_BIT);
111 new |= (old & PSR_Z_BIT);
112 new |= (old & PSR_C_BIT);
113 new |= (old & PSR_V_BIT);
115 if (kvm_has_mte(vcpu->kvm))
118 new |= (old & PSR_DIT_BIT);
120 // PSTATE.UAO is set to zero upon any exception to AArch64
121 // See ARM DDI 0487E.a, page D5-2579.
123 // PSTATE.PAN is unchanged unless SCTLR_ELx.SPAN == 0b0
124 // SCTLR_ELx.SPAN is RES1 when ARMv8.1-PAN is not implemented
125 // See ARM DDI 0487E.a, page D5-2578.
126 new |= (old & PSR_PAN_BIT);
127 if (!(sctlr & SCTLR_EL1_SPAN))
130 // PSTATE.SS is set to zero upon any exception to AArch64
131 // See ARM DDI 0487E.a, page D2-2452.
133 // PSTATE.IL is set to zero upon any exception to AArch64
134 // See ARM DDI 0487E.a, page D1-2306.
136 // PSTATE.SSBS is set to SCTLR_ELx.DSSBS upon any exception to AArch64
137 // See ARM DDI 0487E.a, page D13-3258
138 if (sctlr & SCTLR_ELx_DSSBS)
141 // PSTATE.BTYPE is set to zero upon any exception to AArch64
142 // See ARM DDI 0487E.a, pages D1-2293 to D1-2294.
151 *vcpu_cpsr(vcpu) = new;
152 __vcpu_write_spsr(vcpu, old);
156 * When an exception is taken, most CPSR fields are left unchanged in the
157 * handler. However, some are explicitly overridden (e.g. M[4:0]).
159 * The SPSR/SPSR_ELx layouts differ, and the below is intended to work with
160 * either format. Note: SPSR.J bit doesn't exist in SPSR_ELx, but this bit was
161 * obsoleted by the ARMv7 virtualization extensions and is RES0.
163 * For the SPSR layout seen from AArch32, see:
164 * - ARM DDI 0406C.d, page B1-1148
165 * - ARM DDI 0487E.a, page G8-6264
167 * For the SPSR_ELx layout for AArch32 seen from AArch64, see:
168 * - ARM DDI 0487E.a, page C5-426
170 * Here we manipulate the fields in order of the AArch32 SPSR_ELx layout, from
173 static unsigned long get_except32_cpsr(struct kvm_vcpu *vcpu, u32 mode)
175 u32 sctlr = __vcpu_read_sys_reg(vcpu, SCTLR_EL1);
176 unsigned long old, new;
178 old = *vcpu_cpsr(vcpu);
181 new |= (old & PSR_AA32_N_BIT);
182 new |= (old & PSR_AA32_Z_BIT);
183 new |= (old & PSR_AA32_C_BIT);
184 new |= (old & PSR_AA32_V_BIT);
185 new |= (old & PSR_AA32_Q_BIT);
187 // CPSR.IT[7:0] are set to zero upon any exception
188 // See ARM DDI 0487E.a, section G1.12.3
189 // See ARM DDI 0406C.d, section B1.8.3
191 new |= (old & PSR_AA32_DIT_BIT);
193 // CPSR.SSBS is set to SCTLR.DSSBS upon any exception
194 // See ARM DDI 0487E.a, page G8-6244
196 new |= PSR_AA32_SSBS_BIT;
198 // CPSR.PAN is unchanged unless SCTLR.SPAN == 0b0
199 // SCTLR.SPAN is RES1 when ARMv8.1-PAN is not implemented
200 // See ARM DDI 0487E.a, page G8-6246
201 new |= (old & PSR_AA32_PAN_BIT);
202 if (!(sctlr & BIT(23)))
203 new |= PSR_AA32_PAN_BIT;
205 // SS does not exist in AArch32, so ignore
207 // CPSR.IL is set to zero upon any exception
208 // See ARM DDI 0487E.a, page G1-5527
210 new |= (old & PSR_AA32_GE_MASK);
212 // CPSR.IT[7:0] are set to zero upon any exception
213 // See prior comment above
215 // CPSR.E is set to SCTLR.EE upon any exception
216 // See ARM DDI 0487E.a, page G8-6245
217 // See ARM DDI 0406C.d, page B4-1701
219 new |= PSR_AA32_E_BIT;
221 // CPSR.A is unchanged upon an exception to Undefined, Supervisor
222 // CPSR.A is set upon an exception to other modes
223 // See ARM DDI 0487E.a, pages G1-5515 to G1-5516
224 // See ARM DDI 0406C.d, page B1-1182
225 new |= (old & PSR_AA32_A_BIT);
226 if (mode != PSR_AA32_MODE_UND && mode != PSR_AA32_MODE_SVC)
227 new |= PSR_AA32_A_BIT;
229 // CPSR.I is set upon any exception
230 // See ARM DDI 0487E.a, pages G1-5515 to G1-5516
231 // See ARM DDI 0406C.d, page B1-1182
232 new |= PSR_AA32_I_BIT;
234 // CPSR.F is set upon an exception to FIQ
235 // CPSR.F is unchanged upon an exception to other modes
236 // See ARM DDI 0487E.a, pages G1-5515 to G1-5516
237 // See ARM DDI 0406C.d, page B1-1182
238 new |= (old & PSR_AA32_F_BIT);
239 if (mode == PSR_AA32_MODE_FIQ)
240 new |= PSR_AA32_F_BIT;
242 // CPSR.T is set to SCTLR.TE upon any exception
243 // See ARM DDI 0487E.a, page G8-5514
244 // See ARM DDI 0406C.d, page B1-1181
246 new |= PSR_AA32_T_BIT;
254 * Table taken from ARMv8 ARM DDI0487B-B, table G1-10.
256 static const u8 return_offsets[8][2] = {
257 [0] = { 0, 0 }, /* Reset, unused */
258 [1] = { 4, 2 }, /* Undefined */
259 [2] = { 0, 0 }, /* SVC, unused */
260 [3] = { 4, 4 }, /* Prefetch abort */
261 [4] = { 8, 8 }, /* Data abort */
262 [5] = { 0, 0 }, /* HVC, unused */
263 [6] = { 4, 4 }, /* IRQ, unused */
264 [7] = { 4, 4 }, /* FIQ, unused */
267 static void enter_exception32(struct kvm_vcpu *vcpu, u32 mode, u32 vect_offset)
269 unsigned long spsr = *vcpu_cpsr(vcpu);
270 bool is_thumb = (spsr & PSR_AA32_T_BIT);
271 u32 sctlr = __vcpu_read_sys_reg(vcpu, SCTLR_EL1);
274 *vcpu_cpsr(vcpu) = get_except32_cpsr(vcpu, mode);
275 return_address = *vcpu_pc(vcpu);
276 return_address += return_offsets[vect_offset >> 2][is_thumb];
278 /* KVM only enters the ABT and UND modes, so only deal with those */
280 case PSR_AA32_MODE_ABT:
281 __vcpu_write_spsr_abt(vcpu, host_spsr_to_spsr32(spsr));
282 vcpu_gp_regs(vcpu)->compat_lr_abt = return_address;
285 case PSR_AA32_MODE_UND:
286 __vcpu_write_spsr_und(vcpu, host_spsr_to_spsr32(spsr));
287 vcpu_gp_regs(vcpu)->compat_lr_und = return_address;
291 /* Branch to exception vector */
292 if (sctlr & (1 << 13))
293 vect_offset += 0xffff0000;
294 else /* always have security exceptions */
295 vect_offset += __vcpu_read_sys_reg(vcpu, VBAR_EL1);
297 *vcpu_pc(vcpu) = vect_offset;
300 static void kvm_inject_exception(struct kvm_vcpu *vcpu)
302 if (vcpu_el1_is_32bit(vcpu)) {
303 switch (vcpu->arch.flags & KVM_ARM64_EXCEPT_MASK) {
304 case KVM_ARM64_EXCEPT_AA32_UND:
305 enter_exception32(vcpu, PSR_AA32_MODE_UND, 4);
307 case KVM_ARM64_EXCEPT_AA32_IABT:
308 enter_exception32(vcpu, PSR_AA32_MODE_ABT, 12);
310 case KVM_ARM64_EXCEPT_AA32_DABT:
311 enter_exception32(vcpu, PSR_AA32_MODE_ABT, 16);
318 switch (vcpu->arch.flags & KVM_ARM64_EXCEPT_MASK) {
319 case (KVM_ARM64_EXCEPT_AA64_ELx_SYNC |
320 KVM_ARM64_EXCEPT_AA64_EL1):
321 enter_exception64(vcpu, PSR_MODE_EL1h, except_type_sync);
325 * Only EL1_SYNC makes sense so far, EL2_{SYNC,IRQ}
326 * will be implemented at some point. Everything
327 * else gets silently ignored.
335 * Adjust the guest PC (and potentially exception state) depending on
336 * flags provided by the emulation code.
338 void __kvm_adjust_pc(struct kvm_vcpu *vcpu)
340 if (vcpu->arch.flags & KVM_ARM64_PENDING_EXCEPTION) {
341 kvm_inject_exception(vcpu);
342 vcpu->arch.flags &= ~(KVM_ARM64_PENDING_EXCEPTION |
343 KVM_ARM64_EXCEPT_MASK);
344 } else if (vcpu->arch.flags & KVM_ARM64_INCREMENT_PC) {
345 kvm_skip_instr(vcpu);
346 vcpu->arch.flags &= ~KVM_ARM64_INCREMENT_PC;