arch/arm64/kernel/traps.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Based on arch/arm/kernel/traps.c
   4  *
   5  * Copyright (C) 1995-2009 Russell King
   6  * Copyright (C) 2012 ARM Ltd.
   7  */
   8
   9 #include <linux/bug.h>
  10 #include <linux/context_tracking.h>
  11 #include <linux/signal.h>
  12 #include <linux/kallsyms.h>
  13 #include <linux/kprobes.h>
  14 #include <linux/spinlock.h>
  15 #include <linux/uaccess.h>
  16 #include <linux/hardirq.h>
  17 #include <linux/kdebug.h>
  18 #include <linux/module.h>
  19 #include <linux/kexec.h>
  20 #include <linux/delay.h>
  21 #include <linux/efi.h>
  22 #include <linux/init.h>
  23 #include <linux/sched/signal.h>
  24 #include <linux/sched/debug.h>
  25 #include <linux/sched/task_stack.h>
  26 #include <linux/sizes.h>
  27 #include <linux/syscalls.h>
  28 #include <linux/mm_types.h>
  29 #include <linux/kasan.h>
  30 #include <linux/ubsan.h>
  31 #include <linux/cfi.h>
  32
  33 #include <asm/atomic.h>
  34 #include <asm/bug.h>
  35 #include <asm/cpufeature.h>
  36 #include <asm/daifflags.h>
  37 #include <asm/debug-monitors.h>
  38 #include <asm/efi.h>
  39 #include <asm/esr.h>
  40 #include <asm/exception.h>
  41 #include <asm/extable.h>
  42 #include <asm/insn.h>
  43 #include <asm/kprobes.h>
  44 #include <asm/patching.h>
  45 #include <asm/traps.h>
  46 #include <asm/smp.h>
  47 #include <asm/stack_pointer.h>
  48 #include <asm/stacktrace.h>
  49 #include <asm/system_misc.h>
  50 #include <asm/sysreg.h>
  51
  52 static bool __kprobes __check_eq(unsigned long pstate)
  53 {
  54         return (pstate & PSR_Z_BIT) != 0;
  55 }
  56
  57 static bool __kprobes __check_ne(unsigned long pstate)
  58 {
  59         return (pstate & PSR_Z_BIT) == 0;
  60 }
  61
  62 static bool __kprobes __check_cs(unsigned long pstate)
  63 {
  64         return (pstate & PSR_C_BIT) != 0;
  65 }
  66
  67 static bool __kprobes __check_cc(unsigned long pstate)
  68 {
  69         return (pstate & PSR_C_BIT) == 0;
  70 }
  71
  72 static bool __kprobes __check_mi(unsigned long pstate)
  73 {
  74         return (pstate & PSR_N_BIT) != 0;
  75 }
  76
  77 static bool __kprobes __check_pl(unsigned long pstate)
  78 {
  79         return (pstate & PSR_N_BIT) == 0;
  80 }
  81
  82 static bool __kprobes __check_vs(unsigned long pstate)
  83 {
  84         return (pstate & PSR_V_BIT) != 0;
  85 }
  86
  87 static bool __kprobes __check_vc(unsigned long pstate)
  88 {
  89         return (pstate & PSR_V_BIT) == 0;
  90 }
  91
  92 static bool __kprobes __check_hi(unsigned long pstate)
  93 {
  94         pstate &= ~(pstate >> 1);       /* PSR_C_BIT &= ~PSR_Z_BIT */
  95         return (pstate & PSR_C_BIT) != 0;
  96 }
  97
  98 static bool __kprobes __check_ls(unsigned long pstate)
  99 {
 100         pstate &= ~(pstate >> 1);       /* PSR_C_BIT &= ~PSR_Z_BIT */
 101         return (pstate & PSR_C_BIT) == 0;
 102 }
 103
 104 static bool __kprobes __check_ge(unsigned long pstate)
 105 {
 106         pstate ^= (pstate << 3);        /* PSR_N_BIT ^= PSR_V_BIT */
 107         return (pstate & PSR_N_BIT) == 0;
 108 }
 109
 110 static bool __kprobes __check_lt(unsigned long pstate)
 111 {
 112         pstate ^= (pstate << 3);        /* PSR_N_BIT ^= PSR_V_BIT */
 113         return (pstate & PSR_N_BIT) != 0;
 114 }
 115
 116 static bool __kprobes __check_gt(unsigned long pstate)
 117 {
 118         /*PSR_N_BIT ^= PSR_V_BIT */
 119         unsigned long temp = pstate ^ (pstate << 3);
 120
 121         temp |= (pstate << 1);  /*PSR_N_BIT |= PSR_Z_BIT */
 122         return (temp & PSR_N_BIT) == 0;
 123 }
 124
 125 static bool __kprobes __check_le(unsigned long pstate)
 126 {
 127         /*PSR_N_BIT ^= PSR_V_BIT */
 128         unsigned long temp = pstate ^ (pstate << 3);
 129
 130         temp |= (pstate << 1);  /*PSR_N_BIT |= PSR_Z_BIT */
 131         return (temp & PSR_N_BIT) != 0;
 132 }
 133
 134 static bool __kprobes __check_al(unsigned long pstate)
 135 {
 136         return true;
 137 }
 138
 139 /*
 140  * Note that the ARMv8 ARM calls condition code 0b1111 "nv", but states that
 141  * it behaves identically to 0b1110 ("al").
 142  */
 143 pstate_check_t * const aarch32_opcode_cond_checks[16] = {
 144         __check_eq, __check_ne, __check_cs, __check_cc,
 145         __check_mi, __check_pl, __check_vs, __check_vc,
 146         __check_hi, __check_ls, __check_ge, __check_lt,
 147         __check_gt, __check_le, __check_al, __check_al
 148 };
 149
 150 int show_unhandled_signals = 0;
 151
 152 static void dump_kernel_instr(const char *lvl, struct pt_regs *regs)
 153 {
 154         unsigned long addr = instruction_pointer(regs);
 155         char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str;
 156         int i;
 157
 158         if (user_mode(regs))
 159                 return;
 160
 161         for (i = -4; i < 1; i++) {
 162                 unsigned int val, bad;
 163
 164                 bad = aarch64_insn_read(&((u32 *)addr)[i], &val);
 165
 166                 if (!bad)
 167                         p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val);
 168                 else
 169                         p += sprintf(p, i == 0 ? "(????????) " : "???????? ");
 170         }
 171
 172         printk("%sCode: %s\n", lvl, str);
 173 }
 174
 175 #ifdef CONFIG_PREEMPT
 176 #define S_PREEMPT " PREEMPT"
 177 #elif defined(CONFIG_PREEMPT_RT)
 178 #define S_PREEMPT " PREEMPT_RT"
 179 #else
 180 #define S_PREEMPT ""
 181 #endif
 182
 183 #define S_SMP " SMP"
 184
 185 static int __die(const char *str, long err, struct pt_regs *regs)
 186 {
 187         static int die_counter;
 188         int ret;
 189
 190         pr_emerg("Internal error: %s: %016lx [#%d]" S_PREEMPT S_SMP "\n",
 191                  str, err, ++die_counter);
 192
 193         /* trap and error numbers are mostly meaningless on ARM */
 194         ret = notify_die(DIE_OOPS, str, regs, err, 0, SIGSEGV);
 195         if (ret == NOTIFY_STOP)
 196                 return ret;
 197
 198         print_modules();
 199         show_regs(regs);
 200
 201         dump_kernel_instr(KERN_EMERG, regs);
 202
 203         return ret;
 204 }
 205
 206 static DEFINE_RAW_SPINLOCK(die_lock);
 207
 208 /*
 209  * This function is protected against re-entrancy.
 210  */
 211 void die(const char *str, struct pt_regs *regs, long err)
 212 {
 213         int ret;
 214         unsigned long flags;
 215
 216         raw_spin_lock_irqsave(&die_lock, flags);
 217
 218         oops_enter();
 219
 220         console_verbose();
 221         bust_spinlocks(1);
 222         ret = __die(str, err, regs);
 223
 224         if (regs && kexec_should_crash(current))
 225                 crash_kexec(regs);
 226
 227         bust_spinlocks(0);
 228         add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
 229         oops_exit();
 230
 231         if (in_interrupt())
 232                 panic("%s: Fatal exception in interrupt", str);
 233         if (panic_on_oops)
 234                 panic("%s: Fatal exception", str);
 235
 236         raw_spin_unlock_irqrestore(&die_lock, flags);
 237
 238         if (ret != NOTIFY_STOP)
 239                 make_task_dead(SIGSEGV);
 240 }
 241
 242 static void arm64_show_signal(int signo, const char *str)
 243 {
 244         static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,
 245                                       DEFAULT_RATELIMIT_BURST);
 246         struct task_struct *tsk = current;
 247         unsigned long esr = tsk->thread.fault_code;
 248         struct pt_regs *regs = task_pt_regs(tsk);
 249
 250         /* Leave if the signal won't be shown */
 251         if (!show_unhandled_signals ||
 252             !unhandled_signal(tsk, signo) ||
 253             !__ratelimit(&rs))
 254                 return;
 255
 256         pr_info("%s[%d]: unhandled exception: ", tsk->comm, task_pid_nr(tsk));
 257         if (esr)
 258                 pr_cont("%s, ESR 0x%016lx, ", esr_get_class_string(esr), esr);
 259
 260         pr_cont("%s", str);
 261         print_vma_addr(KERN_CONT " in ", regs->pc);
 262         pr_cont("\n");
 263         __show_regs(regs);
 264 }
 265
 266 void arm64_force_sig_fault(int signo, int code, unsigned long far,
 267                            const char *str)
 268 {
 269         arm64_show_signal(signo, str);
 270         if (signo == SIGKILL)
 271                 force_sig(SIGKILL);
 272         else
 273                 force_sig_fault(signo, code, (void __user *)far);
 274 }
 275
 276 void arm64_force_sig_mceerr(int code, unsigned long far, short lsb,
 277                             const char *str)
 278 {
 279         arm64_show_signal(SIGBUS, str);
 280         force_sig_mceerr(code, (void __user *)far, lsb);
 281 }
 282
 283 void arm64_force_sig_ptrace_errno_trap(int errno, unsigned long far,
 284                                        const char *str)
 285 {
 286         arm64_show_signal(SIGTRAP, str);
 287         force_sig_ptrace_errno_trap(errno, (void __user *)far);
 288 }
 289
 290 void arm64_notify_die(const char *str, struct pt_regs *regs,
 291                       int signo, int sicode, unsigned long far,
 292                       unsigned long err)
 293 {
 294         if (user_mode(regs)) {
 295                 WARN_ON(regs != current_pt_regs());
 296                 current->thread.fault_address = 0;
 297                 current->thread.fault_code = err;
 298
 299                 arm64_force_sig_fault(signo, sicode, far, str);
 300         } else {
 301                 die(str, regs, err);
 302         }
 303 }
 304
 305 #ifdef CONFIG_COMPAT
 306 #define PSTATE_IT_1_0_SHIFT     25
 307 #define PSTATE_IT_1_0_MASK      (0x3 << PSTATE_IT_1_0_SHIFT)
 308 #define PSTATE_IT_7_2_SHIFT     10
 309 #define PSTATE_IT_7_2_MASK      (0x3f << PSTATE_IT_7_2_SHIFT)
 310
 311 static u32 compat_get_it_state(struct pt_regs *regs)
 312 {
 313         u32 it, pstate = regs->pstate;
 314
 315         it  = (pstate & PSTATE_IT_1_0_MASK) >> PSTATE_IT_1_0_SHIFT;
 316         it |= ((pstate & PSTATE_IT_7_2_MASK) >> PSTATE_IT_7_2_SHIFT) << 2;
 317
 318         return it;
 319 }
 320
 321 static void compat_set_it_state(struct pt_regs *regs, u32 it)
 322 {
 323         u32 pstate_it;
 324
 325         pstate_it  = (it << PSTATE_IT_1_0_SHIFT) & PSTATE_IT_1_0_MASK;
 326         pstate_it |= ((it >> 2) << PSTATE_IT_7_2_SHIFT) & PSTATE_IT_7_2_MASK;
 327
 328         regs->pstate &= ~PSR_AA32_IT_MASK;
 329         regs->pstate |= pstate_it;
 330 }
 331
 332 static void advance_itstate(struct pt_regs *regs)
 333 {
 334         u32 it;
 335
 336         /* ARM mode */
 337         if (!(regs->pstate & PSR_AA32_T_BIT) ||
 338             !(regs->pstate & PSR_AA32_IT_MASK))
 339                 return;
 340
 341         it  = compat_get_it_state(regs);
 342
 343         /*
 344          * If this is the last instruction of the block, wipe the IT
 345          * state. Otherwise advance it.
 346          */
 347         if (!(it & 7))
 348                 it = 0;
 349         else
 350                 it = (it & 0xe0) | ((it << 1) & 0x1f);
 351
 352         compat_set_it_state(regs, it);
 353 }
 354 #else
 355 static void advance_itstate(struct pt_regs *regs)
 356 {
 357 }
 358 #endif
 359
 360 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size)
 361 {
 362         regs->pc += size;
 363
 364         /*
 365          * If we were single stepping, we want to get the step exception after
 366          * we return from the trap.
 367          */
 368         if (user_mode(regs))
 369                 user_fastforward_single_step(current);
 370
 371         if (compat_user_mode(regs))
 372                 advance_itstate(regs);
 373         else
 374                 regs->pstate &= ~PSR_BTYPE_MASK;
 375 }
 376
 377 static int user_insn_read(struct pt_regs *regs, u32 *insnp)
 378 {
 379         u32 instr;
 380         unsigned long pc = instruction_pointer(regs);
 381
 382         if (compat_thumb_mode(regs)) {
 383                 /* 16-bit Thumb instruction */
 384                 __le16 instr_le;
 385                 if (get_user(instr_le, (__le16 __user *)pc))
 386                         return -EFAULT;
 387                 instr = le16_to_cpu(instr_le);
 388                 if (aarch32_insn_is_wide(instr)) {
 389                         u32 instr2;
 390
 391                         if (get_user(instr_le, (__le16 __user *)(pc + 2)))
 392                                 return -EFAULT;
 393                         instr2 = le16_to_cpu(instr_le);
 394                         instr = (instr << 16) | instr2;
 395                 }
 396         } else {
 397                 /* 32-bit ARM instruction */
 398                 __le32 instr_le;
 399                 if (get_user(instr_le, (__le32 __user *)pc))
 400                         return -EFAULT;
 401                 instr = le32_to_cpu(instr_le);
 402         }
 403
 404         *insnp = instr;
 405         return 0;
 406 }
 407
 408 void force_signal_inject(int signal, int code, unsigned long address, unsigned long err)
 409 {
 410         const char *desc;
 411         struct pt_regs *regs = current_pt_regs();
 412
 413         if (WARN_ON(!user_mode(regs)))
 414                 return;
 415
 416         switch (signal) {
 417         case SIGILL:
 418                 desc = "undefined instruction";
 419                 break;
 420         case SIGSEGV:
 421                 desc = "illegal memory access";
 422                 break;
 423         default:
 424                 desc = "unknown or unrecoverable error";
 425                 break;
 426         }
 427
 428         /* Force signals we don't understand to SIGKILL */
 429         if (WARN_ON(signal != SIGKILL &&
 430                     siginfo_layout(signal, code) != SIL_FAULT)) {
 431                 signal = SIGKILL;
 432         }
 433
 434         arm64_notify_die(desc, regs, signal, code, address, err);
 435 }
 436
 437 /*
 438  * Set up process info to signal segmentation fault - called on access error.
 439  */
 440 void arm64_notify_segfault(unsigned long addr)
 441 {
 442         int code;
 443
 444         mmap_read_lock(current->mm);
 445         if (find_vma(current->mm, untagged_addr(addr)) == NULL)
 446                 code = SEGV_MAPERR;
 447         else
 448                 code = SEGV_ACCERR;
 449         mmap_read_unlock(current->mm);
 450
 451         force_signal_inject(SIGSEGV, code, addr, 0);
 452 }
 453
 454 void do_el0_undef(struct pt_regs *regs, unsigned long esr)
 455 {
 456         u32 insn;
 457
 458         /* check for AArch32 breakpoint instructions */
 459         if (!aarch32_break_handler(regs))
 460                 return;
 461
 462         if (user_insn_read(regs, &insn))
 463                 goto out_err;
 464
 465         if (try_emulate_mrs(regs, insn))
 466                 return;
 467
 468         if (try_emulate_armv8_deprecated(regs, insn))
 469                 return;
 470
 471 out_err:
 472         force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
 473 }
 474
 475 void do_el1_undef(struct pt_regs *regs, unsigned long esr)
 476 {
 477         u32 insn;
 478
 479         if (aarch64_insn_read((void *)regs->pc, &insn))
 480                 goto out_err;
 481
 482         if (try_emulate_el1_ssbs(regs, insn))
 483                 return;
 484
 485 out_err:
 486         die("Oops - Undefined instruction", regs, esr);
 487 }
 488
 489 void do_el0_bti(struct pt_regs *regs)
 490 {
 491         force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
 492 }
 493
 494 void do_el1_bti(struct pt_regs *regs, unsigned long esr)
 495 {
 496         if (efi_runtime_fixup_exception(regs, "BTI violation")) {
 497                 regs->pstate &= ~PSR_BTYPE_MASK;
 498                 return;
 499         }
 500         die("Oops - BTI", regs, esr);
 501 }
 502
 503 void do_el0_fpac(struct pt_regs *regs, unsigned long esr)
 504 {
 505         force_signal_inject(SIGILL, ILL_ILLOPN, regs->pc, esr);
 506 }
 507
 508 void do_el1_fpac(struct pt_regs *regs, unsigned long esr)
 509 {
 510         /*
 511          * Unexpected FPAC exception in the kernel: kill the task before it
 512          * does any more harm.
 513          */
 514         die("Oops - FPAC", regs, esr);
 515 }
 516
 517 void do_el0_mops(struct pt_regs *regs, unsigned long esr)
 518 {
 519         bool wrong_option = esr & ESR_ELx_MOPS_ISS_WRONG_OPTION;
 520         bool option_a = esr & ESR_ELx_MOPS_ISS_OPTION_A;
 521         int dstreg = ESR_ELx_MOPS_ISS_DESTREG(esr);
 522         int srcreg = ESR_ELx_MOPS_ISS_SRCREG(esr);
 523         int sizereg = ESR_ELx_MOPS_ISS_SIZEREG(esr);
 524         unsigned long dst, src, size;
 525
 526         dst = pt_regs_read_reg(regs, dstreg);
 527         src = pt_regs_read_reg(regs, srcreg);
 528         size = pt_regs_read_reg(regs, sizereg);
 529
 530         /*
 531          * Put the registers back in the original format suitable for a
 532          * prologue instruction, using the generic return routine from the
 533          * Arm ARM (DDI 0487I.a) rules CNTMJ and MWFQH.
 534          */
 535         if (esr & ESR_ELx_MOPS_ISS_MEM_INST) {
 536                 /* SET* instruction */
 537                 if (option_a ^ wrong_option) {
 538                         /* Format is from Option A; forward set */
 539                         pt_regs_write_reg(regs, dstreg, dst + size);
 540                         pt_regs_write_reg(regs, sizereg, -size);
 541                 }
 542         } else {
 543                 /* CPY* instruction */
 544                 if (!(option_a ^ wrong_option)) {
 545                         /* Format is from Option B */
 546                         if (regs->pstate & PSR_N_BIT) {
 547                                 /* Backward copy */
 548                                 pt_regs_write_reg(regs, dstreg, dst - size);
 549                                 pt_regs_write_reg(regs, srcreg, src - size);
 550                         }
 551                 } else {
 552                         /* Format is from Option A */
 553                         if (size & BIT(63)) {
 554                                 /* Forward copy */
 555                                 pt_regs_write_reg(regs, dstreg, dst + size);
 556                                 pt_regs_write_reg(regs, srcreg, src + size);
 557                                 pt_regs_write_reg(regs, sizereg, -size);
 558                         }
 559                 }
 560         }
 561
 562         if (esr & ESR_ELx_MOPS_ISS_FROM_EPILOGUE)
 563                 regs->pc -= 8;
 564         else
 565                 regs->pc -= 4;
 566
 567         /*
 568          * If single stepping then finish the step before executing the
 569          * prologue instruction.
 570          */
 571         user_fastforward_single_step(current);
 572 }
 573
 574 #define __user_cache_maint(insn, address, res)                  \
 575         if (address >= TASK_SIZE_MAX) {                         \
 576                 res = -EFAULT;                                  \
 577         } else {                                                \
 578                 uaccess_ttbr0_enable();                         \
 579                 asm volatile (                                  \
 580                         "1:     " insn ", %1\n"                 \
 581                         "       mov     %w0, #0\n"              \
 582                         "2:\n"                                  \
 583                         _ASM_EXTABLE_UACCESS_ERR(1b, 2b, %w0)   \
 584                         : "=r" (res)                            \
 585                         : "r" (address));                       \
 586                 uaccess_ttbr0_disable();                        \
 587         }
 588
 589 static void user_cache_maint_handler(unsigned long esr, struct pt_regs *regs)
 590 {
 591         unsigned long tagged_address, address;
 592         int rt = ESR_ELx_SYS64_ISS_RT(esr);
 593         int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT;
 594         int ret = 0;
 595
 596         tagged_address = pt_regs_read_reg(regs, rt);
 597         address = untagged_addr(tagged_address);
 598
 599         switch (crm) {
 600         case ESR_ELx_SYS64_ISS_CRM_DC_CVAU:     /* DC CVAU, gets promoted */
 601                 __user_cache_maint("dc civac", address, ret);
 602                 break;
 603         case ESR_ELx_SYS64_ISS_CRM_DC_CVAC:     /* DC CVAC, gets promoted */
 604                 __user_cache_maint("dc civac", address, ret);
 605                 break;
 606         case ESR_ELx_SYS64_ISS_CRM_DC_CVADP:    /* DC CVADP */
 607                 __user_cache_maint("sys 3, c7, c13, 1", address, ret);
 608                 break;
 609         case ESR_ELx_SYS64_ISS_CRM_DC_CVAP:     /* DC CVAP */
 610                 __user_cache_maint("sys 3, c7, c12, 1", address, ret);
 611                 break;
 612         case ESR_ELx_SYS64_ISS_CRM_DC_CIVAC:    /* DC CIVAC */
 613                 __user_cache_maint("dc civac", address, ret);
 614                 break;
 615         case ESR_ELx_SYS64_ISS_CRM_IC_IVAU:     /* IC IVAU */
 616                 __user_cache_maint("ic ivau", address, ret);
 617                 break;
 618         default:
 619                 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
 620                 return;
 621         }
 622
 623         if (ret)
 624                 arm64_notify_segfault(tagged_address);
 625         else
 626                 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 627 }
 628
 629 static void ctr_read_handler(unsigned long esr, struct pt_regs *regs)
 630 {
 631         int rt = ESR_ELx_SYS64_ISS_RT(esr);
 632         unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0);
 633
 634         if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) {
 635                 /* Hide DIC so that we can trap the unnecessary maintenance...*/
 636                 val &= ~BIT(CTR_EL0_DIC_SHIFT);
 637
 638                 /* ... and fake IminLine to reduce the number of traps. */
 639                 val &= ~CTR_EL0_IminLine_MASK;
 640                 val |= (PAGE_SHIFT - 2) & CTR_EL0_IminLine_MASK;
 641         }
 642
 643         pt_regs_write_reg(regs, rt, val);
 644
 645         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 646 }
 647
 648 static void cntvct_read_handler(unsigned long esr, struct pt_regs *regs)
 649 {
 650         int rt = ESR_ELx_SYS64_ISS_RT(esr);
 651
 652         pt_regs_write_reg(regs, rt, arch_timer_read_counter());
 653         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 654 }
 655
 656 static void cntfrq_read_handler(unsigned long esr, struct pt_regs *regs)
 657 {
 658         int rt = ESR_ELx_SYS64_ISS_RT(esr);
 659
 660         pt_regs_write_reg(regs, rt, arch_timer_get_rate());
 661         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 662 }
 663
 664 static void mrs_handler(unsigned long esr, struct pt_regs *regs)
 665 {
 666         u32 sysreg, rt;
 667
 668         rt = ESR_ELx_SYS64_ISS_RT(esr);
 669         sysreg = esr_sys64_to_sysreg(esr);
 670
 671         if (do_emulate_mrs(regs, sysreg, rt) != 0)
 672                 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
 673 }
 674
 675 static void wfi_handler(unsigned long esr, struct pt_regs *regs)
 676 {
 677         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 678 }
 679
 680 struct sys64_hook {
 681         unsigned long esr_mask;
 682         unsigned long esr_val;
 683         void (*handler)(unsigned long esr, struct pt_regs *regs);
 684 };
 685
 686 static const struct sys64_hook sys64_hooks[] = {
 687         {
 688                 .esr_mask = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK,
 689                 .esr_val = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL,
 690                 .handler = user_cache_maint_handler,
 691         },
 692         {
 693                 /* Trap read access to CTR_EL0 */
 694                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
 695                 .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ,
 696                 .handler = ctr_read_handler,
 697         },
 698         {
 699                 /* Trap read access to CNTVCT_EL0 */
 700                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
 701                 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT,
 702                 .handler = cntvct_read_handler,
 703         },
 704         {
 705                 /* Trap read access to CNTVCTSS_EL0 */
 706                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
 707                 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCTSS,
 708                 .handler = cntvct_read_handler,
 709         },
 710         {
 711                 /* Trap read access to CNTFRQ_EL0 */
 712                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
 713                 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTFRQ,
 714                 .handler = cntfrq_read_handler,
 715         },
 716         {
 717                 /* Trap read access to CPUID registers */
 718                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK,
 719                 .esr_val = ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL,
 720                 .handler = mrs_handler,
 721         },
 722         {
 723                 /* Trap WFI instructions executed in userspace */
 724                 .esr_mask = ESR_ELx_WFx_MASK,
 725                 .esr_val = ESR_ELx_WFx_WFI_VAL,
 726                 .handler = wfi_handler,
 727         },
 728         {},
 729 };
 730
 731 #ifdef CONFIG_COMPAT
 732 static bool cp15_cond_valid(unsigned long esr, struct pt_regs *regs)
 733 {
 734         int cond;
 735
 736         /* Only a T32 instruction can trap without CV being set */
 737         if (!(esr & ESR_ELx_CV)) {
 738                 u32 it;
 739
 740                 it = compat_get_it_state(regs);
 741                 if (!it)
 742                         return true;
 743
 744                 cond = it >> 4;
 745         } else {
 746                 cond = (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT;
 747         }
 748
 749         return aarch32_opcode_cond_checks[cond](regs->pstate);
 750 }
 751
 752 static void compat_cntfrq_read_handler(unsigned long esr, struct pt_regs *regs)
 753 {
 754         int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT;
 755
 756         pt_regs_write_reg(regs, reg, arch_timer_get_rate());
 757         arm64_skip_faulting_instruction(regs, 4);
 758 }
 759
 760 static const struct sys64_hook cp15_32_hooks[] = {
 761         {
 762                 .esr_mask = ESR_ELx_CP15_32_ISS_SYS_MASK,
 763                 .esr_val = ESR_ELx_CP15_32_ISS_SYS_CNTFRQ,
 764                 .handler = compat_cntfrq_read_handler,
 765         },
 766         {},
 767 };
 768
 769 static void compat_cntvct_read_handler(unsigned long esr, struct pt_regs *regs)
 770 {
 771         int rt = (esr & ESR_ELx_CP15_64_ISS_RT_MASK) >> ESR_ELx_CP15_64_ISS_RT_SHIFT;
 772         int rt2 = (esr & ESR_ELx_CP15_64_ISS_RT2_MASK) >> ESR_ELx_CP15_64_ISS_RT2_SHIFT;
 773         u64 val = arch_timer_read_counter();
 774
 775         pt_regs_write_reg(regs, rt, lower_32_bits(val));
 776         pt_regs_write_reg(regs, rt2, upper_32_bits(val));
 777         arm64_skip_faulting_instruction(regs, 4);
 778 }
 779
 780 static const struct sys64_hook cp15_64_hooks[] = {
 781         {
 782                 .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK,
 783                 .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCT,
 784                 .handler = compat_cntvct_read_handler,
 785         },
 786         {
 787                 .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK,
 788                 .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS,
 789                 .handler = compat_cntvct_read_handler,
 790         },
 791         {},
 792 };
 793
 794 void do_el0_cp15(unsigned long esr, struct pt_regs *regs)
 795 {
 796         const struct sys64_hook *hook, *hook_base;
 797
 798         if (!cp15_cond_valid(esr, regs)) {
 799                 /*
 800                  * There is no T16 variant of a CP access, so we
 801                  * always advance PC by 4 bytes.
 802                  */
 803                 arm64_skip_faulting_instruction(regs, 4);
 804                 return;
 805         }
 806
 807         switch (ESR_ELx_EC(esr)) {
 808         case ESR_ELx_EC_CP15_32:
 809                 hook_base = cp15_32_hooks;
 810                 break;
 811         case ESR_ELx_EC_CP15_64:
 812                 hook_base = cp15_64_hooks;
 813                 break;
 814         default:
 815                 do_el0_undef(regs, esr);
 816                 return;
 817         }
 818
 819         for (hook = hook_base; hook->handler; hook++)
 820                 if ((hook->esr_mask & esr) == hook->esr_val) {
 821                         hook->handler(esr, regs);
 822                         return;
 823                 }
 824
 825         /*
 826          * New cp15 instructions may previously have been undefined at
 827          * EL0. Fall back to our usual undefined instruction handler
 828          * so that we handle these consistently.
 829          */
 830         do_el0_undef(regs, esr);
 831 }
 832 #endif
 833
 834 void do_el0_sys(unsigned long esr, struct pt_regs *regs)
 835 {
 836         const struct sys64_hook *hook;
 837
 838         for (hook = sys64_hooks; hook->handler; hook++)
 839                 if ((hook->esr_mask & esr) == hook->esr_val) {
 840                         hook->handler(esr, regs);
 841                         return;
 842                 }
 843
 844         /*
 845          * New SYS instructions may previously have been undefined at EL0. Fall
 846          * back to our usual undefined instruction handler so that we handle
 847          * these consistently.
 848          */
 849         do_el0_undef(regs, esr);
 850 }
 851
 852 static const char *esr_class_str[] = {
 853         [0 ... ESR_ELx_EC_MAX]          = "UNRECOGNIZED EC",
 854         [ESR_ELx_EC_UNKNOWN]            = "Unknown/Uncategorized",
 855         [ESR_ELx_EC_WFx]                = "WFI/WFE",
 856         [ESR_ELx_EC_CP15_32]            = "CP15 MCR/MRC",
 857         [ESR_ELx_EC_CP15_64]            = "CP15 MCRR/MRRC",
 858         [ESR_ELx_EC_CP14_MR]            = "CP14 MCR/MRC",
 859         [ESR_ELx_EC_CP14_LS]            = "CP14 LDC/STC",
 860         [ESR_ELx_EC_FP_ASIMD]           = "ASIMD",
 861         [ESR_ELx_EC_CP10_ID]            = "CP10 MRC/VMRS",
 862         [ESR_ELx_EC_PAC]                = "PAC",
 863         [ESR_ELx_EC_CP14_64]            = "CP14 MCRR/MRRC",
 864         [ESR_ELx_EC_BTI]                = "BTI",
 865         [ESR_ELx_EC_ILL]                = "PSTATE.IL",
 866         [ESR_ELx_EC_SVC32]              = "SVC (AArch32)",
 867         [ESR_ELx_EC_HVC32]              = "HVC (AArch32)",
 868         [ESR_ELx_EC_SMC32]              = "SMC (AArch32)",
 869         [ESR_ELx_EC_SVC64]              = "SVC (AArch64)",
 870         [ESR_ELx_EC_HVC64]              = "HVC (AArch64)",
 871         [ESR_ELx_EC_SMC64]              = "SMC (AArch64)",
 872         [ESR_ELx_EC_SYS64]              = "MSR/MRS (AArch64)",
 873         [ESR_ELx_EC_SVE]                = "SVE",
 874         [ESR_ELx_EC_ERET]               = "ERET/ERETAA/ERETAB",
 875         [ESR_ELx_EC_FPAC]               = "FPAC",
 876         [ESR_ELx_EC_SME]                = "SME",
 877         [ESR_ELx_EC_IMP_DEF]            = "EL3 IMP DEF",
 878         [ESR_ELx_EC_IABT_LOW]           = "IABT (lower EL)",
 879         [ESR_ELx_EC_IABT_CUR]           = "IABT (current EL)",
 880         [ESR_ELx_EC_PC_ALIGN]           = "PC Alignment",
 881         [ESR_ELx_EC_DABT_LOW]           = "DABT (lower EL)",
 882         [ESR_ELx_EC_DABT_CUR]           = "DABT (current EL)",
 883         [ESR_ELx_EC_SP_ALIGN]           = "SP Alignment",
 884         [ESR_ELx_EC_MOPS]               = "MOPS",
 885         [ESR_ELx_EC_FP_EXC32]           = "FP (AArch32)",
 886         [ESR_ELx_EC_FP_EXC64]           = "FP (AArch64)",
 887         [ESR_ELx_EC_SERROR]             = "SError",
 888         [ESR_ELx_EC_BREAKPT_LOW]        = "Breakpoint (lower EL)",
 889         [ESR_ELx_EC_BREAKPT_CUR]        = "Breakpoint (current EL)",
 890         [ESR_ELx_EC_SOFTSTP_LOW]        = "Software Step (lower EL)",
 891         [ESR_ELx_EC_SOFTSTP_CUR]        = "Software Step (current EL)",
 892         [ESR_ELx_EC_WATCHPT_LOW]        = "Watchpoint (lower EL)",
 893         [ESR_ELx_EC_WATCHPT_CUR]        = "Watchpoint (current EL)",
 894         [ESR_ELx_EC_BKPT32]             = "BKPT (AArch32)",
 895         [ESR_ELx_EC_VECTOR32]           = "Vector catch (AArch32)",
 896         [ESR_ELx_EC_BRK64]              = "BRK (AArch64)",
 897 };
 898
 899 const char *esr_get_class_string(unsigned long esr)
 900 {
 901         return esr_class_str[ESR_ELx_EC(esr)];
 902 }
 903
 904 /*
 905  * bad_el0_sync handles unexpected, but potentially recoverable synchronous
 906  * exceptions taken from EL0.
 907  */
 908 void bad_el0_sync(struct pt_regs *regs, int reason, unsigned long esr)
 909 {
 910         unsigned long pc = instruction_pointer(regs);
 911
 912         current->thread.fault_address = 0;
 913         current->thread.fault_code = esr;
 914
 915         arm64_force_sig_fault(SIGILL, ILL_ILLOPC, pc,
 916                               "Bad EL0 synchronous exception");
 917 }
 918
 919 #ifdef CONFIG_VMAP_STACK
 920
 921 DEFINE_PER_CPU(unsigned long [OVERFLOW_STACK_SIZE/sizeof(long)], overflow_stack)
 922         __aligned(16);
 923
 924 void __noreturn panic_bad_stack(struct pt_regs *regs, unsigned long esr, unsigned long far)
 925 {
 926         unsigned long tsk_stk = (unsigned long)current->stack;
 927         unsigned long irq_stk = (unsigned long)this_cpu_read(irq_stack_ptr);
 928         unsigned long ovf_stk = (unsigned long)this_cpu_ptr(overflow_stack);
 929
 930         console_verbose();
 931         pr_emerg("Insufficient stack space to handle exception!");
 932
 933         pr_emerg("ESR: 0x%016lx -- %s\n", esr, esr_get_class_string(esr));
 934         pr_emerg("FAR: 0x%016lx\n", far);
 935
 936         pr_emerg("Task stack:     [0x%016lx..0x%016lx]\n",
 937                  tsk_stk, tsk_stk + THREAD_SIZE);
 938         pr_emerg("IRQ stack:      [0x%016lx..0x%016lx]\n",
 939                  irq_stk, irq_stk + IRQ_STACK_SIZE);
 940         pr_emerg("Overflow stack: [0x%016lx..0x%016lx]\n",
 941                  ovf_stk, ovf_stk + OVERFLOW_STACK_SIZE);
 942
 943         __show_regs(regs);
 944
 945         /*
 946          * We use nmi_panic to limit the potential for recusive overflows, and
 947          * to get a better stack trace.
 948          */
 949         nmi_panic(NULL, "kernel stack overflow");
 950         cpu_park_loop();
 951 }
 952 #endif
 953
 954 void __noreturn arm64_serror_panic(struct pt_regs *regs, unsigned long esr)
 955 {
 956         console_verbose();
 957
 958         pr_crit("SError Interrupt on CPU%d, code 0x%016lx -- %s\n",
 959                 smp_processor_id(), esr, esr_get_class_string(esr));
 960         if (regs)
 961                 __show_regs(regs);
 962
 963         nmi_panic(regs, "Asynchronous SError Interrupt");
 964
 965         cpu_park_loop();
 966 }
 967
 968 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned long esr)
 969 {
 970         unsigned long aet = arm64_ras_serror_get_severity(esr);
 971
 972         switch (aet) {
 973         case ESR_ELx_AET_CE:    /* corrected error */
 974         case ESR_ELx_AET_UEO:   /* restartable, not yet consumed */
 975                 /*
 976                  * The CPU can make progress. We may take UEO again as
 977                  * a more severe error.
 978                  */
 979                 return false;
 980
 981         case ESR_ELx_AET_UEU:   /* Uncorrected Unrecoverable */
 982         case ESR_ELx_AET_UER:   /* Uncorrected Recoverable */
 983                 /*
 984                  * The CPU can't make progress. The exception may have
 985                  * been imprecise.
 986                  *
 987                  * Neoverse-N1 #1349291 means a non-KVM SError reported as
 988                  * Unrecoverable should be treated as Uncontainable. We
 989                  * call arm64_serror_panic() in both cases.
 990                  */
 991                 return true;
 992
 993         case ESR_ELx_AET_UC:    /* Uncontainable or Uncategorized error */
 994         default:
 995                 /* Error has been silently propagated */
 996                 arm64_serror_panic(regs, esr);
 997         }
 998 }
 999
1000 void do_serror(struct pt_regs *regs, unsigned long esr)
1001 {
1002         /* non-RAS errors are not containable */
1003         if (!arm64_is_ras_serror(esr) || arm64_is_fatal_ras_serror(regs, esr))
1004                 arm64_serror_panic(regs, esr);
1005 }
1006
1007 /* GENERIC_BUG traps */
1008 #ifdef CONFIG_GENERIC_BUG
1009 int is_valid_bugaddr(unsigned long addr)
1010 {
1011         /*
1012          * bug_handler() only called for BRK #BUG_BRK_IMM.
1013          * So the answer is trivial -- any spurious instances with no
1014          * bug table entry will be rejected by report_bug() and passed
1015          * back to the debug-monitors code and handled as a fatal
1016          * unexpected debug exception.
1017          */
1018         return 1;
1019 }
1020 #endif
1021
1022 static int bug_handler(struct pt_regs *regs, unsigned long esr)
1023 {
1024         switch (report_bug(regs->pc, regs)) {
1025         case BUG_TRAP_TYPE_BUG:
1026                 die("Oops - BUG", regs, esr);
1027                 break;
1028
1029         case BUG_TRAP_TYPE_WARN:
1030                 break;
1031
1032         default:
1033                 /* unknown/unrecognised bug trap type */
1034                 return DBG_HOOK_ERROR;
1035         }
1036
1037         /* If thread survives, skip over the BUG instruction and continue: */
1038         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
1039         return DBG_HOOK_HANDLED;
1040 }
1041
1042 static struct break_hook bug_break_hook = {
1043         .fn = bug_handler,
1044         .imm = BUG_BRK_IMM,
1045 };
1046
1047 #ifdef CONFIG_CFI_CLANG
1048 static int cfi_handler(struct pt_regs *regs, unsigned long esr)
1049 {
1050         unsigned long target;
1051         u32 type;
1052
1053         target = pt_regs_read_reg(regs, FIELD_GET(CFI_BRK_IMM_TARGET, esr));
1054         type = (u32)pt_regs_read_reg(regs, FIELD_GET(CFI_BRK_IMM_TYPE, esr));
1055
1056         switch (report_cfi_failure(regs, regs->pc, &target, type)) {
1057         case BUG_TRAP_TYPE_BUG:
1058                 die("Oops - CFI", regs, esr);
1059                 break;
1060
1061         case BUG_TRAP_TYPE_WARN:
1062                 break;
1063
1064         default:
1065                 return DBG_HOOK_ERROR;
1066         }
1067
1068         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
1069         return DBG_HOOK_HANDLED;
1070 }
1071
1072 static struct break_hook cfi_break_hook = {
1073         .fn = cfi_handler,
1074         .imm = CFI_BRK_IMM_BASE,
1075         .mask = CFI_BRK_IMM_MASK,
1076 };
1077 #endif /* CONFIG_CFI_CLANG */
1078
1079 static int reserved_fault_handler(struct pt_regs *regs, unsigned long esr)
1080 {
1081         pr_err("%s generated an invalid instruction at %pS!\n",
1082                 "Kernel text patching",
1083                 (void *)instruction_pointer(regs));
1084
1085         /* We cannot handle this */
1086         return DBG_HOOK_ERROR;
1087 }
1088
1089 static struct break_hook fault_break_hook = {
1090         .fn = reserved_fault_handler,
1091         .imm = FAULT_BRK_IMM,
1092 };
1093
1094 #ifdef CONFIG_KASAN_SW_TAGS
1095
1096 #define KASAN_ESR_RECOVER       0x20
1097 #define KASAN_ESR_WRITE 0x10
1098 #define KASAN_ESR_SIZE_MASK     0x0f
1099 #define KASAN_ESR_SIZE(esr)     (1 << ((esr) & KASAN_ESR_SIZE_MASK))
1100
1101 static int kasan_handler(struct pt_regs *regs, unsigned long esr)
1102 {
1103         bool recover = esr & KASAN_ESR_RECOVER;
1104         bool write = esr & KASAN_ESR_WRITE;
1105         size_t size = KASAN_ESR_SIZE(esr);
1106         void *addr = (void *)regs->regs[0];
1107         u64 pc = regs->pc;
1108
1109         kasan_report(addr, size, write, pc);
1110
1111         /*
1112          * The instrumentation allows to control whether we can proceed after
1113          * a crash was detected. This is done by passing the -recover flag to
1114          * the compiler. Disabling recovery allows to generate more compact
1115          * code.
1116          *
1117          * Unfortunately disabling recovery doesn't work for the kernel right
1118          * now. KASAN reporting is disabled in some contexts (for example when
1119          * the allocator accesses slab object metadata; this is controlled by
1120          * current->kasan_depth). All these accesses are detected by the tool,
1121          * even though the reports for them are not printed.
1122          *
1123          * This is something that might be fixed at some point in the future.
1124          */
1125         if (!recover)
1126                 die("Oops - KASAN", regs, esr);
1127
1128         /* If thread survives, skip over the brk instruction and continue: */
1129         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
1130         return DBG_HOOK_HANDLED;
1131 }
1132
1133 static struct break_hook kasan_break_hook = {
1134         .fn     = kasan_handler,
1135         .imm    = KASAN_BRK_IMM,
1136         .mask   = KASAN_BRK_MASK,
1137 };
1138 #endif
1139
1140 #ifdef CONFIG_UBSAN_TRAP
1141 static int ubsan_handler(struct pt_regs *regs, unsigned long esr)
1142 {
1143         die(report_ubsan_failure(regs, esr & UBSAN_BRK_MASK), regs, esr);
1144         return DBG_HOOK_HANDLED;
1145 }
1146
1147 static struct break_hook ubsan_break_hook = {
1148         .fn     = ubsan_handler,
1149         .imm    = UBSAN_BRK_IMM,
1150         .mask   = UBSAN_BRK_MASK,
1151 };
1152 #endif
1153
1154 #define esr_comment(esr) ((esr) & ESR_ELx_BRK64_ISS_COMMENT_MASK)
1155
1156 /*
1157  * Initial handler for AArch64 BRK exceptions
1158  * This handler only used until debug_traps_init().
1159  */
1160 int __init early_brk64(unsigned long addr, unsigned long esr,
1161                 struct pt_regs *regs)
1162 {
1163 #ifdef CONFIG_CFI_CLANG
1164         if ((esr_comment(esr) & ~CFI_BRK_IMM_MASK) == CFI_BRK_IMM_BASE)
1165                 return cfi_handler(regs, esr) != DBG_HOOK_HANDLED;
1166 #endif
1167 #ifdef CONFIG_KASAN_SW_TAGS
1168         if ((esr_comment(esr) & ~KASAN_BRK_MASK) == KASAN_BRK_IMM)
1169                 return kasan_handler(regs, esr) != DBG_HOOK_HANDLED;
1170 #endif
1171 #ifdef CONFIG_UBSAN_TRAP
1172         if ((esr_comment(esr) & ~UBSAN_BRK_MASK) == UBSAN_BRK_IMM)
1173                 return ubsan_handler(regs, esr) != DBG_HOOK_HANDLED;
1174 #endif
1175         return bug_handler(regs, esr) != DBG_HOOK_HANDLED;
1176 }
1177
1178 void __init trap_init(void)
1179 {
1180         register_kernel_break_hook(&bug_break_hook);
1181 #ifdef CONFIG_CFI_CLANG
1182         register_kernel_break_hook(&cfi_break_hook);
1183 #endif
1184         register_kernel_break_hook(&fault_break_hook);
1185 #ifdef CONFIG_KASAN_SW_TAGS
1186         register_kernel_break_hook(&kasan_break_hook);
1187 #endif
1188 #ifdef CONFIG_UBSAN_TRAP
1189         register_kernel_break_hook(&ubsan_break_hook);
1190 #endif
1191         debug_traps_init();
1192 }