1 // SPDX-License-Identifier: GPL-2.0-only
3 * Based on arch/arm/kernel/traps.c
5 * Copyright (C) 1995-2009 Russell King
6 * Copyright (C) 2012 ARM Ltd.
10 #include <linux/context_tracking.h>
11 #include <linux/signal.h>
12 #include <linux/personality.h>
13 #include <linux/kallsyms.h>
14 #include <linux/kprobes.h>
15 #include <linux/spinlock.h>
16 #include <linux/uaccess.h>
17 #include <linux/hardirq.h>
18 #include <linux/kdebug.h>
19 #include <linux/module.h>
20 #include <linux/kexec.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/sched/signal.h>
24 #include <linux/sched/debug.h>
25 #include <linux/sched/task_stack.h>
26 #include <linux/sizes.h>
27 #include <linux/syscalls.h>
28 #include <linux/mm_types.h>
29 #include <linux/kasan.h>
31 #include <asm/atomic.h>
33 #include <asm/cpufeature.h>
34 #include <asm/daifflags.h>
35 #include <asm/debug-monitors.h>
38 #include <asm/kprobes.h>
39 #include <asm/traps.h>
41 #include <asm/stack_pointer.h>
42 #include <asm/stacktrace.h>
43 #include <asm/exception.h>
44 #include <asm/system_misc.h>
45 #include <asm/sysreg.h>
47 static const char *handler[]= {
54 int show_unhandled_signals = 0;
56 static void dump_backtrace_entry(unsigned long where, const char *loglvl)
58 printk("%s %pS\n", loglvl, (void *)where);
61 static void dump_kernel_instr(const char *lvl, struct pt_regs *regs)
63 unsigned long addr = instruction_pointer(regs);
64 char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str;
70 for (i = -4; i < 1; i++) {
71 unsigned int val, bad;
73 bad = aarch64_insn_read(&((u32 *)addr)[i], &val);
76 p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val);
78 p += sprintf(p, "bad PC value");
83 printk("%sCode: %s\n", lvl, str);
86 void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk,
89 struct stackframe frame;
92 pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk);
103 if (!try_get_task_stack(tsk))
106 if (tsk == current) {
107 start_backtrace(&frame,
108 (unsigned long)__builtin_frame_address(0),
109 (unsigned long)dump_backtrace);
112 * task blocked in __switch_to
114 start_backtrace(&frame,
115 thread_saved_fp(tsk),
116 thread_saved_pc(tsk));
119 printk("%sCall trace:\n", loglvl);
121 /* skip until specified stack frame */
123 dump_backtrace_entry(frame.pc, loglvl);
124 } else if (frame.fp == regs->regs[29]) {
127 * Mostly, this is the case where this function is
128 * called in panic/abort. As exception handler's
129 * stack frame does not contain the corresponding pc
130 * at which an exception has taken place, use regs->pc
133 dump_backtrace_entry(regs->pc, loglvl);
135 } while (!unwind_frame(tsk, &frame));
140 void show_stack(struct task_struct *tsk, unsigned long *sp, const char *loglvl)
142 dump_backtrace(NULL, tsk, loglvl);
146 #ifdef CONFIG_PREEMPT
147 #define S_PREEMPT " PREEMPT"
148 #elif defined(CONFIG_PREEMPT_RT)
149 #define S_PREEMPT " PREEMPT_RT"
156 static int __die(const char *str, int err, struct pt_regs *regs)
158 static int die_counter;
161 pr_emerg("Internal error: %s: %x [#%d]" S_PREEMPT S_SMP "\n",
162 str, err, ++die_counter);
164 /* trap and error numbers are mostly meaningless on ARM */
165 ret = notify_die(DIE_OOPS, str, regs, err, 0, SIGSEGV);
166 if (ret == NOTIFY_STOP)
172 dump_kernel_instr(KERN_EMERG, regs);
177 static DEFINE_RAW_SPINLOCK(die_lock);
180 * This function is protected against re-entrancy.
182 void die(const char *str, struct pt_regs *regs, int err)
187 raw_spin_lock_irqsave(&die_lock, flags);
193 ret = __die(str, err, regs);
195 if (regs && kexec_should_crash(current))
199 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
203 panic("Fatal exception in interrupt");
205 panic("Fatal exception");
207 raw_spin_unlock_irqrestore(&die_lock, flags);
209 if (ret != NOTIFY_STOP)
213 static void arm64_show_signal(int signo, const char *str)
215 static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,
216 DEFAULT_RATELIMIT_BURST);
217 struct task_struct *tsk = current;
218 unsigned int esr = tsk->thread.fault_code;
219 struct pt_regs *regs = task_pt_regs(tsk);
221 /* Leave if the signal won't be shown */
222 if (!show_unhandled_signals ||
223 !unhandled_signal(tsk, signo) ||
227 pr_info("%s[%d]: unhandled exception: ", tsk->comm, task_pid_nr(tsk));
229 pr_cont("%s, ESR 0x%08x, ", esr_get_class_string(esr), esr);
232 print_vma_addr(KERN_CONT " in ", regs->pc);
237 void arm64_force_sig_fault(int signo, int code, void __user *addr,
240 arm64_show_signal(signo, str);
241 if (signo == SIGKILL)
244 force_sig_fault(signo, code, addr);
247 void arm64_force_sig_mceerr(int code, void __user *addr, short lsb,
250 arm64_show_signal(SIGBUS, str);
251 force_sig_mceerr(code, addr, lsb);
254 void arm64_force_sig_ptrace_errno_trap(int errno, void __user *addr,
257 arm64_show_signal(SIGTRAP, str);
258 force_sig_ptrace_errno_trap(errno, addr);
261 void arm64_notify_die(const char *str, struct pt_regs *regs,
262 int signo, int sicode, void __user *addr,
265 if (user_mode(regs)) {
266 WARN_ON(regs != current_pt_regs());
267 current->thread.fault_address = 0;
268 current->thread.fault_code = err;
270 arm64_force_sig_fault(signo, sicode, addr, str);
277 #define PSTATE_IT_1_0_SHIFT 25
278 #define PSTATE_IT_1_0_MASK (0x3 << PSTATE_IT_1_0_SHIFT)
279 #define PSTATE_IT_7_2_SHIFT 10
280 #define PSTATE_IT_7_2_MASK (0x3f << PSTATE_IT_7_2_SHIFT)
282 static u32 compat_get_it_state(struct pt_regs *regs)
284 u32 it, pstate = regs->pstate;
286 it = (pstate & PSTATE_IT_1_0_MASK) >> PSTATE_IT_1_0_SHIFT;
287 it |= ((pstate & PSTATE_IT_7_2_MASK) >> PSTATE_IT_7_2_SHIFT) << 2;
292 static void compat_set_it_state(struct pt_regs *regs, u32 it)
296 pstate_it = (it << PSTATE_IT_1_0_SHIFT) & PSTATE_IT_1_0_MASK;
297 pstate_it |= ((it >> 2) << PSTATE_IT_7_2_SHIFT) & PSTATE_IT_7_2_MASK;
299 regs->pstate &= ~PSR_AA32_IT_MASK;
300 regs->pstate |= pstate_it;
303 static void advance_itstate(struct pt_regs *regs)
308 if (!(regs->pstate & PSR_AA32_T_BIT) ||
309 !(regs->pstate & PSR_AA32_IT_MASK))
312 it = compat_get_it_state(regs);
315 * If this is the last instruction of the block, wipe the IT
316 * state. Otherwise advance it.
321 it = (it & 0xe0) | ((it << 1) & 0x1f);
323 compat_set_it_state(regs, it);
326 static void advance_itstate(struct pt_regs *regs)
331 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size)
336 * If we were single stepping, we want to get the step exception after
337 * we return from the trap.
340 user_fastforward_single_step(current);
342 if (compat_user_mode(regs))
343 advance_itstate(regs);
345 regs->pstate &= ~PSR_BTYPE_MASK;
348 static LIST_HEAD(undef_hook);
349 static DEFINE_RAW_SPINLOCK(undef_lock);
351 void register_undef_hook(struct undef_hook *hook)
355 raw_spin_lock_irqsave(&undef_lock, flags);
356 list_add(&hook->node, &undef_hook);
357 raw_spin_unlock_irqrestore(&undef_lock, flags);
360 void unregister_undef_hook(struct undef_hook *hook)
364 raw_spin_lock_irqsave(&undef_lock, flags);
365 list_del(&hook->node);
366 raw_spin_unlock_irqrestore(&undef_lock, flags);
369 static int call_undef_hook(struct pt_regs *regs)
371 struct undef_hook *hook;
374 int (*fn)(struct pt_regs *regs, u32 instr) = NULL;
375 void __user *pc = (void __user *)instruction_pointer(regs);
377 if (!user_mode(regs)) {
379 if (probe_kernel_address((__force __le32 *)pc, instr_le))
381 instr = le32_to_cpu(instr_le);
382 } else if (compat_thumb_mode(regs)) {
383 /* 16-bit Thumb instruction */
385 if (get_user(instr_le, (__le16 __user *)pc))
387 instr = le16_to_cpu(instr_le);
388 if (aarch32_insn_is_wide(instr)) {
391 if (get_user(instr_le, (__le16 __user *)(pc + 2)))
393 instr2 = le16_to_cpu(instr_le);
394 instr = (instr << 16) | instr2;
397 /* 32-bit ARM instruction */
399 if (get_user(instr_le, (__le32 __user *)pc))
401 instr = le32_to_cpu(instr_le);
404 raw_spin_lock_irqsave(&undef_lock, flags);
405 list_for_each_entry(hook, &undef_hook, node)
406 if ((instr & hook->instr_mask) == hook->instr_val &&
407 (regs->pstate & hook->pstate_mask) == hook->pstate_val)
410 raw_spin_unlock_irqrestore(&undef_lock, flags);
412 return fn ? fn(regs, instr) : 1;
415 void force_signal_inject(int signal, int code, unsigned long address)
418 struct pt_regs *regs = current_pt_regs();
420 if (WARN_ON(!user_mode(regs)))
425 desc = "undefined instruction";
428 desc = "illegal memory access";
431 desc = "unknown or unrecoverable error";
435 /* Force signals we don't understand to SIGKILL */
436 if (WARN_ON(signal != SIGKILL &&
437 siginfo_layout(signal, code) != SIL_FAULT)) {
441 arm64_notify_die(desc, regs, signal, code, (void __user *)address, 0);
445 * Set up process info to signal segmentation fault - called on access error.
447 void arm64_notify_segfault(unsigned long addr)
451 mmap_read_lock(current->mm);
452 if (find_vma(current->mm, addr) == NULL)
456 mmap_read_unlock(current->mm);
458 force_signal_inject(SIGSEGV, code, addr);
461 void do_undefinstr(struct pt_regs *regs)
463 /* check for AArch32 breakpoint instructions */
464 if (!aarch32_break_handler(regs))
467 if (call_undef_hook(regs) == 0)
470 BUG_ON(!user_mode(regs));
471 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc);
473 NOKPROBE_SYMBOL(do_undefinstr);
475 void do_bti(struct pt_regs *regs)
477 BUG_ON(!user_mode(regs));
478 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc);
480 NOKPROBE_SYMBOL(do_bti);
482 #define __user_cache_maint(insn, address, res) \
483 if (address >= user_addr_max()) { \
486 uaccess_ttbr0_enable(); \
488 "1: " insn ", %1\n" \
491 " .pushsection .fixup,\"ax\"\n" \
493 "3: mov %w0, %w2\n" \
496 _ASM_EXTABLE(1b, 3b) \
498 : "r" (address), "i" (-EFAULT)); \
499 uaccess_ttbr0_disable(); \
502 static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs)
504 unsigned long address;
505 int rt = ESR_ELx_SYS64_ISS_RT(esr);
506 int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT;
509 address = untagged_addr(pt_regs_read_reg(regs, rt));
512 case ESR_ELx_SYS64_ISS_CRM_DC_CVAU: /* DC CVAU, gets promoted */
513 __user_cache_maint("dc civac", address, ret);
515 case ESR_ELx_SYS64_ISS_CRM_DC_CVAC: /* DC CVAC, gets promoted */
516 __user_cache_maint("dc civac", address, ret);
518 case ESR_ELx_SYS64_ISS_CRM_DC_CVADP: /* DC CVADP */
519 __user_cache_maint("sys 3, c7, c13, 1", address, ret);
521 case ESR_ELx_SYS64_ISS_CRM_DC_CVAP: /* DC CVAP */
522 __user_cache_maint("sys 3, c7, c12, 1", address, ret);
524 case ESR_ELx_SYS64_ISS_CRM_DC_CIVAC: /* DC CIVAC */
525 __user_cache_maint("dc civac", address, ret);
527 case ESR_ELx_SYS64_ISS_CRM_IC_IVAU: /* IC IVAU */
528 __user_cache_maint("ic ivau", address, ret);
531 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc);
536 arm64_notify_segfault(address);
538 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
541 static void ctr_read_handler(unsigned int esr, struct pt_regs *regs)
543 int rt = ESR_ELx_SYS64_ISS_RT(esr);
544 unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0);
546 if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) {
547 /* Hide DIC so that we can trap the unnecessary maintenance...*/
548 val &= ~BIT(CTR_DIC_SHIFT);
550 /* ... and fake IminLine to reduce the number of traps. */
551 val &= ~CTR_IMINLINE_MASK;
552 val |= (PAGE_SHIFT - 2) & CTR_IMINLINE_MASK;
555 pt_regs_write_reg(regs, rt, val);
557 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
560 static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs)
562 int rt = ESR_ELx_SYS64_ISS_RT(esr);
564 pt_regs_write_reg(regs, rt, arch_timer_read_counter());
565 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
568 static void cntfrq_read_handler(unsigned int esr, struct pt_regs *regs)
570 int rt = ESR_ELx_SYS64_ISS_RT(esr);
572 pt_regs_write_reg(regs, rt, arch_timer_get_rate());
573 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
576 static void mrs_handler(unsigned int esr, struct pt_regs *regs)
580 rt = ESR_ELx_SYS64_ISS_RT(esr);
581 sysreg = esr_sys64_to_sysreg(esr);
583 if (do_emulate_mrs(regs, sysreg, rt) != 0)
584 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc);
587 static void wfi_handler(unsigned int esr, struct pt_regs *regs)
589 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
593 unsigned int esr_mask;
594 unsigned int esr_val;
595 void (*handler)(unsigned int esr, struct pt_regs *regs);
598 static const struct sys64_hook sys64_hooks[] = {
600 .esr_mask = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK,
601 .esr_val = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL,
602 .handler = user_cache_maint_handler,
605 /* Trap read access to CTR_EL0 */
606 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
607 .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ,
608 .handler = ctr_read_handler,
611 /* Trap read access to CNTVCT_EL0 */
612 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
613 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT,
614 .handler = cntvct_read_handler,
617 /* Trap read access to CNTFRQ_EL0 */
618 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
619 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTFRQ,
620 .handler = cntfrq_read_handler,
623 /* Trap read access to CPUID registers */
624 .esr_mask = ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK,
625 .esr_val = ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL,
626 .handler = mrs_handler,
629 /* Trap WFI instructions executed in userspace */
630 .esr_mask = ESR_ELx_WFx_MASK,
631 .esr_val = ESR_ELx_WFx_WFI_VAL,
632 .handler = wfi_handler,
638 static bool cp15_cond_valid(unsigned int esr, struct pt_regs *regs)
642 /* Only a T32 instruction can trap without CV being set */
643 if (!(esr & ESR_ELx_CV)) {
646 it = compat_get_it_state(regs);
652 cond = (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT;
655 return aarch32_opcode_cond_checks[cond](regs->pstate);
658 static void compat_cntfrq_read_handler(unsigned int esr, struct pt_regs *regs)
660 int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT;
662 pt_regs_write_reg(regs, reg, arch_timer_get_rate());
663 arm64_skip_faulting_instruction(regs, 4);
666 static const struct sys64_hook cp15_32_hooks[] = {
668 .esr_mask = ESR_ELx_CP15_32_ISS_SYS_MASK,
669 .esr_val = ESR_ELx_CP15_32_ISS_SYS_CNTFRQ,
670 .handler = compat_cntfrq_read_handler,
675 static void compat_cntvct_read_handler(unsigned int esr, struct pt_regs *regs)
677 int rt = (esr & ESR_ELx_CP15_64_ISS_RT_MASK) >> ESR_ELx_CP15_64_ISS_RT_SHIFT;
678 int rt2 = (esr & ESR_ELx_CP15_64_ISS_RT2_MASK) >> ESR_ELx_CP15_64_ISS_RT2_SHIFT;
679 u64 val = arch_timer_read_counter();
681 pt_regs_write_reg(regs, rt, lower_32_bits(val));
682 pt_regs_write_reg(regs, rt2, upper_32_bits(val));
683 arm64_skip_faulting_instruction(regs, 4);
686 static const struct sys64_hook cp15_64_hooks[] = {
688 .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK,
689 .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCT,
690 .handler = compat_cntvct_read_handler,
695 void do_cp15instr(unsigned int esr, struct pt_regs *regs)
697 const struct sys64_hook *hook, *hook_base;
699 if (!cp15_cond_valid(esr, regs)) {
701 * There is no T16 variant of a CP access, so we
702 * always advance PC by 4 bytes.
704 arm64_skip_faulting_instruction(regs, 4);
708 switch (ESR_ELx_EC(esr)) {
709 case ESR_ELx_EC_CP15_32:
710 hook_base = cp15_32_hooks;
712 case ESR_ELx_EC_CP15_64:
713 hook_base = cp15_64_hooks;
720 for (hook = hook_base; hook->handler; hook++)
721 if ((hook->esr_mask & esr) == hook->esr_val) {
722 hook->handler(esr, regs);
727 * New cp15 instructions may previously have been undefined at
728 * EL0. Fall back to our usual undefined instruction handler
729 * so that we handle these consistently.
733 NOKPROBE_SYMBOL(do_cp15instr);
736 void do_sysinstr(unsigned int esr, struct pt_regs *regs)
738 const struct sys64_hook *hook;
740 for (hook = sys64_hooks; hook->handler; hook++)
741 if ((hook->esr_mask & esr) == hook->esr_val) {
742 hook->handler(esr, regs);
747 * New SYS instructions may previously have been undefined at EL0. Fall
748 * back to our usual undefined instruction handler so that we handle
749 * these consistently.
753 NOKPROBE_SYMBOL(do_sysinstr);
755 static const char *esr_class_str[] = {
756 [0 ... ESR_ELx_EC_MAX] = "UNRECOGNIZED EC",
757 [ESR_ELx_EC_UNKNOWN] = "Unknown/Uncategorized",
758 [ESR_ELx_EC_WFx] = "WFI/WFE",
759 [ESR_ELx_EC_CP15_32] = "CP15 MCR/MRC",
760 [ESR_ELx_EC_CP15_64] = "CP15 MCRR/MRRC",
761 [ESR_ELx_EC_CP14_MR] = "CP14 MCR/MRC",
762 [ESR_ELx_EC_CP14_LS] = "CP14 LDC/STC",
763 [ESR_ELx_EC_FP_ASIMD] = "ASIMD",
764 [ESR_ELx_EC_CP10_ID] = "CP10 MRC/VMRS",
765 [ESR_ELx_EC_PAC] = "PAC",
766 [ESR_ELx_EC_CP14_64] = "CP14 MCRR/MRRC",
767 [ESR_ELx_EC_BTI] = "BTI",
768 [ESR_ELx_EC_ILL] = "PSTATE.IL",
769 [ESR_ELx_EC_SVC32] = "SVC (AArch32)",
770 [ESR_ELx_EC_HVC32] = "HVC (AArch32)",
771 [ESR_ELx_EC_SMC32] = "SMC (AArch32)",
772 [ESR_ELx_EC_SVC64] = "SVC (AArch64)",
773 [ESR_ELx_EC_HVC64] = "HVC (AArch64)",
774 [ESR_ELx_EC_SMC64] = "SMC (AArch64)",
775 [ESR_ELx_EC_SYS64] = "MSR/MRS (AArch64)",
776 [ESR_ELx_EC_SVE] = "SVE",
777 [ESR_ELx_EC_ERET] = "ERET/ERETAA/ERETAB",
778 [ESR_ELx_EC_IMP_DEF] = "EL3 IMP DEF",
779 [ESR_ELx_EC_IABT_LOW] = "IABT (lower EL)",
780 [ESR_ELx_EC_IABT_CUR] = "IABT (current EL)",
781 [ESR_ELx_EC_PC_ALIGN] = "PC Alignment",
782 [ESR_ELx_EC_DABT_LOW] = "DABT (lower EL)",
783 [ESR_ELx_EC_DABT_CUR] = "DABT (current EL)",
784 [ESR_ELx_EC_SP_ALIGN] = "SP Alignment",
785 [ESR_ELx_EC_FP_EXC32] = "FP (AArch32)",
786 [ESR_ELx_EC_FP_EXC64] = "FP (AArch64)",
787 [ESR_ELx_EC_SERROR] = "SError",
788 [ESR_ELx_EC_BREAKPT_LOW] = "Breakpoint (lower EL)",
789 [ESR_ELx_EC_BREAKPT_CUR] = "Breakpoint (current EL)",
790 [ESR_ELx_EC_SOFTSTP_LOW] = "Software Step (lower EL)",
791 [ESR_ELx_EC_SOFTSTP_CUR] = "Software Step (current EL)",
792 [ESR_ELx_EC_WATCHPT_LOW] = "Watchpoint (lower EL)",
793 [ESR_ELx_EC_WATCHPT_CUR] = "Watchpoint (current EL)",
794 [ESR_ELx_EC_BKPT32] = "BKPT (AArch32)",
795 [ESR_ELx_EC_VECTOR32] = "Vector catch (AArch32)",
796 [ESR_ELx_EC_BRK64] = "BRK (AArch64)",
799 const char *esr_get_class_string(u32 esr)
801 return esr_class_str[ESR_ELx_EC(esr)];
805 * bad_mode handles the impossible case in the exception vector. This is always
808 asmlinkage void bad_mode(struct pt_regs *regs, int reason, unsigned int esr)
812 pr_crit("Bad mode in %s handler detected on CPU%d, code 0x%08x -- %s\n",
813 handler[reason], smp_processor_id(), esr,
814 esr_get_class_string(esr));
821 * bad_el0_sync handles unexpected, but potentially recoverable synchronous
822 * exceptions taken from EL0. Unlike bad_mode, this returns.
824 void bad_el0_sync(struct pt_regs *regs, int reason, unsigned int esr)
826 void __user *pc = (void __user *)instruction_pointer(regs);
828 current->thread.fault_address = 0;
829 current->thread.fault_code = esr;
831 arm64_force_sig_fault(SIGILL, ILL_ILLOPC, pc,
832 "Bad EL0 synchronous exception");
835 #ifdef CONFIG_VMAP_STACK
837 DEFINE_PER_CPU(unsigned long [OVERFLOW_STACK_SIZE/sizeof(long)], overflow_stack)
840 asmlinkage void handle_bad_stack(struct pt_regs *regs)
842 unsigned long tsk_stk = (unsigned long)current->stack;
843 unsigned long irq_stk = (unsigned long)this_cpu_read(irq_stack_ptr);
844 unsigned long ovf_stk = (unsigned long)this_cpu_ptr(overflow_stack);
845 unsigned int esr = read_sysreg(esr_el1);
846 unsigned long far = read_sysreg(far_el1);
849 pr_emerg("Insufficient stack space to handle exception!");
851 pr_emerg("ESR: 0x%08x -- %s\n", esr, esr_get_class_string(esr));
852 pr_emerg("FAR: 0x%016lx\n", far);
854 pr_emerg("Task stack: [0x%016lx..0x%016lx]\n",
855 tsk_stk, tsk_stk + THREAD_SIZE);
856 pr_emerg("IRQ stack: [0x%016lx..0x%016lx]\n",
857 irq_stk, irq_stk + THREAD_SIZE);
858 pr_emerg("Overflow stack: [0x%016lx..0x%016lx]\n",
859 ovf_stk, ovf_stk + OVERFLOW_STACK_SIZE);
864 * We use nmi_panic to limit the potential for recusive overflows, and
865 * to get a better stack trace.
867 nmi_panic(NULL, "kernel stack overflow");
872 void __noreturn arm64_serror_panic(struct pt_regs *regs, u32 esr)
876 pr_crit("SError Interrupt on CPU%d, code 0x%08x -- %s\n",
877 smp_processor_id(), esr, esr_get_class_string(esr));
881 nmi_panic(regs, "Asynchronous SError Interrupt");
887 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned int esr)
889 u32 aet = arm64_ras_serror_get_severity(esr);
892 case ESR_ELx_AET_CE: /* corrected error */
893 case ESR_ELx_AET_UEO: /* restartable, not yet consumed */
895 * The CPU can make progress. We may take UEO again as
896 * a more severe error.
900 case ESR_ELx_AET_UEU: /* Uncorrected Unrecoverable */
901 case ESR_ELx_AET_UER: /* Uncorrected Recoverable */
903 * The CPU can't make progress. The exception may have
906 * Neoverse-N1 #1349291 means a non-KVM SError reported as
907 * Unrecoverable should be treated as Uncontainable. We
908 * call arm64_serror_panic() in both cases.
912 case ESR_ELx_AET_UC: /* Uncontainable or Uncategorized error */
914 /* Error has been silently propagated */
915 arm64_serror_panic(regs, esr);
919 asmlinkage void do_serror(struct pt_regs *regs, unsigned int esr)
923 /* non-RAS errors are not containable */
924 if (!arm64_is_ras_serror(esr) || arm64_is_fatal_ras_serror(regs, esr))
925 arm64_serror_panic(regs, esr);
930 asmlinkage void enter_from_user_mode(void)
932 CT_WARN_ON(ct_state() != CONTEXT_USER);
935 NOKPROBE_SYMBOL(enter_from_user_mode);
937 void __pte_error(const char *file, int line, unsigned long val)
939 pr_err("%s:%d: bad pte %016lx.\n", file, line, val);
942 void __pmd_error(const char *file, int line, unsigned long val)
944 pr_err("%s:%d: bad pmd %016lx.\n", file, line, val);
947 void __pud_error(const char *file, int line, unsigned long val)
949 pr_err("%s:%d: bad pud %016lx.\n", file, line, val);
952 void __pgd_error(const char *file, int line, unsigned long val)
954 pr_err("%s:%d: bad pgd %016lx.\n", file, line, val);
957 /* GENERIC_BUG traps */
959 int is_valid_bugaddr(unsigned long addr)
962 * bug_handler() only called for BRK #BUG_BRK_IMM.
963 * So the answer is trivial -- any spurious instances with no
964 * bug table entry will be rejected by report_bug() and passed
965 * back to the debug-monitors code and handled as a fatal
966 * unexpected debug exception.
971 static int bug_handler(struct pt_regs *regs, unsigned int esr)
973 switch (report_bug(regs->pc, regs)) {
974 case BUG_TRAP_TYPE_BUG:
975 die("Oops - BUG", regs, 0);
978 case BUG_TRAP_TYPE_WARN:
982 /* unknown/unrecognised bug trap type */
983 return DBG_HOOK_ERROR;
986 /* If thread survives, skip over the BUG instruction and continue: */
987 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
988 return DBG_HOOK_HANDLED;
991 static struct break_hook bug_break_hook = {
996 #ifdef CONFIG_KASAN_SW_TAGS
998 #define KASAN_ESR_RECOVER 0x20
999 #define KASAN_ESR_WRITE 0x10
1000 #define KASAN_ESR_SIZE_MASK 0x0f
1001 #define KASAN_ESR_SIZE(esr) (1 << ((esr) & KASAN_ESR_SIZE_MASK))
1003 static int kasan_handler(struct pt_regs *regs, unsigned int esr)
1005 bool recover = esr & KASAN_ESR_RECOVER;
1006 bool write = esr & KASAN_ESR_WRITE;
1007 size_t size = KASAN_ESR_SIZE(esr);
1008 u64 addr = regs->regs[0];
1011 kasan_report(addr, size, write, pc);
1014 * The instrumentation allows to control whether we can proceed after
1015 * a crash was detected. This is done by passing the -recover flag to
1016 * the compiler. Disabling recovery allows to generate more compact
1019 * Unfortunately disabling recovery doesn't work for the kernel right
1020 * now. KASAN reporting is disabled in some contexts (for example when
1021 * the allocator accesses slab object metadata; this is controlled by
1022 * current->kasan_depth). All these accesses are detected by the tool,
1023 * even though the reports for them are not printed.
1025 * This is something that might be fixed at some point in the future.
1028 die("Oops - KASAN", regs, 0);
1030 /* If thread survives, skip over the brk instruction and continue: */
1031 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
1032 return DBG_HOOK_HANDLED;
1035 static struct break_hook kasan_break_hook = {
1036 .fn = kasan_handler,
1037 .imm = KASAN_BRK_IMM,
1038 .mask = KASAN_BRK_MASK,
1043 * Initial handler for AArch64 BRK exceptions
1044 * This handler only used until debug_traps_init().
1046 int __init early_brk64(unsigned long addr, unsigned int esr,
1047 struct pt_regs *regs)
1049 #ifdef CONFIG_KASAN_SW_TAGS
1050 unsigned int comment = esr & ESR_ELx_BRK64_ISS_COMMENT_MASK;
1052 if ((comment & ~KASAN_BRK_MASK) == KASAN_BRK_IMM)
1053 return kasan_handler(regs, esr) != DBG_HOOK_HANDLED;
1055 return bug_handler(regs, esr) != DBG_HOOK_HANDLED;
1058 void __init trap_init(void)
1060 register_kernel_break_hook(&bug_break_hook);
1061 #ifdef CONFIG_KASAN_SW_TAGS
1062 register_kernel_break_hook(&kasan_break_hook);