1 // SPDX-License-Identifier: GPL-2.0-only
3 * Based on arch/arm/kernel/process.c
5 * Original Copyright (C) 1995 Linus Torvalds
6 * Copyright (C) 1996-2000 Russell King - Converted to ARM.
7 * Copyright (C) 2012 ARM Ltd.
12 #include <linux/compat.h>
13 #include <linux/efi.h>
14 #include <linux/elf.h>
15 #include <linux/export.h>
16 #include <linux/sched.h>
17 #include <linux/sched/debug.h>
18 #include <linux/sched/task.h>
19 #include <linux/sched/task_stack.h>
20 #include <linux/kernel.h>
21 #include <linux/lockdep.h>
22 #include <linux/mman.h>
24 #include <linux/nospec.h>
25 #include <linux/stddef.h>
26 #include <linux/sysctl.h>
27 #include <linux/unistd.h>
28 #include <linux/user.h>
29 #include <linux/delay.h>
30 #include <linux/reboot.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/cpu.h>
34 #include <linux/elfcore.h>
36 #include <linux/tick.h>
37 #include <linux/utsname.h>
38 #include <linux/uaccess.h>
39 #include <linux/random.h>
40 #include <linux/hw_breakpoint.h>
41 #include <linux/personality.h>
42 #include <linux/notifier.h>
43 #include <trace/events/power.h>
44 #include <linux/percpu.h>
45 #include <linux/thread_info.h>
46 #include <linux/prctl.h>
48 #include <asm/alternative.h>
49 #include <asm/arch_gicv3.h>
50 #include <asm/compat.h>
51 #include <asm/cpufeature.h>
52 #include <asm/cacheflush.h>
54 #include <asm/fpsimd.h>
55 #include <asm/mmu_context.h>
57 #include <asm/processor.h>
58 #include <asm/pointer_auth.h>
59 #include <asm/stacktrace.h>
60 #include <asm/switch_to.h>
61 #include <asm/system_misc.h>
63 #if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_STACKPROTECTOR_PER_TASK)
64 #include <linux/stackprotector.h>
65 unsigned long __stack_chk_guard __read_mostly;
66 EXPORT_SYMBOL(__stack_chk_guard);
70 * Function pointers to optional machine specific functions
72 void (*pm_power_off)(void);
73 EXPORT_SYMBOL_GPL(pm_power_off);
75 void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
77 static void noinstr __cpu_do_idle(void)
83 static void noinstr __cpu_do_idle_irqprio(void)
86 unsigned long daif_bits;
88 daif_bits = read_sysreg(daif);
89 write_sysreg(daif_bits | PSR_I_BIT | PSR_F_BIT, daif);
92 * Unmask PMR before going idle to make sure interrupts can
96 gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET);
101 write_sysreg(daif_bits, daif);
107 * Idle the processor (wait for interrupt).
109 * If the CPU supports priority masking we must do additional work to
110 * ensure that interrupts are not masked at the PMR (because the core will
111 * not wake up if we block the wake up signal in the interrupt controller).
113 void noinstr cpu_do_idle(void)
115 if (system_uses_irq_prio_masking())
116 __cpu_do_idle_irqprio();
122 * This is our default idle handler.
124 void noinstr arch_cpu_idle(void)
127 * This should do all the clock switching and wait for interrupt
131 raw_local_irq_enable();
134 #ifdef CONFIG_HOTPLUG_CPU
135 void arch_cpu_idle_dead(void)
142 * Called by kexec, immediately prior to machine_kexec().
144 * This must completely disable all secondary CPUs; simply causing those CPUs
145 * to execute e.g. a RAM-based pin loop is not sufficient. This allows the
146 * kexec'd kernel to use any and all RAM as it sees fit, without having to
147 * avoid any code or data used by any SW CPU pin loop. The CPU hotplug
148 * functionality embodied in smpt_shutdown_nonboot_cpus() to achieve this.
150 void machine_shutdown(void)
152 smp_shutdown_nonboot_cpus(reboot_cpu);
156 * Halting simply requires that the secondary CPUs stop performing any
157 * activity (executing tasks, handling interrupts). smp_send_stop()
160 void machine_halt(void)
168 * Power-off simply requires that the secondary CPUs stop performing any
169 * activity (executing tasks, handling interrupts). smp_send_stop()
170 * achieves this. When the system power is turned off, it will take all CPUs
173 void machine_power_off(void)
182 * Restart requires that the secondary CPUs stop performing any activity
183 * while the primary CPU resets the system. Systems with multiple CPUs must
184 * provide a HW restart implementation, to ensure that all CPUs reset at once.
185 * This is required so that any code running after reset on the primary CPU
186 * doesn't have to co-ordinate with other CPUs to ensure they aren't still
187 * executing pre-reset code, and using RAM that the primary CPU's code wishes
188 * to use. Implementing such co-ordination would be essentially impossible.
190 void machine_restart(char *cmd)
192 /* Disable interrupts first */
197 * UpdateCapsule() depends on the system being reset via
200 if (efi_enabled(EFI_RUNTIME_SERVICES))
201 efi_reboot(reboot_mode, NULL);
203 /* Now call the architecture specific reboot code. */
205 arm_pm_restart(reboot_mode, cmd);
207 do_kernel_restart(cmd);
210 * Whoops - the architecture was unable to reboot.
212 printk("Reboot failed -- System halted\n");
216 #define bstr(suffix, str) [PSR_BTYPE_ ## suffix >> PSR_BTYPE_SHIFT] = str
217 static const char *const btypes[] = {
225 static void print_pstate(struct pt_regs *regs)
227 u64 pstate = regs->pstate;
229 if (compat_user_mode(regs)) {
230 printk("pstate: %08llx (%c%c%c%c %c %s %s %c%c%c)\n",
232 pstate & PSR_AA32_N_BIT ? 'N' : 'n',
233 pstate & PSR_AA32_Z_BIT ? 'Z' : 'z',
234 pstate & PSR_AA32_C_BIT ? 'C' : 'c',
235 pstate & PSR_AA32_V_BIT ? 'V' : 'v',
236 pstate & PSR_AA32_Q_BIT ? 'Q' : 'q',
237 pstate & PSR_AA32_T_BIT ? "T32" : "A32",
238 pstate & PSR_AA32_E_BIT ? "BE" : "LE",
239 pstate & PSR_AA32_A_BIT ? 'A' : 'a',
240 pstate & PSR_AA32_I_BIT ? 'I' : 'i',
241 pstate & PSR_AA32_F_BIT ? 'F' : 'f');
243 const char *btype_str = btypes[(pstate & PSR_BTYPE_MASK) >>
246 printk("pstate: %08llx (%c%c%c%c %c%c%c%c %cPAN %cUAO %cTCO BTYPE=%s)\n",
248 pstate & PSR_N_BIT ? 'N' : 'n',
249 pstate & PSR_Z_BIT ? 'Z' : 'z',
250 pstate & PSR_C_BIT ? 'C' : 'c',
251 pstate & PSR_V_BIT ? 'V' : 'v',
252 pstate & PSR_D_BIT ? 'D' : 'd',
253 pstate & PSR_A_BIT ? 'A' : 'a',
254 pstate & PSR_I_BIT ? 'I' : 'i',
255 pstate & PSR_F_BIT ? 'F' : 'f',
256 pstate & PSR_PAN_BIT ? '+' : '-',
257 pstate & PSR_UAO_BIT ? '+' : '-',
258 pstate & PSR_TCO_BIT ? '+' : '-',
263 void __show_regs(struct pt_regs *regs)
268 if (compat_user_mode(regs)) {
269 lr = regs->compat_lr;
270 sp = regs->compat_sp;
278 show_regs_print_info(KERN_DEFAULT);
281 if (!user_mode(regs)) {
282 printk("pc : %pS\n", (void *)regs->pc);
283 printk("lr : %pS\n", (void *)ptrauth_strip_insn_pac(lr));
285 printk("pc : %016llx\n", regs->pc);
286 printk("lr : %016llx\n", lr);
289 printk("sp : %016llx\n", sp);
291 if (system_uses_irq_prio_masking())
292 printk("pmr_save: %08llx\n", regs->pmr_save);
297 printk("x%-2d: %016llx", i, regs->regs[i]);
300 pr_cont(" x%-2d: %016llx", i, regs->regs[i]);
306 void show_regs(struct pt_regs *regs)
309 dump_backtrace(regs, NULL, KERN_DEFAULT);
312 static void tls_thread_flush(void)
314 write_sysreg(0, tpidr_el0);
316 if (is_compat_task()) {
317 current->thread.uw.tp_value = 0;
320 * We need to ensure ordering between the shadow state and the
321 * hardware state, so that we don't corrupt the hardware state
322 * with a stale shadow state during context switch.
325 write_sysreg(0, tpidrro_el0);
329 static void flush_tagged_addr_state(void)
331 if (IS_ENABLED(CONFIG_ARM64_TAGGED_ADDR_ABI))
332 clear_thread_flag(TIF_TAGGED_ADDR);
335 void flush_thread(void)
337 fpsimd_flush_thread();
339 flush_ptrace_hw_breakpoint(current);
340 flush_tagged_addr_state();
343 void release_thread(struct task_struct *dead_task)
347 void arch_release_task_struct(struct task_struct *tsk)
349 fpsimd_release_task(tsk);
352 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
355 fpsimd_preserve_current_state();
358 /* We rely on the above assignment to initialize dst's thread_flags: */
359 BUILD_BUG_ON(!IS_ENABLED(CONFIG_THREAD_INFO_IN_TASK));
362 * Detach src's sve_state (if any) from dst so that it does not
363 * get erroneously used or freed prematurely. dst's sve_state
364 * will be allocated on demand later on if dst uses SVE.
365 * For consistency, also clear TIF_SVE here: this could be done
366 * later in copy_process(), but to avoid tripping up future
367 * maintainers it is best not to leave TIF_SVE and sve_state in
368 * an inconsistent state, even temporarily.
370 dst->thread.sve_state = NULL;
371 clear_tsk_thread_flag(dst, TIF_SVE);
373 /* clear any pending asynchronous tag fault raised by the parent */
374 clear_tsk_thread_flag(dst, TIF_MTE_ASYNC_FAULT);
379 asmlinkage void ret_from_fork(void) asm("ret_from_fork");
381 int copy_thread(unsigned long clone_flags, unsigned long stack_start,
382 unsigned long stk_sz, struct task_struct *p, unsigned long tls)
384 struct pt_regs *childregs = task_pt_regs(p);
386 memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));
389 * In case p was allocated the same task_struct pointer as some
390 * other recently-exited task, make sure p is disassociated from
391 * any cpu that may have run that now-exited task recently.
392 * Otherwise we could erroneously skip reloading the FPSIMD
395 fpsimd_flush_task_state(p);
397 ptrauth_thread_init_kernel(p);
399 if (likely(!(p->flags & (PF_KTHREAD | PF_IO_WORKER)))) {
400 *childregs = *current_pt_regs();
401 childregs->regs[0] = 0;
404 * Read the current TLS pointer from tpidr_el0 as it may be
405 * out-of-sync with the saved value.
407 *task_user_tls(p) = read_sysreg(tpidr_el0);
410 if (is_compat_thread(task_thread_info(p)))
411 childregs->compat_sp = stack_start;
413 childregs->sp = stack_start;
417 * If a TLS pointer was passed to clone, use it for the new
420 if (clone_flags & CLONE_SETTLS)
421 p->thread.uw.tp_value = tls;
424 * A kthread has no context to ERET to, so ensure any buggy
425 * ERET is treated as an illegal exception return.
427 * When a user task is created from a kthread, childregs will
428 * be initialized by start_thread() or start_compat_thread().
430 memset(childregs, 0, sizeof(struct pt_regs));
431 childregs->pstate = PSR_MODE_EL1h | PSR_IL_BIT;
433 p->thread.cpu_context.x19 = stack_start;
434 p->thread.cpu_context.x20 = stk_sz;
436 p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
437 p->thread.cpu_context.sp = (unsigned long)childregs;
439 ptrace_hw_copy_thread(p);
444 void tls_preserve_current_state(void)
446 *task_user_tls(current) = read_sysreg(tpidr_el0);
449 static void tls_thread_switch(struct task_struct *next)
451 tls_preserve_current_state();
453 if (is_compat_thread(task_thread_info(next)))
454 write_sysreg(next->thread.uw.tp_value, tpidrro_el0);
455 else if (!arm64_kernel_unmapped_at_el0())
456 write_sysreg(0, tpidrro_el0);
458 write_sysreg(*task_user_tls(next), tpidr_el0);
462 * Force SSBS state on context-switch, since it may be lost after migrating
463 * from a CPU which treats the bit as RES0 in a heterogeneous system.
465 static void ssbs_thread_switch(struct task_struct *next)
468 * Nothing to do for kernel threads, but 'regs' may be junk
469 * (e.g. idle task) so check the flags and bail early.
471 if (unlikely(next->flags & PF_KTHREAD))
475 * If all CPUs implement the SSBS extension, then we just need to
476 * context-switch the PSTATE field.
478 if (cpus_have_const_cap(ARM64_SSBS))
481 spectre_v4_enable_task_mitigation(next);
485 * We store our current task in sp_el0, which is clobbered by userspace. Keep a
486 * shadow copy so that we can restore this upon entry from userspace.
488 * This is *only* for exception entry from EL0, and is not valid until we
489 * __switch_to() a user task.
491 DEFINE_PER_CPU(struct task_struct *, __entry_task);
493 static void entry_task_switch(struct task_struct *next)
495 __this_cpu_write(__entry_task, next);
499 * ARM erratum 1418040 handling, affecting the 32bit view of CNTVCT.
500 * Assuming the virtual counter is enabled at the beginning of times:
502 * - disable access when switching from a 64bit task to a 32bit task
503 * - enable access when switching from a 32bit task to a 64bit task
505 static void erratum_1418040_thread_switch(struct task_struct *prev,
506 struct task_struct *next)
511 if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_1418040))
514 prev32 = is_compat_thread(task_thread_info(prev));
515 next32 = is_compat_thread(task_thread_info(next));
517 if (prev32 == next32 || !this_cpu_has_cap(ARM64_WORKAROUND_1418040))
520 val = read_sysreg(cntkctl_el1);
523 val |= ARCH_TIMER_USR_VCT_ACCESS_EN;
525 val &= ~ARCH_TIMER_USR_VCT_ACCESS_EN;
527 write_sysreg(val, cntkctl_el1);
530 static void update_sctlr_el1(u64 sctlr)
533 * EnIA must not be cleared while in the kernel as this is necessary for
534 * in-kernel PAC. It will be cleared on kernel exit if needed.
536 sysreg_clear_set(sctlr_el1, SCTLR_USER_MASK & ~SCTLR_ELx_ENIA, sctlr);
538 /* ISB required for the kernel uaccess routines when setting TCF0. */
542 void set_task_sctlr_el1(u64 sctlr)
545 * __switch_to() checks current->thread.sctlr as an
546 * optimisation. Disable preemption so that it does not see
547 * the variable update before the SCTLR_EL1 one.
550 current->thread.sctlr_user = sctlr;
551 update_sctlr_el1(sctlr);
558 __notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev,
559 struct task_struct *next)
561 struct task_struct *last;
563 fpsimd_thread_switch(next);
564 tls_thread_switch(next);
565 hw_breakpoint_thread_switch(next);
566 contextidr_thread_switch(next);
567 entry_task_switch(next);
568 ssbs_thread_switch(next);
569 erratum_1418040_thread_switch(prev, next);
570 ptrauth_thread_switch_user(next);
573 * Complete any pending TLB or cache maintenance on this CPU in case
574 * the thread migrates to a different CPU.
575 * This full barrier is also required by the membarrier system
581 * MTE thread switching must happen after the DSB above to ensure that
582 * any asynchronous tag check faults have been logged in the TFSR*_EL1
585 mte_thread_switch(next);
586 /* avoid expensive SCTLR_EL1 accesses if no change */
587 if (prev->thread.sctlr_user != next->thread.sctlr_user)
588 update_sctlr_el1(next->thread.sctlr_user);
590 /* the actual thread switch */
591 last = cpu_switch_to(prev, next);
596 unsigned long get_wchan(struct task_struct *p)
598 struct stackframe frame;
599 unsigned long stack_page, ret = 0;
601 if (!p || p == current || p->state == TASK_RUNNING)
604 stack_page = (unsigned long)try_get_task_stack(p);
608 start_backtrace(&frame, thread_saved_fp(p), thread_saved_pc(p));
611 if (unwind_frame(p, &frame))
613 if (!in_sched_functions(frame.pc)) {
617 } while (count++ < 16);
624 unsigned long arch_align_stack(unsigned long sp)
626 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
627 sp -= get_random_int() & ~PAGE_MASK;
632 * Called from setup_new_exec() after (COMPAT_)SET_PERSONALITY.
634 void arch_setup_new_exec(void)
636 current->mm->context.flags = is_compat_task() ? MMCF_AARCH32 : 0;
638 ptrauth_thread_init_user();
639 mte_thread_init_user();
641 if (task_spec_ssb_noexec(current)) {
642 arch_prctl_spec_ctrl_set(current, PR_SPEC_STORE_BYPASS,
647 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI
649 * Control the relaxed ABI allowing tagged user addresses into the kernel.
651 static unsigned int tagged_addr_disabled;
653 long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg)
655 unsigned long valid_mask = PR_TAGGED_ADDR_ENABLE;
656 struct thread_info *ti = task_thread_info(task);
658 if (is_compat_thread(ti))
661 if (system_supports_mte())
662 valid_mask |= PR_MTE_TCF_MASK | PR_MTE_TAG_MASK;
664 if (arg & ~valid_mask)
668 * Do not allow the enabling of the tagged address ABI if globally
669 * disabled via sysctl abi.tagged_addr_disabled.
671 if (arg & PR_TAGGED_ADDR_ENABLE && tagged_addr_disabled)
674 if (set_mte_ctrl(task, arg) != 0)
677 update_ti_thread_flag(ti, TIF_TAGGED_ADDR, arg & PR_TAGGED_ADDR_ENABLE);
682 long get_tagged_addr_ctrl(struct task_struct *task)
685 struct thread_info *ti = task_thread_info(task);
687 if (is_compat_thread(ti))
690 if (test_ti_thread_flag(ti, TIF_TAGGED_ADDR))
691 ret = PR_TAGGED_ADDR_ENABLE;
693 ret |= get_mte_ctrl(task);
699 * Global sysctl to disable the tagged user addresses support. This control
700 * only prevents the tagged address ABI enabling via prctl() and does not
701 * disable it for tasks that already opted in to the relaxed ABI.
704 static struct ctl_table tagged_addr_sysctl_table[] = {
706 .procname = "tagged_addr_disabled",
708 .data = &tagged_addr_disabled,
709 .maxlen = sizeof(int),
710 .proc_handler = proc_dointvec_minmax,
711 .extra1 = SYSCTL_ZERO,
712 .extra2 = SYSCTL_ONE,
717 static int __init tagged_addr_init(void)
719 if (!register_sysctl("abi", tagged_addr_sysctl_table))
724 core_initcall(tagged_addr_init);
725 #endif /* CONFIG_ARM64_TAGGED_ADDR_ABI */
727 asmlinkage void __sched arm64_preempt_schedule_irq(void)
729 lockdep_assert_irqs_disabled();
732 * Preempting a task from an IRQ means we leave copies of PSTATE
733 * on the stack. cpufeature's enable calls may modify PSTATE, but
734 * resuming one of these preempted tasks would undo those changes.
736 * Only allow a task to be preempted once cpufeatures have been
739 if (system_capabilities_finalized())
740 preempt_schedule_irq();
743 #ifdef CONFIG_BINFMT_ELF
744 int arch_elf_adjust_prot(int prot, const struct arch_elf_state *state,
745 bool has_interp, bool is_interp)
748 * For dynamically linked executables the interpreter is
749 * responsible for setting PROT_BTI on everything except
752 if (is_interp != has_interp)
755 if (!(state->flags & ARM64_ELF_BTI))
758 if (prot & PROT_EXEC)