2 * AArch64 loadable module support.
4 * Copyright (C) 2012 ARM Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 * Author: Will Deacon <will.deacon@arm.com>
21 #include <linux/bitops.h>
22 #include <linux/elf.h>
23 #include <linux/gfp.h>
24 #include <linux/kernel.h>
26 #include <linux/moduleloader.h>
27 #include <linux/vmalloc.h>
29 void *module_alloc(unsigned long size)
31 return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END,
32 GFP_KERNEL, PAGE_KERNEL_EXEC, NUMA_NO_NODE,
33 __builtin_return_address(0));
36 enum aarch64_reloc_op {
43 static u64 do_reloc(enum aarch64_reloc_op reloc_op, void *place, u64 val)
49 return val - (u64)place;
51 return (val & ~0xfff) - ((u64)place & ~0xfff);
56 pr_err("do_reloc: unknown relocation operation %d\n", reloc_op);
60 static int reloc_data(enum aarch64_reloc_op op, void *place, u64 val, int len)
62 u64 imm_mask = (1 << len) - 1;
63 s64 sval = do_reloc(op, place, val);
76 pr_err("Invalid length (%d) for data relocation\n", len);
81 * Extract the upper value bits (including the sign bit) and
82 * shift them to bit 0.
84 sval = (s64)(sval & ~(imm_mask >> 1)) >> (len - 1);
87 * Overflow has occurred if the value is not representable in
88 * len bits (i.e the bottom len bits are not sign-extended and
89 * the top bits are not all zero).
91 if ((u64)(sval + 1) > 2)
97 enum aarch64_imm_type {
109 static u32 encode_insn_immediate(enum aarch64_imm_type type, u32 insn, u64 imm)
111 u32 immlo, immhi, lomask, himask, mask;
114 /* The instruction stream is always little endian. */
115 insn = le32_to_cpu(insn);
120 * For signed MOVW relocations, we have to manipulate the
121 * instruction encoding depending on whether or not the
122 * immediate is less than zero.
126 /* >=0: Set the instruction to MOVZ (opcode 10b). */
130 * <0: Set the instruction to MOVN (opcode 00b).
131 * Since we've masked the opcode already, we
132 * don't need to do anything other than
133 * inverting the new immediate field.
144 immlo = imm & lomask;
146 immhi = imm & himask;
147 imm = (immlo << 24) | (immhi);
148 mask = (lomask << 24) | (himask);
176 pr_err("encode_insn_immediate: unknown immediate encoding %d\n",
181 /* Update the immediate field. */
182 insn &= ~(mask << shift);
183 insn |= (imm & mask) << shift;
185 return cpu_to_le32(insn);
188 static int reloc_insn_movw(enum aarch64_reloc_op op, void *place, u64 val,
189 int lsb, enum aarch64_imm_type imm_type)
193 u32 insn = *(u32 *)place;
195 sval = do_reloc(op, place, val);
199 /* Update the instruction with the new encoding. */
200 *(u32 *)place = encode_insn_immediate(imm_type, insn, imm);
202 /* Shift out the immediate field. */
206 * For unsigned immediates, the overflow check is straightforward.
207 * For signed immediates, the sign bit is actually the bit past the
208 * most significant bit of the field.
209 * The INSN_IMM_16 immediate type is unsigned.
211 if (imm_type != INSN_IMM_16) {
216 /* Check the upper bits depending on the sign of the immediate. */
217 if ((u64)sval > limit)
223 static int reloc_insn_imm(enum aarch64_reloc_op op, void *place, u64 val,
224 int lsb, int len, enum aarch64_imm_type imm_type)
228 u32 insn = *(u32 *)place;
230 /* Calculate the relocation value. */
231 sval = do_reloc(op, place, val);
234 /* Extract the value bits and shift them to bit 0. */
235 imm_mask = (BIT(lsb + len) - 1) >> lsb;
236 imm = sval & imm_mask;
238 /* Update the instruction's immediate field. */
239 *(u32 *)place = encode_insn_immediate(imm_type, insn, imm);
242 * Extract the upper value bits (including the sign bit) and
243 * shift them to bit 0.
245 sval = (s64)(sval & ~(imm_mask >> 1)) >> (len - 1);
248 * Overflow has occurred if the upper bits are not all equal to
249 * the sign bit of the value.
251 if ((u64)(sval + 1) >= 2)
257 int apply_relocate_add(Elf64_Shdr *sechdrs,
259 unsigned int symindex,
269 Elf64_Rela *rel = (void *)sechdrs[relsec].sh_addr;
271 for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
272 /* loc corresponds to P in the AArch64 ELF document. */
273 loc = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
276 /* sym is the ELF symbol we're referring to. */
277 sym = (Elf64_Sym *)sechdrs[symindex].sh_addr
278 + ELF64_R_SYM(rel[i].r_info);
280 /* val corresponds to (S + A) in the AArch64 ELF document. */
281 val = sym->st_value + rel[i].r_addend;
283 /* Check for overflow by default. */
284 overflow_check = true;
286 /* Perform the static relocation. */
287 switch (ELF64_R_TYPE(rel[i].r_info)) {
288 /* Null relocations. */
294 /* Data relocations. */
295 case R_AARCH64_ABS64:
296 overflow_check = false;
297 ovf = reloc_data(RELOC_OP_ABS, loc, val, 64);
299 case R_AARCH64_ABS32:
300 ovf = reloc_data(RELOC_OP_ABS, loc, val, 32);
302 case R_AARCH64_ABS16:
303 ovf = reloc_data(RELOC_OP_ABS, loc, val, 16);
305 case R_AARCH64_PREL64:
306 overflow_check = false;
307 ovf = reloc_data(RELOC_OP_PREL, loc, val, 64);
309 case R_AARCH64_PREL32:
310 ovf = reloc_data(RELOC_OP_PREL, loc, val, 32);
312 case R_AARCH64_PREL16:
313 ovf = reloc_data(RELOC_OP_PREL, loc, val, 16);
316 /* MOVW instruction relocations. */
317 case R_AARCH64_MOVW_UABS_G0_NC:
318 overflow_check = false;
319 case R_AARCH64_MOVW_UABS_G0:
320 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
323 case R_AARCH64_MOVW_UABS_G1_NC:
324 overflow_check = false;
325 case R_AARCH64_MOVW_UABS_G1:
326 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
329 case R_AARCH64_MOVW_UABS_G2_NC:
330 overflow_check = false;
331 case R_AARCH64_MOVW_UABS_G2:
332 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
335 case R_AARCH64_MOVW_UABS_G3:
336 /* We're using the top bits so we can't overflow. */
337 overflow_check = false;
338 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 48,
341 case R_AARCH64_MOVW_SABS_G0:
342 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
345 case R_AARCH64_MOVW_SABS_G1:
346 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
349 case R_AARCH64_MOVW_SABS_G2:
350 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
353 case R_AARCH64_MOVW_PREL_G0_NC:
354 overflow_check = false;
355 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
358 case R_AARCH64_MOVW_PREL_G0:
359 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
362 case R_AARCH64_MOVW_PREL_G1_NC:
363 overflow_check = false;
364 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
367 case R_AARCH64_MOVW_PREL_G1:
368 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
371 case R_AARCH64_MOVW_PREL_G2_NC:
372 overflow_check = false;
373 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
376 case R_AARCH64_MOVW_PREL_G2:
377 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
380 case R_AARCH64_MOVW_PREL_G3:
381 /* We're using the top bits so we can't overflow. */
382 overflow_check = false;
383 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 48,
387 /* Immediate instruction relocations. */
388 case R_AARCH64_LD_PREL_LO19:
389 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
392 case R_AARCH64_ADR_PREL_LO21:
393 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 0, 21,
396 case R_AARCH64_ADR_PREL_PG_HI21_NC:
397 overflow_check = false;
398 case R_AARCH64_ADR_PREL_PG_HI21:
399 ovf = reloc_insn_imm(RELOC_OP_PAGE, loc, val, 12, 21,
402 case R_AARCH64_ADD_ABS_LO12_NC:
403 case R_AARCH64_LDST8_ABS_LO12_NC:
404 overflow_check = false;
405 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 0, 12,
408 case R_AARCH64_LDST16_ABS_LO12_NC:
409 overflow_check = false;
410 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 1, 11,
413 case R_AARCH64_LDST32_ABS_LO12_NC:
414 overflow_check = false;
415 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 2, 10,
418 case R_AARCH64_LDST64_ABS_LO12_NC:
419 overflow_check = false;
420 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 3, 9,
423 case R_AARCH64_LDST128_ABS_LO12_NC:
424 overflow_check = false;
425 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 4, 8,
428 case R_AARCH64_TSTBR14:
429 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 14,
432 case R_AARCH64_CONDBR19:
433 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
436 case R_AARCH64_JUMP26:
437 case R_AARCH64_CALL26:
438 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 26,
443 pr_err("module %s: unsupported RELA relocation: %llu\n",
444 me->name, ELF64_R_TYPE(rel[i].r_info));
448 if (overflow_check && ovf == -ERANGE)
456 pr_err("module %s: overflow in relocation type %d val %Lx\n",
457 me->name, (int)ELF64_R_TYPE(rel[i].r_info), val);