2 * AArch64 loadable module support.
4 * Copyright (C) 2012 ARM Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 * Author: Will Deacon <will.deacon@arm.com>
21 #include <linux/bitops.h>
22 #include <linux/elf.h>
23 #include <linux/gfp.h>
24 #include <linux/kasan.h>
25 #include <linux/kernel.h>
27 #include <linux/moduleloader.h>
28 #include <linux/vmalloc.h>
29 #include <asm/alternative.h>
31 #include <asm/sections.h>
33 void *module_alloc(unsigned long size)
35 gfp_t gfp_mask = GFP_KERNEL;
38 /* Silence the initial allocation */
39 if (IS_ENABLED(CONFIG_ARM64_MODULE_PLTS))
40 gfp_mask |= __GFP_NOWARN;
42 p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base,
43 module_alloc_base + MODULES_VSIZE,
44 gfp_mask, PAGE_KERNEL_EXEC, 0,
45 NUMA_NO_NODE, __builtin_return_address(0));
47 if (!p && IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) &&
48 !IS_ENABLED(CONFIG_KASAN))
50 * KASAN can only deal with module allocations being served
51 * from the reserved module region, since the remainder of
52 * the vmalloc region is already backed by zero shadow pages,
53 * and punching holes into it is non-trivial. Since the module
54 * region is not randomized when KASAN is enabled, it is even
55 * less likely that the module region gets exhausted, so we
56 * can simply omit this fallback in that case.
58 p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base,
59 module_alloc_base + SZ_4G, GFP_KERNEL,
60 PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE,
61 __builtin_return_address(0));
63 if (p && (kasan_module_alloc(p, size) < 0)) {
71 enum aarch64_reloc_op {
78 static u64 do_reloc(enum aarch64_reloc_op reloc_op, __le32 *place, u64 val)
84 return val - (u64)place;
86 return (val & ~0xfff) - ((u64)place & ~0xfff);
91 pr_err("do_reloc: unknown relocation operation %d\n", reloc_op);
95 static int reloc_data(enum aarch64_reloc_op op, void *place, u64 val, int len)
97 s64 sval = do_reloc(op, place, val);
101 *(s16 *)place = sval;
102 if (sval < S16_MIN || sval > U16_MAX)
106 *(s32 *)place = sval;
107 if (sval < S32_MIN || sval > U32_MAX)
111 *(s64 *)place = sval;
114 pr_err("Invalid length (%d) for data relocation\n", len);
120 enum aarch64_insn_movw_imm_type {
121 AARCH64_INSN_IMM_MOVNZ,
122 AARCH64_INSN_IMM_MOVKZ,
125 static int reloc_insn_movw(enum aarch64_reloc_op op, __le32 *place, u64 val,
126 int lsb, enum aarch64_insn_movw_imm_type imm_type)
130 u32 insn = le32_to_cpu(*place);
132 sval = do_reloc(op, place, val);
135 if (imm_type == AARCH64_INSN_IMM_MOVNZ) {
137 * For signed MOVW relocations, we have to manipulate the
138 * instruction encoding depending on whether or not the
139 * immediate is less than zero.
143 /* >=0: Set the instruction to MOVZ (opcode 10b). */
147 * <0: Set the instruction to MOVN (opcode 00b).
148 * Since we've masked the opcode already, we
149 * don't need to do anything other than
150 * inverting the new immediate field.
156 /* Update the instruction with the new encoding. */
157 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm);
158 *place = cpu_to_le32(insn);
166 static int reloc_insn_imm(enum aarch64_reloc_op op, __le32 *place, u64 val,
167 int lsb, int len, enum aarch64_insn_imm_type imm_type)
171 u32 insn = le32_to_cpu(*place);
173 /* Calculate the relocation value. */
174 sval = do_reloc(op, place, val);
177 /* Extract the value bits and shift them to bit 0. */
178 imm_mask = (BIT(lsb + len) - 1) >> lsb;
179 imm = sval & imm_mask;
181 /* Update the instruction's immediate field. */
182 insn = aarch64_insn_encode_immediate(imm_type, insn, imm);
183 *place = cpu_to_le32(insn);
186 * Extract the upper value bits (including the sign bit) and
187 * shift them to bit 0.
189 sval = (s64)(sval & ~(imm_mask >> 1)) >> (len - 1);
192 * Overflow has occurred if the upper bits are not all equal to
193 * the sign bit of the value.
195 if ((u64)(sval + 1) >= 2)
201 static int reloc_insn_adrp(struct module *mod, Elf64_Shdr *sechdrs,
202 __le32 *place, u64 val)
206 if (!is_forbidden_offset_for_adrp(place))
207 return reloc_insn_imm(RELOC_OP_PAGE, place, val, 12, 21,
208 AARCH64_INSN_IMM_ADR);
210 /* patch ADRP to ADR if it is in range */
211 if (!reloc_insn_imm(RELOC_OP_PREL, place, val & ~0xfff, 0, 21,
212 AARCH64_INSN_IMM_ADR)) {
213 insn = le32_to_cpu(*place);
216 /* out of range for ADR -> emit a veneer */
217 val = module_emit_veneer_for_adrp(mod, sechdrs, place, val & ~0xfff);
220 insn = aarch64_insn_gen_branch_imm((u64)place, val,
221 AARCH64_INSN_BRANCH_NOLINK);
224 *place = cpu_to_le32(insn);
228 int apply_relocate_add(Elf64_Shdr *sechdrs,
230 unsigned int symindex,
240 Elf64_Rela *rel = (void *)sechdrs[relsec].sh_addr;
242 for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
243 /* loc corresponds to P in the AArch64 ELF document. */
244 loc = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
247 /* sym is the ELF symbol we're referring to. */
248 sym = (Elf64_Sym *)sechdrs[symindex].sh_addr
249 + ELF64_R_SYM(rel[i].r_info);
251 /* val corresponds to (S + A) in the AArch64 ELF document. */
252 val = sym->st_value + rel[i].r_addend;
254 /* Check for overflow by default. */
255 overflow_check = true;
257 /* Perform the static relocation. */
258 switch (ELF64_R_TYPE(rel[i].r_info)) {
259 /* Null relocations. */
265 /* Data relocations. */
266 case R_AARCH64_ABS64:
267 overflow_check = false;
268 ovf = reloc_data(RELOC_OP_ABS, loc, val, 64);
270 case R_AARCH64_ABS32:
271 ovf = reloc_data(RELOC_OP_ABS, loc, val, 32);
273 case R_AARCH64_ABS16:
274 ovf = reloc_data(RELOC_OP_ABS, loc, val, 16);
276 case R_AARCH64_PREL64:
277 overflow_check = false;
278 ovf = reloc_data(RELOC_OP_PREL, loc, val, 64);
280 case R_AARCH64_PREL32:
281 ovf = reloc_data(RELOC_OP_PREL, loc, val, 32);
283 case R_AARCH64_PREL16:
284 ovf = reloc_data(RELOC_OP_PREL, loc, val, 16);
287 /* MOVW instruction relocations. */
288 case R_AARCH64_MOVW_UABS_G0_NC:
289 overflow_check = false;
290 case R_AARCH64_MOVW_UABS_G0:
291 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
292 AARCH64_INSN_IMM_MOVKZ);
294 case R_AARCH64_MOVW_UABS_G1_NC:
295 overflow_check = false;
296 case R_AARCH64_MOVW_UABS_G1:
297 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
298 AARCH64_INSN_IMM_MOVKZ);
300 case R_AARCH64_MOVW_UABS_G2_NC:
301 overflow_check = false;
302 case R_AARCH64_MOVW_UABS_G2:
303 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
304 AARCH64_INSN_IMM_MOVKZ);
306 case R_AARCH64_MOVW_UABS_G3:
307 /* We're using the top bits so we can't overflow. */
308 overflow_check = false;
309 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 48,
310 AARCH64_INSN_IMM_MOVKZ);
312 case R_AARCH64_MOVW_SABS_G0:
313 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
314 AARCH64_INSN_IMM_MOVNZ);
316 case R_AARCH64_MOVW_SABS_G1:
317 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
318 AARCH64_INSN_IMM_MOVNZ);
320 case R_AARCH64_MOVW_SABS_G2:
321 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
322 AARCH64_INSN_IMM_MOVNZ);
324 case R_AARCH64_MOVW_PREL_G0_NC:
325 overflow_check = false;
326 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
327 AARCH64_INSN_IMM_MOVKZ);
329 case R_AARCH64_MOVW_PREL_G0:
330 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
331 AARCH64_INSN_IMM_MOVNZ);
333 case R_AARCH64_MOVW_PREL_G1_NC:
334 overflow_check = false;
335 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
336 AARCH64_INSN_IMM_MOVKZ);
338 case R_AARCH64_MOVW_PREL_G1:
339 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
340 AARCH64_INSN_IMM_MOVNZ);
342 case R_AARCH64_MOVW_PREL_G2_NC:
343 overflow_check = false;
344 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
345 AARCH64_INSN_IMM_MOVKZ);
347 case R_AARCH64_MOVW_PREL_G2:
348 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
349 AARCH64_INSN_IMM_MOVNZ);
351 case R_AARCH64_MOVW_PREL_G3:
352 /* We're using the top bits so we can't overflow. */
353 overflow_check = false;
354 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 48,
355 AARCH64_INSN_IMM_MOVNZ);
358 /* Immediate instruction relocations. */
359 case R_AARCH64_LD_PREL_LO19:
360 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
361 AARCH64_INSN_IMM_19);
363 case R_AARCH64_ADR_PREL_LO21:
364 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 0, 21,
365 AARCH64_INSN_IMM_ADR);
367 case R_AARCH64_ADR_PREL_PG_HI21_NC:
368 overflow_check = false;
369 case R_AARCH64_ADR_PREL_PG_HI21:
370 ovf = reloc_insn_adrp(me, sechdrs, loc, val);
371 if (ovf && ovf != -ERANGE)
374 case R_AARCH64_ADD_ABS_LO12_NC:
375 case R_AARCH64_LDST8_ABS_LO12_NC:
376 overflow_check = false;
377 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 0, 12,
378 AARCH64_INSN_IMM_12);
380 case R_AARCH64_LDST16_ABS_LO12_NC:
381 overflow_check = false;
382 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 1, 11,
383 AARCH64_INSN_IMM_12);
385 case R_AARCH64_LDST32_ABS_LO12_NC:
386 overflow_check = false;
387 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 2, 10,
388 AARCH64_INSN_IMM_12);
390 case R_AARCH64_LDST64_ABS_LO12_NC:
391 overflow_check = false;
392 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 3, 9,
393 AARCH64_INSN_IMM_12);
395 case R_AARCH64_LDST128_ABS_LO12_NC:
396 overflow_check = false;
397 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 4, 8,
398 AARCH64_INSN_IMM_12);
400 case R_AARCH64_TSTBR14:
401 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 14,
402 AARCH64_INSN_IMM_14);
404 case R_AARCH64_CONDBR19:
405 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
406 AARCH64_INSN_IMM_19);
408 case R_AARCH64_JUMP26:
409 case R_AARCH64_CALL26:
410 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 26,
411 AARCH64_INSN_IMM_26);
413 if (IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) &&
415 val = module_emit_plt_entry(me, sechdrs, loc, &rel[i], sym);
418 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2,
419 26, AARCH64_INSN_IMM_26);
424 pr_err("module %s: unsupported RELA relocation: %llu\n",
425 me->name, ELF64_R_TYPE(rel[i].r_info));
429 if (overflow_check && ovf == -ERANGE)
437 pr_err("module %s: overflow in relocation type %d val %Lx\n",
438 me->name, (int)ELF64_R_TYPE(rel[i].r_info), val);
442 int module_finalize(const Elf_Ehdr *hdr,
443 const Elf_Shdr *sechdrs,
446 const Elf_Shdr *s, *se;
447 const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;
449 for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++) {
450 if (strcmp(".altinstructions", secstrs + s->sh_name) == 0)
451 apply_alternatives_module((void *)s->sh_addr, s->sh_size);
452 #ifdef CONFIG_ARM64_MODULE_PLTS
453 if (IS_ENABLED(CONFIG_DYNAMIC_FTRACE) &&
454 !strcmp(".text.ftrace_trampoline", secstrs + s->sh_name))
455 me->arch.ftrace_trampoline = (void *)s->sh_addr;