1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Huawei Ltd.
4 * Author: Jiang Liu <liuj97@gmail.com>
6 * Copyright (C) 2014-2016 Zi Shen Lim <zlim.lnx@gmail.com>
8 #include <linux/bitops.h>
10 #include <linux/compiler.h>
11 #include <linux/kernel.h>
13 #include <linux/smp.h>
14 #include <linux/spinlock.h>
15 #include <linux/stop_machine.h>
16 #include <linux/types.h>
17 #include <linux/uaccess.h>
19 #include <asm/cacheflush.h>
20 #include <asm/debug-monitors.h>
21 #include <asm/fixmap.h>
23 #include <asm/kprobes.h>
25 #define AARCH64_INSN_SF_BIT BIT(31)
26 #define AARCH64_INSN_N_BIT BIT(22)
27 #define AARCH64_INSN_LSL_12 BIT(22)
29 static int aarch64_insn_encoding_class[] = {
30 AARCH64_INSN_CLS_UNKNOWN,
31 AARCH64_INSN_CLS_UNKNOWN,
32 AARCH64_INSN_CLS_UNKNOWN,
33 AARCH64_INSN_CLS_UNKNOWN,
34 AARCH64_INSN_CLS_LDST,
35 AARCH64_INSN_CLS_DP_REG,
36 AARCH64_INSN_CLS_LDST,
37 AARCH64_INSN_CLS_DP_FPSIMD,
38 AARCH64_INSN_CLS_DP_IMM,
39 AARCH64_INSN_CLS_DP_IMM,
40 AARCH64_INSN_CLS_BR_SYS,
41 AARCH64_INSN_CLS_BR_SYS,
42 AARCH64_INSN_CLS_LDST,
43 AARCH64_INSN_CLS_DP_REG,
44 AARCH64_INSN_CLS_LDST,
45 AARCH64_INSN_CLS_DP_FPSIMD,
48 enum aarch64_insn_encoding_class __kprobes aarch64_get_insn_class(u32 insn)
50 return aarch64_insn_encoding_class[(insn >> 25) & 0xf];
53 /* NOP is an alias of HINT */
54 bool __kprobes aarch64_insn_is_nop(u32 insn)
56 if (!aarch64_insn_is_hint(insn))
59 switch (insn & 0xFE0) {
60 case AARCH64_INSN_HINT_YIELD:
61 case AARCH64_INSN_HINT_WFE:
62 case AARCH64_INSN_HINT_WFI:
63 case AARCH64_INSN_HINT_SEV:
64 case AARCH64_INSN_HINT_SEVL:
71 bool aarch64_insn_is_branch_imm(u32 insn)
73 return (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn) ||
74 aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn) ||
75 aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) ||
76 aarch64_insn_is_bcond(insn));
79 static DEFINE_RAW_SPINLOCK(patch_lock);
81 static void __kprobes *patch_map(void *addr, int fixmap)
83 unsigned long uintaddr = (uintptr_t) addr;
84 bool module = !core_kernel_text(uintaddr);
87 if (module && IS_ENABLED(CONFIG_STRICT_MODULE_RWX))
88 page = vmalloc_to_page(addr);
90 page = phys_to_page(__pa_symbol(addr));
95 return (void *)set_fixmap_offset(fixmap, page_to_phys(page) +
96 (uintaddr & ~PAGE_MASK));
99 static void __kprobes patch_unmap(int fixmap)
101 clear_fixmap(fixmap);
104 * In ARMv8-A, A64 instructions have a fixed length of 32 bits and are always
107 int __kprobes aarch64_insn_read(void *addr, u32 *insnp)
112 ret = probe_kernel_read(&val, addr, AARCH64_INSN_SIZE);
114 *insnp = le32_to_cpu(val);
119 static int __kprobes __aarch64_insn_write(void *addr, __le32 insn)
122 unsigned long flags = 0;
125 raw_spin_lock_irqsave(&patch_lock, flags);
126 waddr = patch_map(addr, FIX_TEXT_POKE0);
128 ret = probe_kernel_write(waddr, &insn, AARCH64_INSN_SIZE);
130 patch_unmap(FIX_TEXT_POKE0);
131 raw_spin_unlock_irqrestore(&patch_lock, flags);
136 int __kprobes aarch64_insn_write(void *addr, u32 insn)
138 return __aarch64_insn_write(addr, cpu_to_le32(insn));
141 bool __kprobes aarch64_insn_uses_literal(u32 insn)
143 /* ldr/ldrsw (literal), prfm */
145 return aarch64_insn_is_ldr_lit(insn) ||
146 aarch64_insn_is_ldrsw_lit(insn) ||
147 aarch64_insn_is_adr_adrp(insn) ||
148 aarch64_insn_is_prfm_lit(insn);
151 bool __kprobes aarch64_insn_is_branch(u32 insn)
153 /* b, bl, cb*, tb*, b.cond, br, blr */
155 return aarch64_insn_is_b(insn) ||
156 aarch64_insn_is_bl(insn) ||
157 aarch64_insn_is_cbz(insn) ||
158 aarch64_insn_is_cbnz(insn) ||
159 aarch64_insn_is_tbz(insn) ||
160 aarch64_insn_is_tbnz(insn) ||
161 aarch64_insn_is_ret(insn) ||
162 aarch64_insn_is_br(insn) ||
163 aarch64_insn_is_blr(insn) ||
164 aarch64_insn_is_bcond(insn);
167 int __kprobes aarch64_insn_patch_text_nosync(void *addr, u32 insn)
172 /* A64 instructions must be word aligned */
173 if ((uintptr_t)tp & 0x3)
176 ret = aarch64_insn_write(tp, insn);
178 __flush_icache_range((uintptr_t)tp,
179 (uintptr_t)tp + AARCH64_INSN_SIZE);
184 struct aarch64_insn_patch {
191 static int __kprobes aarch64_insn_patch_text_cb(void *arg)
194 struct aarch64_insn_patch *pp = arg;
196 /* The first CPU becomes master */
197 if (atomic_inc_return(&pp->cpu_count) == 1) {
198 for (i = 0; ret == 0 && i < pp->insn_cnt; i++)
199 ret = aarch64_insn_patch_text_nosync(pp->text_addrs[i],
201 /* Notify other processors with an additional increment. */
202 atomic_inc(&pp->cpu_count);
204 while (atomic_read(&pp->cpu_count) <= num_online_cpus())
212 int __kprobes aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt)
214 struct aarch64_insn_patch patch = {
218 .cpu_count = ATOMIC_INIT(0),
224 return stop_machine_cpuslocked(aarch64_insn_patch_text_cb, &patch,
228 static int __kprobes aarch64_get_imm_shift_mask(enum aarch64_insn_imm_type type,
229 u32 *maskp, int *shiftp)
235 case AARCH64_INSN_IMM_26:
239 case AARCH64_INSN_IMM_19:
243 case AARCH64_INSN_IMM_16:
247 case AARCH64_INSN_IMM_14:
251 case AARCH64_INSN_IMM_12:
255 case AARCH64_INSN_IMM_9:
259 case AARCH64_INSN_IMM_7:
263 case AARCH64_INSN_IMM_6:
264 case AARCH64_INSN_IMM_S:
268 case AARCH64_INSN_IMM_R:
272 case AARCH64_INSN_IMM_N:
286 #define ADR_IMM_HILOSPLIT 2
287 #define ADR_IMM_SIZE SZ_2M
288 #define ADR_IMM_LOMASK ((1 << ADR_IMM_HILOSPLIT) - 1)
289 #define ADR_IMM_HIMASK ((ADR_IMM_SIZE >> ADR_IMM_HILOSPLIT) - 1)
290 #define ADR_IMM_LOSHIFT 29
291 #define ADR_IMM_HISHIFT 5
293 u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn)
295 u32 immlo, immhi, mask;
299 case AARCH64_INSN_IMM_ADR:
301 immlo = (insn >> ADR_IMM_LOSHIFT) & ADR_IMM_LOMASK;
302 immhi = (insn >> ADR_IMM_HISHIFT) & ADR_IMM_HIMASK;
303 insn = (immhi << ADR_IMM_HILOSPLIT) | immlo;
304 mask = ADR_IMM_SIZE - 1;
307 if (aarch64_get_imm_shift_mask(type, &mask, &shift) < 0) {
308 pr_err("aarch64_insn_decode_immediate: unknown immediate encoding %d\n",
314 return (insn >> shift) & mask;
317 u32 __kprobes aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
320 u32 immlo, immhi, mask;
323 if (insn == AARCH64_BREAK_FAULT)
324 return AARCH64_BREAK_FAULT;
327 case AARCH64_INSN_IMM_ADR:
329 immlo = (imm & ADR_IMM_LOMASK) << ADR_IMM_LOSHIFT;
330 imm >>= ADR_IMM_HILOSPLIT;
331 immhi = (imm & ADR_IMM_HIMASK) << ADR_IMM_HISHIFT;
333 mask = ((ADR_IMM_LOMASK << ADR_IMM_LOSHIFT) |
334 (ADR_IMM_HIMASK << ADR_IMM_HISHIFT));
337 if (aarch64_get_imm_shift_mask(type, &mask, &shift) < 0) {
338 pr_err("aarch64_insn_encode_immediate: unknown immediate encoding %d\n",
340 return AARCH64_BREAK_FAULT;
344 /* Update the immediate field. */
345 insn &= ~(mask << shift);
346 insn |= (imm & mask) << shift;
351 u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type,
357 case AARCH64_INSN_REGTYPE_RT:
358 case AARCH64_INSN_REGTYPE_RD:
361 case AARCH64_INSN_REGTYPE_RN:
364 case AARCH64_INSN_REGTYPE_RT2:
365 case AARCH64_INSN_REGTYPE_RA:
368 case AARCH64_INSN_REGTYPE_RM:
372 pr_err("%s: unknown register type encoding %d\n", __func__,
377 return (insn >> shift) & GENMASK(4, 0);
380 static u32 aarch64_insn_encode_register(enum aarch64_insn_register_type type,
382 enum aarch64_insn_register reg)
386 if (insn == AARCH64_BREAK_FAULT)
387 return AARCH64_BREAK_FAULT;
389 if (reg < AARCH64_INSN_REG_0 || reg > AARCH64_INSN_REG_SP) {
390 pr_err("%s: unknown register encoding %d\n", __func__, reg);
391 return AARCH64_BREAK_FAULT;
395 case AARCH64_INSN_REGTYPE_RT:
396 case AARCH64_INSN_REGTYPE_RD:
399 case AARCH64_INSN_REGTYPE_RN:
402 case AARCH64_INSN_REGTYPE_RT2:
403 case AARCH64_INSN_REGTYPE_RA:
406 case AARCH64_INSN_REGTYPE_RM:
407 case AARCH64_INSN_REGTYPE_RS:
411 pr_err("%s: unknown register type encoding %d\n", __func__,
413 return AARCH64_BREAK_FAULT;
416 insn &= ~(GENMASK(4, 0) << shift);
417 insn |= reg << shift;
422 static u32 aarch64_insn_encode_ldst_size(enum aarch64_insn_size_type type,
428 case AARCH64_INSN_SIZE_8:
431 case AARCH64_INSN_SIZE_16:
434 case AARCH64_INSN_SIZE_32:
437 case AARCH64_INSN_SIZE_64:
441 pr_err("%s: unknown size encoding %d\n", __func__, type);
442 return AARCH64_BREAK_FAULT;
445 insn &= ~GENMASK(31, 30);
451 static inline long branch_imm_common(unsigned long pc, unsigned long addr,
456 if ((pc & 0x3) || (addr & 0x3)) {
457 pr_err("%s: A64 instructions must be word aligned\n", __func__);
461 offset = ((long)addr - (long)pc);
463 if (offset < -range || offset >= range) {
464 pr_err("%s: offset out of range\n", __func__);
471 u32 __kprobes aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
472 enum aarch64_insn_branch_type type)
478 * B/BL support [-128M, 128M) offset
479 * ARM64 virtual address arrangement guarantees all kernel and module
480 * texts are within +/-128M.
482 offset = branch_imm_common(pc, addr, SZ_128M);
483 if (offset >= SZ_128M)
484 return AARCH64_BREAK_FAULT;
487 case AARCH64_INSN_BRANCH_LINK:
488 insn = aarch64_insn_get_bl_value();
490 case AARCH64_INSN_BRANCH_NOLINK:
491 insn = aarch64_insn_get_b_value();
494 pr_err("%s: unknown branch encoding %d\n", __func__, type);
495 return AARCH64_BREAK_FAULT;
498 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_26, insn,
502 u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
503 enum aarch64_insn_register reg,
504 enum aarch64_insn_variant variant,
505 enum aarch64_insn_branch_type type)
510 offset = branch_imm_common(pc, addr, SZ_1M);
512 return AARCH64_BREAK_FAULT;
515 case AARCH64_INSN_BRANCH_COMP_ZERO:
516 insn = aarch64_insn_get_cbz_value();
518 case AARCH64_INSN_BRANCH_COMP_NONZERO:
519 insn = aarch64_insn_get_cbnz_value();
522 pr_err("%s: unknown branch encoding %d\n", __func__, type);
523 return AARCH64_BREAK_FAULT;
527 case AARCH64_INSN_VARIANT_32BIT:
529 case AARCH64_INSN_VARIANT_64BIT:
530 insn |= AARCH64_INSN_SF_BIT;
533 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
534 return AARCH64_BREAK_FAULT;
537 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
539 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
543 u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
544 enum aarch64_insn_condition cond)
549 offset = branch_imm_common(pc, addr, SZ_1M);
551 insn = aarch64_insn_get_bcond_value();
553 if (cond < AARCH64_INSN_COND_EQ || cond > AARCH64_INSN_COND_AL) {
554 pr_err("%s: unknown condition encoding %d\n", __func__, cond);
555 return AARCH64_BREAK_FAULT;
559 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
563 u32 __kprobes aarch64_insn_gen_hint(enum aarch64_insn_hint_op op)
565 return aarch64_insn_get_hint_value() | op;
568 u32 __kprobes aarch64_insn_gen_nop(void)
570 return aarch64_insn_gen_hint(AARCH64_INSN_HINT_NOP);
573 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
574 enum aarch64_insn_branch_type type)
579 case AARCH64_INSN_BRANCH_NOLINK:
580 insn = aarch64_insn_get_br_value();
582 case AARCH64_INSN_BRANCH_LINK:
583 insn = aarch64_insn_get_blr_value();
585 case AARCH64_INSN_BRANCH_RETURN:
586 insn = aarch64_insn_get_ret_value();
589 pr_err("%s: unknown branch encoding %d\n", __func__, type);
590 return AARCH64_BREAK_FAULT;
593 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, reg);
596 u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
597 enum aarch64_insn_register base,
598 enum aarch64_insn_register offset,
599 enum aarch64_insn_size_type size,
600 enum aarch64_insn_ldst_type type)
605 case AARCH64_INSN_LDST_LOAD_REG_OFFSET:
606 insn = aarch64_insn_get_ldr_reg_value();
608 case AARCH64_INSN_LDST_STORE_REG_OFFSET:
609 insn = aarch64_insn_get_str_reg_value();
612 pr_err("%s: unknown load/store encoding %d\n", __func__, type);
613 return AARCH64_BREAK_FAULT;
616 insn = aarch64_insn_encode_ldst_size(size, insn);
618 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
620 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
623 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
627 u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
628 enum aarch64_insn_register reg2,
629 enum aarch64_insn_register base,
631 enum aarch64_insn_variant variant,
632 enum aarch64_insn_ldst_type type)
638 case AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX:
639 insn = aarch64_insn_get_ldp_pre_value();
641 case AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX:
642 insn = aarch64_insn_get_stp_pre_value();
644 case AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX:
645 insn = aarch64_insn_get_ldp_post_value();
647 case AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX:
648 insn = aarch64_insn_get_stp_post_value();
651 pr_err("%s: unknown load/store encoding %d\n", __func__, type);
652 return AARCH64_BREAK_FAULT;
656 case AARCH64_INSN_VARIANT_32BIT:
657 if ((offset & 0x3) || (offset < -256) || (offset > 252)) {
658 pr_err("%s: offset must be multiples of 4 in the range of [-256, 252] %d\n",
660 return AARCH64_BREAK_FAULT;
664 case AARCH64_INSN_VARIANT_64BIT:
665 if ((offset & 0x7) || (offset < -512) || (offset > 504)) {
666 pr_err("%s: offset must be multiples of 8 in the range of [-512, 504] %d\n",
668 return AARCH64_BREAK_FAULT;
671 insn |= AARCH64_INSN_SF_BIT;
674 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
675 return AARCH64_BREAK_FAULT;
678 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn,
681 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT2, insn,
684 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
687 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_7, insn,
691 u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,
692 enum aarch64_insn_register base,
693 enum aarch64_insn_register state,
694 enum aarch64_insn_size_type size,
695 enum aarch64_insn_ldst_type type)
700 case AARCH64_INSN_LDST_LOAD_EX:
701 insn = aarch64_insn_get_load_ex_value();
703 case AARCH64_INSN_LDST_STORE_EX:
704 insn = aarch64_insn_get_store_ex_value();
707 pr_err("%s: unknown load/store exclusive encoding %d\n", __func__, type);
708 return AARCH64_BREAK_FAULT;
711 insn = aarch64_insn_encode_ldst_size(size, insn);
713 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn,
716 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
719 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT2, insn,
720 AARCH64_INSN_REG_ZR);
722 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RS, insn,
726 u32 aarch64_insn_gen_ldadd(enum aarch64_insn_register result,
727 enum aarch64_insn_register address,
728 enum aarch64_insn_register value,
729 enum aarch64_insn_size_type size)
731 u32 insn = aarch64_insn_get_ldadd_value();
734 case AARCH64_INSN_SIZE_32:
735 case AARCH64_INSN_SIZE_64:
738 pr_err("%s: unimplemented size encoding %d\n", __func__, size);
739 return AARCH64_BREAK_FAULT;
742 insn = aarch64_insn_encode_ldst_size(size, insn);
744 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn,
747 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
750 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RS, insn,
754 u32 aarch64_insn_gen_stadd(enum aarch64_insn_register address,
755 enum aarch64_insn_register value,
756 enum aarch64_insn_size_type size)
759 * STADD is simply encoded as an alias for LDADD with XZR as
760 * the destination register.
762 return aarch64_insn_gen_ldadd(AARCH64_INSN_REG_ZR, address,
766 static u32 aarch64_insn_encode_prfm_imm(enum aarch64_insn_prfm_type type,
767 enum aarch64_insn_prfm_target target,
768 enum aarch64_insn_prfm_policy policy,
771 u32 imm_type = 0, imm_target = 0, imm_policy = 0;
774 case AARCH64_INSN_PRFM_TYPE_PLD:
776 case AARCH64_INSN_PRFM_TYPE_PLI:
779 case AARCH64_INSN_PRFM_TYPE_PST:
783 pr_err("%s: unknown prfm type encoding %d\n", __func__, type);
784 return AARCH64_BREAK_FAULT;
788 case AARCH64_INSN_PRFM_TARGET_L1:
790 case AARCH64_INSN_PRFM_TARGET_L2:
793 case AARCH64_INSN_PRFM_TARGET_L3:
797 pr_err("%s: unknown prfm target encoding %d\n", __func__, target);
798 return AARCH64_BREAK_FAULT;
802 case AARCH64_INSN_PRFM_POLICY_KEEP:
804 case AARCH64_INSN_PRFM_POLICY_STRM:
808 pr_err("%s: unknown prfm policy encoding %d\n", __func__, policy);
809 return AARCH64_BREAK_FAULT;
812 /* In this case, imm5 is encoded into Rt field. */
813 insn &= ~GENMASK(4, 0);
814 insn |= imm_policy | (imm_target << 1) | (imm_type << 3);
819 u32 aarch64_insn_gen_prefetch(enum aarch64_insn_register base,
820 enum aarch64_insn_prfm_type type,
821 enum aarch64_insn_prfm_target target,
822 enum aarch64_insn_prfm_policy policy)
824 u32 insn = aarch64_insn_get_prfm_value();
826 insn = aarch64_insn_encode_ldst_size(AARCH64_INSN_SIZE_64, insn);
828 insn = aarch64_insn_encode_prfm_imm(type, target, policy, insn);
830 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
833 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_12, insn, 0);
836 u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
837 enum aarch64_insn_register src,
838 int imm, enum aarch64_insn_variant variant,
839 enum aarch64_insn_adsb_type type)
844 case AARCH64_INSN_ADSB_ADD:
845 insn = aarch64_insn_get_add_imm_value();
847 case AARCH64_INSN_ADSB_SUB:
848 insn = aarch64_insn_get_sub_imm_value();
850 case AARCH64_INSN_ADSB_ADD_SETFLAGS:
851 insn = aarch64_insn_get_adds_imm_value();
853 case AARCH64_INSN_ADSB_SUB_SETFLAGS:
854 insn = aarch64_insn_get_subs_imm_value();
857 pr_err("%s: unknown add/sub encoding %d\n", __func__, type);
858 return AARCH64_BREAK_FAULT;
862 case AARCH64_INSN_VARIANT_32BIT:
864 case AARCH64_INSN_VARIANT_64BIT:
865 insn |= AARCH64_INSN_SF_BIT;
868 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
869 return AARCH64_BREAK_FAULT;
872 /* We can't encode more than a 24bit value (12bit + 12bit shift) */
873 if (imm & ~(BIT(24) - 1))
876 /* If we have something in the top 12 bits... */
877 if (imm & ~(SZ_4K - 1)) {
878 /* ... and in the low 12 bits -> error */
879 if (imm & (SZ_4K - 1))
883 insn |= AARCH64_INSN_LSL_12;
886 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
888 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
890 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_12, insn, imm);
893 pr_err("%s: invalid immediate encoding %d\n", __func__, imm);
894 return AARCH64_BREAK_FAULT;
897 u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
898 enum aarch64_insn_register src,
900 enum aarch64_insn_variant variant,
901 enum aarch64_insn_bitfield_type type)
907 case AARCH64_INSN_BITFIELD_MOVE:
908 insn = aarch64_insn_get_bfm_value();
910 case AARCH64_INSN_BITFIELD_MOVE_UNSIGNED:
911 insn = aarch64_insn_get_ubfm_value();
913 case AARCH64_INSN_BITFIELD_MOVE_SIGNED:
914 insn = aarch64_insn_get_sbfm_value();
917 pr_err("%s: unknown bitfield encoding %d\n", __func__, type);
918 return AARCH64_BREAK_FAULT;
922 case AARCH64_INSN_VARIANT_32BIT:
923 mask = GENMASK(4, 0);
925 case AARCH64_INSN_VARIANT_64BIT:
926 insn |= AARCH64_INSN_SF_BIT | AARCH64_INSN_N_BIT;
927 mask = GENMASK(5, 0);
930 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
931 return AARCH64_BREAK_FAULT;
935 pr_err("%s: invalid immr encoding %d\n", __func__, immr);
936 return AARCH64_BREAK_FAULT;
939 pr_err("%s: invalid imms encoding %d\n", __func__, imms);
940 return AARCH64_BREAK_FAULT;
943 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
945 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
947 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_R, insn, immr);
949 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_S, insn, imms);
952 u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
954 enum aarch64_insn_variant variant,
955 enum aarch64_insn_movewide_type type)
960 case AARCH64_INSN_MOVEWIDE_ZERO:
961 insn = aarch64_insn_get_movz_value();
963 case AARCH64_INSN_MOVEWIDE_KEEP:
964 insn = aarch64_insn_get_movk_value();
966 case AARCH64_INSN_MOVEWIDE_INVERSE:
967 insn = aarch64_insn_get_movn_value();
970 pr_err("%s: unknown movewide encoding %d\n", __func__, type);
971 return AARCH64_BREAK_FAULT;
974 if (imm & ~(SZ_64K - 1)) {
975 pr_err("%s: invalid immediate encoding %d\n", __func__, imm);
976 return AARCH64_BREAK_FAULT;
980 case AARCH64_INSN_VARIANT_32BIT:
981 if (shift != 0 && shift != 16) {
982 pr_err("%s: invalid shift encoding %d\n", __func__,
984 return AARCH64_BREAK_FAULT;
987 case AARCH64_INSN_VARIANT_64BIT:
988 insn |= AARCH64_INSN_SF_BIT;
989 if (shift != 0 && shift != 16 && shift != 32 && shift != 48) {
990 pr_err("%s: invalid shift encoding %d\n", __func__,
992 return AARCH64_BREAK_FAULT;
996 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
997 return AARCH64_BREAK_FAULT;
1000 insn |= (shift >> 4) << 21;
1002 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1004 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm);
1007 u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
1008 enum aarch64_insn_register src,
1009 enum aarch64_insn_register reg,
1011 enum aarch64_insn_variant variant,
1012 enum aarch64_insn_adsb_type type)
1017 case AARCH64_INSN_ADSB_ADD:
1018 insn = aarch64_insn_get_add_value();
1020 case AARCH64_INSN_ADSB_SUB:
1021 insn = aarch64_insn_get_sub_value();
1023 case AARCH64_INSN_ADSB_ADD_SETFLAGS:
1024 insn = aarch64_insn_get_adds_value();
1026 case AARCH64_INSN_ADSB_SUB_SETFLAGS:
1027 insn = aarch64_insn_get_subs_value();
1030 pr_err("%s: unknown add/sub encoding %d\n", __func__, type);
1031 return AARCH64_BREAK_FAULT;
1035 case AARCH64_INSN_VARIANT_32BIT:
1036 if (shift & ~(SZ_32 - 1)) {
1037 pr_err("%s: invalid shift encoding %d\n", __func__,
1039 return AARCH64_BREAK_FAULT;
1042 case AARCH64_INSN_VARIANT_64BIT:
1043 insn |= AARCH64_INSN_SF_BIT;
1044 if (shift & ~(SZ_64 - 1)) {
1045 pr_err("%s: invalid shift encoding %d\n", __func__,
1047 return AARCH64_BREAK_FAULT;
1051 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1052 return AARCH64_BREAK_FAULT;
1056 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1058 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
1060 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
1062 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);
1065 u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
1066 enum aarch64_insn_register src,
1067 enum aarch64_insn_variant variant,
1068 enum aarch64_insn_data1_type type)
1073 case AARCH64_INSN_DATA1_REVERSE_16:
1074 insn = aarch64_insn_get_rev16_value();
1076 case AARCH64_INSN_DATA1_REVERSE_32:
1077 insn = aarch64_insn_get_rev32_value();
1079 case AARCH64_INSN_DATA1_REVERSE_64:
1080 if (variant != AARCH64_INSN_VARIANT_64BIT) {
1081 pr_err("%s: invalid variant for reverse64 %d\n",
1083 return AARCH64_BREAK_FAULT;
1085 insn = aarch64_insn_get_rev64_value();
1088 pr_err("%s: unknown data1 encoding %d\n", __func__, type);
1089 return AARCH64_BREAK_FAULT;
1093 case AARCH64_INSN_VARIANT_32BIT:
1095 case AARCH64_INSN_VARIANT_64BIT:
1096 insn |= AARCH64_INSN_SF_BIT;
1099 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1100 return AARCH64_BREAK_FAULT;
1103 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1105 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
1108 u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
1109 enum aarch64_insn_register src,
1110 enum aarch64_insn_register reg,
1111 enum aarch64_insn_variant variant,
1112 enum aarch64_insn_data2_type type)
1117 case AARCH64_INSN_DATA2_UDIV:
1118 insn = aarch64_insn_get_udiv_value();
1120 case AARCH64_INSN_DATA2_SDIV:
1121 insn = aarch64_insn_get_sdiv_value();
1123 case AARCH64_INSN_DATA2_LSLV:
1124 insn = aarch64_insn_get_lslv_value();
1126 case AARCH64_INSN_DATA2_LSRV:
1127 insn = aarch64_insn_get_lsrv_value();
1129 case AARCH64_INSN_DATA2_ASRV:
1130 insn = aarch64_insn_get_asrv_value();
1132 case AARCH64_INSN_DATA2_RORV:
1133 insn = aarch64_insn_get_rorv_value();
1136 pr_err("%s: unknown data2 encoding %d\n", __func__, type);
1137 return AARCH64_BREAK_FAULT;
1141 case AARCH64_INSN_VARIANT_32BIT:
1143 case AARCH64_INSN_VARIANT_64BIT:
1144 insn |= AARCH64_INSN_SF_BIT;
1147 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1148 return AARCH64_BREAK_FAULT;
1151 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1153 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
1155 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
1158 u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
1159 enum aarch64_insn_register src,
1160 enum aarch64_insn_register reg1,
1161 enum aarch64_insn_register reg2,
1162 enum aarch64_insn_variant variant,
1163 enum aarch64_insn_data3_type type)
1168 case AARCH64_INSN_DATA3_MADD:
1169 insn = aarch64_insn_get_madd_value();
1171 case AARCH64_INSN_DATA3_MSUB:
1172 insn = aarch64_insn_get_msub_value();
1175 pr_err("%s: unknown data3 encoding %d\n", __func__, type);
1176 return AARCH64_BREAK_FAULT;
1180 case AARCH64_INSN_VARIANT_32BIT:
1182 case AARCH64_INSN_VARIANT_64BIT:
1183 insn |= AARCH64_INSN_SF_BIT;
1186 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1187 return AARCH64_BREAK_FAULT;
1190 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1192 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RA, insn, src);
1194 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
1197 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
1201 u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
1202 enum aarch64_insn_register src,
1203 enum aarch64_insn_register reg,
1205 enum aarch64_insn_variant variant,
1206 enum aarch64_insn_logic_type type)
1211 case AARCH64_INSN_LOGIC_AND:
1212 insn = aarch64_insn_get_and_value();
1214 case AARCH64_INSN_LOGIC_BIC:
1215 insn = aarch64_insn_get_bic_value();
1217 case AARCH64_INSN_LOGIC_ORR:
1218 insn = aarch64_insn_get_orr_value();
1220 case AARCH64_INSN_LOGIC_ORN:
1221 insn = aarch64_insn_get_orn_value();
1223 case AARCH64_INSN_LOGIC_EOR:
1224 insn = aarch64_insn_get_eor_value();
1226 case AARCH64_INSN_LOGIC_EON:
1227 insn = aarch64_insn_get_eon_value();
1229 case AARCH64_INSN_LOGIC_AND_SETFLAGS:
1230 insn = aarch64_insn_get_ands_value();
1232 case AARCH64_INSN_LOGIC_BIC_SETFLAGS:
1233 insn = aarch64_insn_get_bics_value();
1236 pr_err("%s: unknown logical encoding %d\n", __func__, type);
1237 return AARCH64_BREAK_FAULT;
1241 case AARCH64_INSN_VARIANT_32BIT:
1242 if (shift & ~(SZ_32 - 1)) {
1243 pr_err("%s: invalid shift encoding %d\n", __func__,
1245 return AARCH64_BREAK_FAULT;
1248 case AARCH64_INSN_VARIANT_64BIT:
1249 insn |= AARCH64_INSN_SF_BIT;
1250 if (shift & ~(SZ_64 - 1)) {
1251 pr_err("%s: invalid shift encoding %d\n", __func__,
1253 return AARCH64_BREAK_FAULT;
1257 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1258 return AARCH64_BREAK_FAULT;
1262 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1264 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
1266 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
1268 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);
1271 u32 aarch64_insn_gen_adr(unsigned long pc, unsigned long addr,
1272 enum aarch64_insn_register reg,
1273 enum aarch64_insn_adr_type type)
1279 case AARCH64_INSN_ADR_TYPE_ADR:
1280 insn = aarch64_insn_get_adr_value();
1283 case AARCH64_INSN_ADR_TYPE_ADRP:
1284 insn = aarch64_insn_get_adrp_value();
1285 offset = (addr - ALIGN_DOWN(pc, SZ_4K)) >> 12;
1288 pr_err("%s: unknown adr encoding %d\n", __func__, type);
1289 return AARCH64_BREAK_FAULT;
1292 if (offset < -SZ_1M || offset >= SZ_1M)
1293 return AARCH64_BREAK_FAULT;
1295 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, reg);
1297 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_ADR, insn, offset);
1301 * Decode the imm field of a branch, and return the byte offset as a
1302 * signed value (so it can be used when computing a new branch
1305 s32 aarch64_get_branch_offset(u32 insn)
1309 if (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn)) {
1310 imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_26, insn);
1311 return (imm << 6) >> 4;
1314 if (aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) ||
1315 aarch64_insn_is_bcond(insn)) {
1316 imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_19, insn);
1317 return (imm << 13) >> 11;
1320 if (aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn)) {
1321 imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_14, insn);
1322 return (imm << 18) >> 16;
1325 /* Unhandled instruction */
1330 * Encode the displacement of a branch in the imm field and return the
1331 * updated instruction.
1333 u32 aarch64_set_branch_offset(u32 insn, s32 offset)
1335 if (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn))
1336 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_26, insn,
1339 if (aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) ||
1340 aarch64_insn_is_bcond(insn))
1341 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
1344 if (aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn))
1345 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_14, insn,
1348 /* Unhandled instruction */
1352 s32 aarch64_insn_adrp_get_offset(u32 insn)
1354 BUG_ON(!aarch64_insn_is_adrp(insn));
1355 return aarch64_insn_decode_immediate(AARCH64_INSN_IMM_ADR, insn) << 12;
1358 u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset)
1360 BUG_ON(!aarch64_insn_is_adrp(insn));
1361 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_ADR, insn,
1366 * Extract the Op/CR data from a msr/mrs instruction.
1368 u32 aarch64_insn_extract_system_reg(u32 insn)
1370 return (insn & 0x1FFFE0) >> 5;
1373 bool aarch32_insn_is_wide(u32 insn)
1375 return insn >= 0xe800;
1379 * Macros/defines for extracting register numbers from instruction.
1381 u32 aarch32_insn_extract_reg_num(u32 insn, int offset)
1383 return (insn & (0xf << offset)) >> offset;
1386 #define OPC2_MASK 0x7
1387 #define OPC2_OFFSET 5
1388 u32 aarch32_insn_mcr_extract_opc2(u32 insn)
1390 return (insn & (OPC2_MASK << OPC2_OFFSET)) >> OPC2_OFFSET;
1393 #define CRM_MASK 0xf
1394 u32 aarch32_insn_mcr_extract_crm(u32 insn)
1396 return insn & CRM_MASK;
1399 static bool __kprobes __check_eq(unsigned long pstate)
1401 return (pstate & PSR_Z_BIT) != 0;
1404 static bool __kprobes __check_ne(unsigned long pstate)
1406 return (pstate & PSR_Z_BIT) == 0;
1409 static bool __kprobes __check_cs(unsigned long pstate)
1411 return (pstate & PSR_C_BIT) != 0;
1414 static bool __kprobes __check_cc(unsigned long pstate)
1416 return (pstate & PSR_C_BIT) == 0;
1419 static bool __kprobes __check_mi(unsigned long pstate)
1421 return (pstate & PSR_N_BIT) != 0;
1424 static bool __kprobes __check_pl(unsigned long pstate)
1426 return (pstate & PSR_N_BIT) == 0;
1429 static bool __kprobes __check_vs(unsigned long pstate)
1431 return (pstate & PSR_V_BIT) != 0;
1434 static bool __kprobes __check_vc(unsigned long pstate)
1436 return (pstate & PSR_V_BIT) == 0;
1439 static bool __kprobes __check_hi(unsigned long pstate)
1441 pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
1442 return (pstate & PSR_C_BIT) != 0;
1445 static bool __kprobes __check_ls(unsigned long pstate)
1447 pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
1448 return (pstate & PSR_C_BIT) == 0;
1451 static bool __kprobes __check_ge(unsigned long pstate)
1453 pstate ^= (pstate << 3); /* PSR_N_BIT ^= PSR_V_BIT */
1454 return (pstate & PSR_N_BIT) == 0;
1457 static bool __kprobes __check_lt(unsigned long pstate)
1459 pstate ^= (pstate << 3); /* PSR_N_BIT ^= PSR_V_BIT */
1460 return (pstate & PSR_N_BIT) != 0;
1463 static bool __kprobes __check_gt(unsigned long pstate)
1465 /*PSR_N_BIT ^= PSR_V_BIT */
1466 unsigned long temp = pstate ^ (pstate << 3);
1468 temp |= (pstate << 1); /*PSR_N_BIT |= PSR_Z_BIT */
1469 return (temp & PSR_N_BIT) == 0;
1472 static bool __kprobes __check_le(unsigned long pstate)
1474 /*PSR_N_BIT ^= PSR_V_BIT */
1475 unsigned long temp = pstate ^ (pstate << 3);
1477 temp |= (pstate << 1); /*PSR_N_BIT |= PSR_Z_BIT */
1478 return (temp & PSR_N_BIT) != 0;
1481 static bool __kprobes __check_al(unsigned long pstate)
1487 * Note that the ARMv8 ARM calls condition code 0b1111 "nv", but states that
1488 * it behaves identically to 0b1110 ("al").
1490 pstate_check_t * const aarch32_opcode_cond_checks[16] = {
1491 __check_eq, __check_ne, __check_cs, __check_cc,
1492 __check_mi, __check_pl, __check_vs, __check_vc,
1493 __check_hi, __check_ls, __check_ge, __check_lt,
1494 __check_gt, __check_le, __check_al, __check_al
1497 static bool range_of_ones(u64 val)
1499 /* Doesn't handle full ones or full zeroes */
1500 u64 sval = val >> __ffs64(val);
1502 /* One of Sean Eron Anderson's bithack tricks */
1503 return ((sval + 1) & (sval)) == 0;
1506 static u32 aarch64_encode_immediate(u64 imm,
1507 enum aarch64_insn_variant variant,
1510 unsigned int immr, imms, n, ones, ror, esz, tmp;
1513 /* Can't encode full zeroes or full ones */
1515 return AARCH64_BREAK_FAULT;
1518 case AARCH64_INSN_VARIANT_32BIT:
1519 if (upper_32_bits(imm))
1520 return AARCH64_BREAK_FAULT;
1523 case AARCH64_INSN_VARIANT_64BIT:
1524 insn |= AARCH64_INSN_SF_BIT;
1528 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1529 return AARCH64_BREAK_FAULT;
1533 * Inverse of Replicate(). Try to spot a repeating pattern
1534 * with a pow2 stride.
1536 for (tmp = esz / 2; tmp >= 2; tmp /= 2) {
1537 u64 emask = BIT(tmp) - 1;
1539 if ((imm & emask) != ((imm >> tmp) & emask))
1546 /* N is only set if we're encoding a 64bit value */
1549 /* Trim imm to the element size */
1552 /* That's how many ones we need to encode */
1553 ones = hweight64(imm);
1556 * imms is set to (ones - 1), prefixed with a string of ones
1557 * and a zero if they fit. Cap it to 6 bits.
1560 imms |= 0xf << ffs(esz);
1563 /* Compute the rotation */
1564 if (range_of_ones(imm)) {
1566 * Pattern: 0..01..10..0
1568 * Compute how many rotate we need to align it right
1573 * Pattern: 0..01..10..01..1
1575 * Fill the unused top bits with ones, and check if
1576 * the result is a valid immediate (all ones with a
1577 * contiguous ranges of zeroes).
1580 if (!range_of_ones(~imm))
1581 return AARCH64_BREAK_FAULT;
1584 * Compute the rotation to get a continuous set of
1585 * ones, with the first bit set at position 0
1591 * immr is the number of bits we need to rotate back to the
1592 * original set of ones. Note that this is relative to the
1595 immr = (esz - ror) % esz;
1597 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_N, insn, n);
1598 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_R, insn, immr);
1599 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_S, insn, imms);
1602 u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type,
1603 enum aarch64_insn_variant variant,
1604 enum aarch64_insn_register Rn,
1605 enum aarch64_insn_register Rd,
1611 case AARCH64_INSN_LOGIC_AND:
1612 insn = aarch64_insn_get_and_imm_value();
1614 case AARCH64_INSN_LOGIC_ORR:
1615 insn = aarch64_insn_get_orr_imm_value();
1617 case AARCH64_INSN_LOGIC_EOR:
1618 insn = aarch64_insn_get_eor_imm_value();
1620 case AARCH64_INSN_LOGIC_AND_SETFLAGS:
1621 insn = aarch64_insn_get_ands_imm_value();
1624 pr_err("%s: unknown logical encoding %d\n", __func__, type);
1625 return AARCH64_BREAK_FAULT;
1628 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, Rd);
1629 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, Rn);
1630 return aarch64_encode_immediate(imm, variant, insn);
1633 u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant,
1634 enum aarch64_insn_register Rm,
1635 enum aarch64_insn_register Rn,
1636 enum aarch64_insn_register Rd,
1641 insn = aarch64_insn_get_extr_value();
1644 case AARCH64_INSN_VARIANT_32BIT:
1646 return AARCH64_BREAK_FAULT;
1648 case AARCH64_INSN_VARIANT_64BIT:
1650 return AARCH64_BREAK_FAULT;
1651 insn |= AARCH64_INSN_SF_BIT;
1652 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_N, insn, 1);
1655 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1656 return AARCH64_BREAK_FAULT;
1659 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_S, insn, lsb);
1660 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, Rd);
1661 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, Rn);
1662 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, Rm);