1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Huawei Ltd.
4 * Author: Jiang Liu <liuj97@gmail.com>
6 * Copyright (C) 2014-2016 Zi Shen Lim <zlim.lnx@gmail.com>
8 #include <linux/bitops.h>
10 #include <linux/compiler.h>
11 #include <linux/kernel.h>
13 #include <linux/smp.h>
14 #include <linux/spinlock.h>
15 #include <linux/stop_machine.h>
16 #include <linux/types.h>
17 #include <linux/uaccess.h>
19 #include <asm/cacheflush.h>
20 #include <asm/debug-monitors.h>
21 #include <asm/fixmap.h>
23 #include <asm/kprobes.h>
24 #include <asm/sections.h>
26 #define AARCH64_INSN_SF_BIT BIT(31)
27 #define AARCH64_INSN_N_BIT BIT(22)
28 #define AARCH64_INSN_LSL_12 BIT(22)
30 static const int aarch64_insn_encoding_class[] = {
31 AARCH64_INSN_CLS_UNKNOWN,
32 AARCH64_INSN_CLS_UNKNOWN,
33 AARCH64_INSN_CLS_UNKNOWN,
34 AARCH64_INSN_CLS_UNKNOWN,
35 AARCH64_INSN_CLS_LDST,
36 AARCH64_INSN_CLS_DP_REG,
37 AARCH64_INSN_CLS_LDST,
38 AARCH64_INSN_CLS_DP_FPSIMD,
39 AARCH64_INSN_CLS_DP_IMM,
40 AARCH64_INSN_CLS_DP_IMM,
41 AARCH64_INSN_CLS_BR_SYS,
42 AARCH64_INSN_CLS_BR_SYS,
43 AARCH64_INSN_CLS_LDST,
44 AARCH64_INSN_CLS_DP_REG,
45 AARCH64_INSN_CLS_LDST,
46 AARCH64_INSN_CLS_DP_FPSIMD,
49 enum aarch64_insn_encoding_class __kprobes aarch64_get_insn_class(u32 insn)
51 return aarch64_insn_encoding_class[(insn >> 25) & 0xf];
54 /* NOP is an alias of HINT */
55 bool __kprobes aarch64_insn_is_nop(u32 insn)
57 if (!aarch64_insn_is_hint(insn))
60 switch (insn & 0xFE0) {
61 case AARCH64_INSN_HINT_YIELD:
62 case AARCH64_INSN_HINT_WFE:
63 case AARCH64_INSN_HINT_WFI:
64 case AARCH64_INSN_HINT_SEV:
65 case AARCH64_INSN_HINT_SEVL:
72 bool aarch64_insn_is_branch_imm(u32 insn)
74 return (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn) ||
75 aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn) ||
76 aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) ||
77 aarch64_insn_is_bcond(insn));
80 static DEFINE_RAW_SPINLOCK(patch_lock);
82 static bool is_exit_text(unsigned long addr)
84 /* discarded with init text/data */
85 return system_state < SYSTEM_RUNNING &&
86 addr >= (unsigned long)__exittext_begin &&
87 addr < (unsigned long)__exittext_end;
90 static bool is_image_text(unsigned long addr)
92 return core_kernel_text(addr) || is_exit_text(addr);
95 static void __kprobes *patch_map(void *addr, int fixmap)
97 unsigned long uintaddr = (uintptr_t) addr;
98 bool image = is_image_text(uintaddr);
102 page = phys_to_page(__pa_symbol(addr));
103 else if (IS_ENABLED(CONFIG_STRICT_MODULE_RWX))
104 page = vmalloc_to_page(addr);
109 return (void *)set_fixmap_offset(fixmap, page_to_phys(page) +
110 (uintaddr & ~PAGE_MASK));
113 static void __kprobes patch_unmap(int fixmap)
115 clear_fixmap(fixmap);
118 * In ARMv8-A, A64 instructions have a fixed length of 32 bits and are always
121 int __kprobes aarch64_insn_read(void *addr, u32 *insnp)
126 ret = probe_kernel_read(&val, addr, AARCH64_INSN_SIZE);
128 *insnp = le32_to_cpu(val);
133 static int __kprobes __aarch64_insn_write(void *addr, __le32 insn)
136 unsigned long flags = 0;
139 raw_spin_lock_irqsave(&patch_lock, flags);
140 waddr = patch_map(addr, FIX_TEXT_POKE0);
142 ret = probe_kernel_write(waddr, &insn, AARCH64_INSN_SIZE);
144 patch_unmap(FIX_TEXT_POKE0);
145 raw_spin_unlock_irqrestore(&patch_lock, flags);
150 int __kprobes aarch64_insn_write(void *addr, u32 insn)
152 return __aarch64_insn_write(addr, cpu_to_le32(insn));
155 bool __kprobes aarch64_insn_uses_literal(u32 insn)
157 /* ldr/ldrsw (literal), prfm */
159 return aarch64_insn_is_ldr_lit(insn) ||
160 aarch64_insn_is_ldrsw_lit(insn) ||
161 aarch64_insn_is_adr_adrp(insn) ||
162 aarch64_insn_is_prfm_lit(insn);
165 bool __kprobes aarch64_insn_is_branch(u32 insn)
167 /* b, bl, cb*, tb*, b.cond, br, blr */
169 return aarch64_insn_is_b(insn) ||
170 aarch64_insn_is_bl(insn) ||
171 aarch64_insn_is_cbz(insn) ||
172 aarch64_insn_is_cbnz(insn) ||
173 aarch64_insn_is_tbz(insn) ||
174 aarch64_insn_is_tbnz(insn) ||
175 aarch64_insn_is_ret(insn) ||
176 aarch64_insn_is_br(insn) ||
177 aarch64_insn_is_blr(insn) ||
178 aarch64_insn_is_bcond(insn);
181 int __kprobes aarch64_insn_patch_text_nosync(void *addr, u32 insn)
186 /* A64 instructions must be word aligned */
187 if ((uintptr_t)tp & 0x3)
190 ret = aarch64_insn_write(tp, insn);
192 __flush_icache_range((uintptr_t)tp,
193 (uintptr_t)tp + AARCH64_INSN_SIZE);
198 struct aarch64_insn_patch {
205 static int __kprobes aarch64_insn_patch_text_cb(void *arg)
208 struct aarch64_insn_patch *pp = arg;
210 /* The first CPU becomes master */
211 if (atomic_inc_return(&pp->cpu_count) == 1) {
212 for (i = 0; ret == 0 && i < pp->insn_cnt; i++)
213 ret = aarch64_insn_patch_text_nosync(pp->text_addrs[i],
215 /* Notify other processors with an additional increment. */
216 atomic_inc(&pp->cpu_count);
218 while (atomic_read(&pp->cpu_count) <= num_online_cpus())
226 int __kprobes aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt)
228 struct aarch64_insn_patch patch = {
232 .cpu_count = ATOMIC_INIT(0),
238 return stop_machine_cpuslocked(aarch64_insn_patch_text_cb, &patch,
242 static int __kprobes aarch64_get_imm_shift_mask(enum aarch64_insn_imm_type type,
243 u32 *maskp, int *shiftp)
249 case AARCH64_INSN_IMM_26:
253 case AARCH64_INSN_IMM_19:
257 case AARCH64_INSN_IMM_16:
261 case AARCH64_INSN_IMM_14:
265 case AARCH64_INSN_IMM_12:
269 case AARCH64_INSN_IMM_9:
273 case AARCH64_INSN_IMM_7:
277 case AARCH64_INSN_IMM_6:
278 case AARCH64_INSN_IMM_S:
282 case AARCH64_INSN_IMM_R:
286 case AARCH64_INSN_IMM_N:
300 #define ADR_IMM_HILOSPLIT 2
301 #define ADR_IMM_SIZE SZ_2M
302 #define ADR_IMM_LOMASK ((1 << ADR_IMM_HILOSPLIT) - 1)
303 #define ADR_IMM_HIMASK ((ADR_IMM_SIZE >> ADR_IMM_HILOSPLIT) - 1)
304 #define ADR_IMM_LOSHIFT 29
305 #define ADR_IMM_HISHIFT 5
307 u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn)
309 u32 immlo, immhi, mask;
313 case AARCH64_INSN_IMM_ADR:
315 immlo = (insn >> ADR_IMM_LOSHIFT) & ADR_IMM_LOMASK;
316 immhi = (insn >> ADR_IMM_HISHIFT) & ADR_IMM_HIMASK;
317 insn = (immhi << ADR_IMM_HILOSPLIT) | immlo;
318 mask = ADR_IMM_SIZE - 1;
321 if (aarch64_get_imm_shift_mask(type, &mask, &shift) < 0) {
322 pr_err("aarch64_insn_decode_immediate: unknown immediate encoding %d\n",
328 return (insn >> shift) & mask;
331 u32 __kprobes aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
334 u32 immlo, immhi, mask;
337 if (insn == AARCH64_BREAK_FAULT)
338 return AARCH64_BREAK_FAULT;
341 case AARCH64_INSN_IMM_ADR:
343 immlo = (imm & ADR_IMM_LOMASK) << ADR_IMM_LOSHIFT;
344 imm >>= ADR_IMM_HILOSPLIT;
345 immhi = (imm & ADR_IMM_HIMASK) << ADR_IMM_HISHIFT;
347 mask = ((ADR_IMM_LOMASK << ADR_IMM_LOSHIFT) |
348 (ADR_IMM_HIMASK << ADR_IMM_HISHIFT));
351 if (aarch64_get_imm_shift_mask(type, &mask, &shift) < 0) {
352 pr_err("aarch64_insn_encode_immediate: unknown immediate encoding %d\n",
354 return AARCH64_BREAK_FAULT;
358 /* Update the immediate field. */
359 insn &= ~(mask << shift);
360 insn |= (imm & mask) << shift;
365 u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type,
371 case AARCH64_INSN_REGTYPE_RT:
372 case AARCH64_INSN_REGTYPE_RD:
375 case AARCH64_INSN_REGTYPE_RN:
378 case AARCH64_INSN_REGTYPE_RT2:
379 case AARCH64_INSN_REGTYPE_RA:
382 case AARCH64_INSN_REGTYPE_RM:
386 pr_err("%s: unknown register type encoding %d\n", __func__,
391 return (insn >> shift) & GENMASK(4, 0);
394 static u32 aarch64_insn_encode_register(enum aarch64_insn_register_type type,
396 enum aarch64_insn_register reg)
400 if (insn == AARCH64_BREAK_FAULT)
401 return AARCH64_BREAK_FAULT;
403 if (reg < AARCH64_INSN_REG_0 || reg > AARCH64_INSN_REG_SP) {
404 pr_err("%s: unknown register encoding %d\n", __func__, reg);
405 return AARCH64_BREAK_FAULT;
409 case AARCH64_INSN_REGTYPE_RT:
410 case AARCH64_INSN_REGTYPE_RD:
413 case AARCH64_INSN_REGTYPE_RN:
416 case AARCH64_INSN_REGTYPE_RT2:
417 case AARCH64_INSN_REGTYPE_RA:
420 case AARCH64_INSN_REGTYPE_RM:
421 case AARCH64_INSN_REGTYPE_RS:
425 pr_err("%s: unknown register type encoding %d\n", __func__,
427 return AARCH64_BREAK_FAULT;
430 insn &= ~(GENMASK(4, 0) << shift);
431 insn |= reg << shift;
436 static u32 aarch64_insn_encode_ldst_size(enum aarch64_insn_size_type type,
442 case AARCH64_INSN_SIZE_8:
445 case AARCH64_INSN_SIZE_16:
448 case AARCH64_INSN_SIZE_32:
451 case AARCH64_INSN_SIZE_64:
455 pr_err("%s: unknown size encoding %d\n", __func__, type);
456 return AARCH64_BREAK_FAULT;
459 insn &= ~GENMASK(31, 30);
465 static inline long branch_imm_common(unsigned long pc, unsigned long addr,
470 if ((pc & 0x3) || (addr & 0x3)) {
471 pr_err("%s: A64 instructions must be word aligned\n", __func__);
475 offset = ((long)addr - (long)pc);
477 if (offset < -range || offset >= range) {
478 pr_err("%s: offset out of range\n", __func__);
485 u32 __kprobes aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
486 enum aarch64_insn_branch_type type)
492 * B/BL support [-128M, 128M) offset
493 * ARM64 virtual address arrangement guarantees all kernel and module
494 * texts are within +/-128M.
496 offset = branch_imm_common(pc, addr, SZ_128M);
497 if (offset >= SZ_128M)
498 return AARCH64_BREAK_FAULT;
501 case AARCH64_INSN_BRANCH_LINK:
502 insn = aarch64_insn_get_bl_value();
504 case AARCH64_INSN_BRANCH_NOLINK:
505 insn = aarch64_insn_get_b_value();
508 pr_err("%s: unknown branch encoding %d\n", __func__, type);
509 return AARCH64_BREAK_FAULT;
512 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_26, insn,
516 u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
517 enum aarch64_insn_register reg,
518 enum aarch64_insn_variant variant,
519 enum aarch64_insn_branch_type type)
524 offset = branch_imm_common(pc, addr, SZ_1M);
526 return AARCH64_BREAK_FAULT;
529 case AARCH64_INSN_BRANCH_COMP_ZERO:
530 insn = aarch64_insn_get_cbz_value();
532 case AARCH64_INSN_BRANCH_COMP_NONZERO:
533 insn = aarch64_insn_get_cbnz_value();
536 pr_err("%s: unknown branch encoding %d\n", __func__, type);
537 return AARCH64_BREAK_FAULT;
541 case AARCH64_INSN_VARIANT_32BIT:
543 case AARCH64_INSN_VARIANT_64BIT:
544 insn |= AARCH64_INSN_SF_BIT;
547 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
548 return AARCH64_BREAK_FAULT;
551 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
553 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
557 u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
558 enum aarch64_insn_condition cond)
563 offset = branch_imm_common(pc, addr, SZ_1M);
565 insn = aarch64_insn_get_bcond_value();
567 if (cond < AARCH64_INSN_COND_EQ || cond > AARCH64_INSN_COND_AL) {
568 pr_err("%s: unknown condition encoding %d\n", __func__, cond);
569 return AARCH64_BREAK_FAULT;
573 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
577 u32 __kprobes aarch64_insn_gen_hint(enum aarch64_insn_hint_op op)
579 return aarch64_insn_get_hint_value() | op;
582 u32 __kprobes aarch64_insn_gen_nop(void)
584 return aarch64_insn_gen_hint(AARCH64_INSN_HINT_NOP);
587 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
588 enum aarch64_insn_branch_type type)
593 case AARCH64_INSN_BRANCH_NOLINK:
594 insn = aarch64_insn_get_br_value();
596 case AARCH64_INSN_BRANCH_LINK:
597 insn = aarch64_insn_get_blr_value();
599 case AARCH64_INSN_BRANCH_RETURN:
600 insn = aarch64_insn_get_ret_value();
603 pr_err("%s: unknown branch encoding %d\n", __func__, type);
604 return AARCH64_BREAK_FAULT;
607 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, reg);
610 u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
611 enum aarch64_insn_register base,
612 enum aarch64_insn_register offset,
613 enum aarch64_insn_size_type size,
614 enum aarch64_insn_ldst_type type)
619 case AARCH64_INSN_LDST_LOAD_REG_OFFSET:
620 insn = aarch64_insn_get_ldr_reg_value();
622 case AARCH64_INSN_LDST_STORE_REG_OFFSET:
623 insn = aarch64_insn_get_str_reg_value();
626 pr_err("%s: unknown load/store encoding %d\n", __func__, type);
627 return AARCH64_BREAK_FAULT;
630 insn = aarch64_insn_encode_ldst_size(size, insn);
632 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
634 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
637 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
641 u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
642 enum aarch64_insn_register reg2,
643 enum aarch64_insn_register base,
645 enum aarch64_insn_variant variant,
646 enum aarch64_insn_ldst_type type)
652 case AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX:
653 insn = aarch64_insn_get_ldp_pre_value();
655 case AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX:
656 insn = aarch64_insn_get_stp_pre_value();
658 case AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX:
659 insn = aarch64_insn_get_ldp_post_value();
661 case AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX:
662 insn = aarch64_insn_get_stp_post_value();
665 pr_err("%s: unknown load/store encoding %d\n", __func__, type);
666 return AARCH64_BREAK_FAULT;
670 case AARCH64_INSN_VARIANT_32BIT:
671 if ((offset & 0x3) || (offset < -256) || (offset > 252)) {
672 pr_err("%s: offset must be multiples of 4 in the range of [-256, 252] %d\n",
674 return AARCH64_BREAK_FAULT;
678 case AARCH64_INSN_VARIANT_64BIT:
679 if ((offset & 0x7) || (offset < -512) || (offset > 504)) {
680 pr_err("%s: offset must be multiples of 8 in the range of [-512, 504] %d\n",
682 return AARCH64_BREAK_FAULT;
685 insn |= AARCH64_INSN_SF_BIT;
688 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
689 return AARCH64_BREAK_FAULT;
692 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn,
695 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT2, insn,
698 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
701 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_7, insn,
705 u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,
706 enum aarch64_insn_register base,
707 enum aarch64_insn_register state,
708 enum aarch64_insn_size_type size,
709 enum aarch64_insn_ldst_type type)
714 case AARCH64_INSN_LDST_LOAD_EX:
715 insn = aarch64_insn_get_load_ex_value();
717 case AARCH64_INSN_LDST_STORE_EX:
718 insn = aarch64_insn_get_store_ex_value();
721 pr_err("%s: unknown load/store exclusive encoding %d\n", __func__, type);
722 return AARCH64_BREAK_FAULT;
725 insn = aarch64_insn_encode_ldst_size(size, insn);
727 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn,
730 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
733 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT2, insn,
734 AARCH64_INSN_REG_ZR);
736 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RS, insn,
740 u32 aarch64_insn_gen_ldadd(enum aarch64_insn_register result,
741 enum aarch64_insn_register address,
742 enum aarch64_insn_register value,
743 enum aarch64_insn_size_type size)
745 u32 insn = aarch64_insn_get_ldadd_value();
748 case AARCH64_INSN_SIZE_32:
749 case AARCH64_INSN_SIZE_64:
752 pr_err("%s: unimplemented size encoding %d\n", __func__, size);
753 return AARCH64_BREAK_FAULT;
756 insn = aarch64_insn_encode_ldst_size(size, insn);
758 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn,
761 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
764 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RS, insn,
768 u32 aarch64_insn_gen_stadd(enum aarch64_insn_register address,
769 enum aarch64_insn_register value,
770 enum aarch64_insn_size_type size)
773 * STADD is simply encoded as an alias for LDADD with XZR as
774 * the destination register.
776 return aarch64_insn_gen_ldadd(AARCH64_INSN_REG_ZR, address,
780 static u32 aarch64_insn_encode_prfm_imm(enum aarch64_insn_prfm_type type,
781 enum aarch64_insn_prfm_target target,
782 enum aarch64_insn_prfm_policy policy,
785 u32 imm_type = 0, imm_target = 0, imm_policy = 0;
788 case AARCH64_INSN_PRFM_TYPE_PLD:
790 case AARCH64_INSN_PRFM_TYPE_PLI:
793 case AARCH64_INSN_PRFM_TYPE_PST:
797 pr_err("%s: unknown prfm type encoding %d\n", __func__, type);
798 return AARCH64_BREAK_FAULT;
802 case AARCH64_INSN_PRFM_TARGET_L1:
804 case AARCH64_INSN_PRFM_TARGET_L2:
807 case AARCH64_INSN_PRFM_TARGET_L3:
811 pr_err("%s: unknown prfm target encoding %d\n", __func__, target);
812 return AARCH64_BREAK_FAULT;
816 case AARCH64_INSN_PRFM_POLICY_KEEP:
818 case AARCH64_INSN_PRFM_POLICY_STRM:
822 pr_err("%s: unknown prfm policy encoding %d\n", __func__, policy);
823 return AARCH64_BREAK_FAULT;
826 /* In this case, imm5 is encoded into Rt field. */
827 insn &= ~GENMASK(4, 0);
828 insn |= imm_policy | (imm_target << 1) | (imm_type << 3);
833 u32 aarch64_insn_gen_prefetch(enum aarch64_insn_register base,
834 enum aarch64_insn_prfm_type type,
835 enum aarch64_insn_prfm_target target,
836 enum aarch64_insn_prfm_policy policy)
838 u32 insn = aarch64_insn_get_prfm_value();
840 insn = aarch64_insn_encode_ldst_size(AARCH64_INSN_SIZE_64, insn);
842 insn = aarch64_insn_encode_prfm_imm(type, target, policy, insn);
844 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
847 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_12, insn, 0);
850 u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
851 enum aarch64_insn_register src,
852 int imm, enum aarch64_insn_variant variant,
853 enum aarch64_insn_adsb_type type)
858 case AARCH64_INSN_ADSB_ADD:
859 insn = aarch64_insn_get_add_imm_value();
861 case AARCH64_INSN_ADSB_SUB:
862 insn = aarch64_insn_get_sub_imm_value();
864 case AARCH64_INSN_ADSB_ADD_SETFLAGS:
865 insn = aarch64_insn_get_adds_imm_value();
867 case AARCH64_INSN_ADSB_SUB_SETFLAGS:
868 insn = aarch64_insn_get_subs_imm_value();
871 pr_err("%s: unknown add/sub encoding %d\n", __func__, type);
872 return AARCH64_BREAK_FAULT;
876 case AARCH64_INSN_VARIANT_32BIT:
878 case AARCH64_INSN_VARIANT_64BIT:
879 insn |= AARCH64_INSN_SF_BIT;
882 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
883 return AARCH64_BREAK_FAULT;
886 /* We can't encode more than a 24bit value (12bit + 12bit shift) */
887 if (imm & ~(BIT(24) - 1))
890 /* If we have something in the top 12 bits... */
891 if (imm & ~(SZ_4K - 1)) {
892 /* ... and in the low 12 bits -> error */
893 if (imm & (SZ_4K - 1))
897 insn |= AARCH64_INSN_LSL_12;
900 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
902 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
904 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_12, insn, imm);
907 pr_err("%s: invalid immediate encoding %d\n", __func__, imm);
908 return AARCH64_BREAK_FAULT;
911 u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
912 enum aarch64_insn_register src,
914 enum aarch64_insn_variant variant,
915 enum aarch64_insn_bitfield_type type)
921 case AARCH64_INSN_BITFIELD_MOVE:
922 insn = aarch64_insn_get_bfm_value();
924 case AARCH64_INSN_BITFIELD_MOVE_UNSIGNED:
925 insn = aarch64_insn_get_ubfm_value();
927 case AARCH64_INSN_BITFIELD_MOVE_SIGNED:
928 insn = aarch64_insn_get_sbfm_value();
931 pr_err("%s: unknown bitfield encoding %d\n", __func__, type);
932 return AARCH64_BREAK_FAULT;
936 case AARCH64_INSN_VARIANT_32BIT:
937 mask = GENMASK(4, 0);
939 case AARCH64_INSN_VARIANT_64BIT:
940 insn |= AARCH64_INSN_SF_BIT | AARCH64_INSN_N_BIT;
941 mask = GENMASK(5, 0);
944 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
945 return AARCH64_BREAK_FAULT;
949 pr_err("%s: invalid immr encoding %d\n", __func__, immr);
950 return AARCH64_BREAK_FAULT;
953 pr_err("%s: invalid imms encoding %d\n", __func__, imms);
954 return AARCH64_BREAK_FAULT;
957 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
959 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
961 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_R, insn, immr);
963 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_S, insn, imms);
966 u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
968 enum aarch64_insn_variant variant,
969 enum aarch64_insn_movewide_type type)
974 case AARCH64_INSN_MOVEWIDE_ZERO:
975 insn = aarch64_insn_get_movz_value();
977 case AARCH64_INSN_MOVEWIDE_KEEP:
978 insn = aarch64_insn_get_movk_value();
980 case AARCH64_INSN_MOVEWIDE_INVERSE:
981 insn = aarch64_insn_get_movn_value();
984 pr_err("%s: unknown movewide encoding %d\n", __func__, type);
985 return AARCH64_BREAK_FAULT;
988 if (imm & ~(SZ_64K - 1)) {
989 pr_err("%s: invalid immediate encoding %d\n", __func__, imm);
990 return AARCH64_BREAK_FAULT;
994 case AARCH64_INSN_VARIANT_32BIT:
995 if (shift != 0 && shift != 16) {
996 pr_err("%s: invalid shift encoding %d\n", __func__,
998 return AARCH64_BREAK_FAULT;
1001 case AARCH64_INSN_VARIANT_64BIT:
1002 insn |= AARCH64_INSN_SF_BIT;
1003 if (shift != 0 && shift != 16 && shift != 32 && shift != 48) {
1004 pr_err("%s: invalid shift encoding %d\n", __func__,
1006 return AARCH64_BREAK_FAULT;
1010 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1011 return AARCH64_BREAK_FAULT;
1014 insn |= (shift >> 4) << 21;
1016 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1018 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm);
1021 u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
1022 enum aarch64_insn_register src,
1023 enum aarch64_insn_register reg,
1025 enum aarch64_insn_variant variant,
1026 enum aarch64_insn_adsb_type type)
1031 case AARCH64_INSN_ADSB_ADD:
1032 insn = aarch64_insn_get_add_value();
1034 case AARCH64_INSN_ADSB_SUB:
1035 insn = aarch64_insn_get_sub_value();
1037 case AARCH64_INSN_ADSB_ADD_SETFLAGS:
1038 insn = aarch64_insn_get_adds_value();
1040 case AARCH64_INSN_ADSB_SUB_SETFLAGS:
1041 insn = aarch64_insn_get_subs_value();
1044 pr_err("%s: unknown add/sub encoding %d\n", __func__, type);
1045 return AARCH64_BREAK_FAULT;
1049 case AARCH64_INSN_VARIANT_32BIT:
1050 if (shift & ~(SZ_32 - 1)) {
1051 pr_err("%s: invalid shift encoding %d\n", __func__,
1053 return AARCH64_BREAK_FAULT;
1056 case AARCH64_INSN_VARIANT_64BIT:
1057 insn |= AARCH64_INSN_SF_BIT;
1058 if (shift & ~(SZ_64 - 1)) {
1059 pr_err("%s: invalid shift encoding %d\n", __func__,
1061 return AARCH64_BREAK_FAULT;
1065 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1066 return AARCH64_BREAK_FAULT;
1070 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1072 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
1074 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
1076 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);
1079 u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
1080 enum aarch64_insn_register src,
1081 enum aarch64_insn_variant variant,
1082 enum aarch64_insn_data1_type type)
1087 case AARCH64_INSN_DATA1_REVERSE_16:
1088 insn = aarch64_insn_get_rev16_value();
1090 case AARCH64_INSN_DATA1_REVERSE_32:
1091 insn = aarch64_insn_get_rev32_value();
1093 case AARCH64_INSN_DATA1_REVERSE_64:
1094 if (variant != AARCH64_INSN_VARIANT_64BIT) {
1095 pr_err("%s: invalid variant for reverse64 %d\n",
1097 return AARCH64_BREAK_FAULT;
1099 insn = aarch64_insn_get_rev64_value();
1102 pr_err("%s: unknown data1 encoding %d\n", __func__, type);
1103 return AARCH64_BREAK_FAULT;
1107 case AARCH64_INSN_VARIANT_32BIT:
1109 case AARCH64_INSN_VARIANT_64BIT:
1110 insn |= AARCH64_INSN_SF_BIT;
1113 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1114 return AARCH64_BREAK_FAULT;
1117 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1119 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
1122 u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
1123 enum aarch64_insn_register src,
1124 enum aarch64_insn_register reg,
1125 enum aarch64_insn_variant variant,
1126 enum aarch64_insn_data2_type type)
1131 case AARCH64_INSN_DATA2_UDIV:
1132 insn = aarch64_insn_get_udiv_value();
1134 case AARCH64_INSN_DATA2_SDIV:
1135 insn = aarch64_insn_get_sdiv_value();
1137 case AARCH64_INSN_DATA2_LSLV:
1138 insn = aarch64_insn_get_lslv_value();
1140 case AARCH64_INSN_DATA2_LSRV:
1141 insn = aarch64_insn_get_lsrv_value();
1143 case AARCH64_INSN_DATA2_ASRV:
1144 insn = aarch64_insn_get_asrv_value();
1146 case AARCH64_INSN_DATA2_RORV:
1147 insn = aarch64_insn_get_rorv_value();
1150 pr_err("%s: unknown data2 encoding %d\n", __func__, type);
1151 return AARCH64_BREAK_FAULT;
1155 case AARCH64_INSN_VARIANT_32BIT:
1157 case AARCH64_INSN_VARIANT_64BIT:
1158 insn |= AARCH64_INSN_SF_BIT;
1161 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1162 return AARCH64_BREAK_FAULT;
1165 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1167 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
1169 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
1172 u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
1173 enum aarch64_insn_register src,
1174 enum aarch64_insn_register reg1,
1175 enum aarch64_insn_register reg2,
1176 enum aarch64_insn_variant variant,
1177 enum aarch64_insn_data3_type type)
1182 case AARCH64_INSN_DATA3_MADD:
1183 insn = aarch64_insn_get_madd_value();
1185 case AARCH64_INSN_DATA3_MSUB:
1186 insn = aarch64_insn_get_msub_value();
1189 pr_err("%s: unknown data3 encoding %d\n", __func__, type);
1190 return AARCH64_BREAK_FAULT;
1194 case AARCH64_INSN_VARIANT_32BIT:
1196 case AARCH64_INSN_VARIANT_64BIT:
1197 insn |= AARCH64_INSN_SF_BIT;
1200 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1201 return AARCH64_BREAK_FAULT;
1204 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1206 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RA, insn, src);
1208 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
1211 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
1215 u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
1216 enum aarch64_insn_register src,
1217 enum aarch64_insn_register reg,
1219 enum aarch64_insn_variant variant,
1220 enum aarch64_insn_logic_type type)
1225 case AARCH64_INSN_LOGIC_AND:
1226 insn = aarch64_insn_get_and_value();
1228 case AARCH64_INSN_LOGIC_BIC:
1229 insn = aarch64_insn_get_bic_value();
1231 case AARCH64_INSN_LOGIC_ORR:
1232 insn = aarch64_insn_get_orr_value();
1234 case AARCH64_INSN_LOGIC_ORN:
1235 insn = aarch64_insn_get_orn_value();
1237 case AARCH64_INSN_LOGIC_EOR:
1238 insn = aarch64_insn_get_eor_value();
1240 case AARCH64_INSN_LOGIC_EON:
1241 insn = aarch64_insn_get_eon_value();
1243 case AARCH64_INSN_LOGIC_AND_SETFLAGS:
1244 insn = aarch64_insn_get_ands_value();
1246 case AARCH64_INSN_LOGIC_BIC_SETFLAGS:
1247 insn = aarch64_insn_get_bics_value();
1250 pr_err("%s: unknown logical encoding %d\n", __func__, type);
1251 return AARCH64_BREAK_FAULT;
1255 case AARCH64_INSN_VARIANT_32BIT:
1256 if (shift & ~(SZ_32 - 1)) {
1257 pr_err("%s: invalid shift encoding %d\n", __func__,
1259 return AARCH64_BREAK_FAULT;
1262 case AARCH64_INSN_VARIANT_64BIT:
1263 insn |= AARCH64_INSN_SF_BIT;
1264 if (shift & ~(SZ_64 - 1)) {
1265 pr_err("%s: invalid shift encoding %d\n", __func__,
1267 return AARCH64_BREAK_FAULT;
1271 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1272 return AARCH64_BREAK_FAULT;
1276 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1278 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
1280 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
1282 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);
1286 * MOV (register) is architecturally an alias of ORR (shifted register) where
1287 * MOV <*d>, <*m> is equivalent to ORR <*d>, <*ZR>, <*m>
1289 u32 aarch64_insn_gen_move_reg(enum aarch64_insn_register dst,
1290 enum aarch64_insn_register src,
1291 enum aarch64_insn_variant variant)
1293 return aarch64_insn_gen_logical_shifted_reg(dst, AARCH64_INSN_REG_ZR,
1295 AARCH64_INSN_LOGIC_ORR);
1298 u32 aarch64_insn_gen_adr(unsigned long pc, unsigned long addr,
1299 enum aarch64_insn_register reg,
1300 enum aarch64_insn_adr_type type)
1306 case AARCH64_INSN_ADR_TYPE_ADR:
1307 insn = aarch64_insn_get_adr_value();
1310 case AARCH64_INSN_ADR_TYPE_ADRP:
1311 insn = aarch64_insn_get_adrp_value();
1312 offset = (addr - ALIGN_DOWN(pc, SZ_4K)) >> 12;
1315 pr_err("%s: unknown adr encoding %d\n", __func__, type);
1316 return AARCH64_BREAK_FAULT;
1319 if (offset < -SZ_1M || offset >= SZ_1M)
1320 return AARCH64_BREAK_FAULT;
1322 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, reg);
1324 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_ADR, insn, offset);
1328 * Decode the imm field of a branch, and return the byte offset as a
1329 * signed value (so it can be used when computing a new branch
1332 s32 aarch64_get_branch_offset(u32 insn)
1336 if (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn)) {
1337 imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_26, insn);
1338 return (imm << 6) >> 4;
1341 if (aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) ||
1342 aarch64_insn_is_bcond(insn)) {
1343 imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_19, insn);
1344 return (imm << 13) >> 11;
1347 if (aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn)) {
1348 imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_14, insn);
1349 return (imm << 18) >> 16;
1352 /* Unhandled instruction */
1357 * Encode the displacement of a branch in the imm field and return the
1358 * updated instruction.
1360 u32 aarch64_set_branch_offset(u32 insn, s32 offset)
1362 if (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn))
1363 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_26, insn,
1366 if (aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) ||
1367 aarch64_insn_is_bcond(insn))
1368 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
1371 if (aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn))
1372 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_14, insn,
1375 /* Unhandled instruction */
1379 s32 aarch64_insn_adrp_get_offset(u32 insn)
1381 BUG_ON(!aarch64_insn_is_adrp(insn));
1382 return aarch64_insn_decode_immediate(AARCH64_INSN_IMM_ADR, insn) << 12;
1385 u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset)
1387 BUG_ON(!aarch64_insn_is_adrp(insn));
1388 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_ADR, insn,
1393 * Extract the Op/CR data from a msr/mrs instruction.
1395 u32 aarch64_insn_extract_system_reg(u32 insn)
1397 return (insn & 0x1FFFE0) >> 5;
1400 bool aarch32_insn_is_wide(u32 insn)
1402 return insn >= 0xe800;
1406 * Macros/defines for extracting register numbers from instruction.
1408 u32 aarch32_insn_extract_reg_num(u32 insn, int offset)
1410 return (insn & (0xf << offset)) >> offset;
1413 #define OPC2_MASK 0x7
1414 #define OPC2_OFFSET 5
1415 u32 aarch32_insn_mcr_extract_opc2(u32 insn)
1417 return (insn & (OPC2_MASK << OPC2_OFFSET)) >> OPC2_OFFSET;
1420 #define CRM_MASK 0xf
1421 u32 aarch32_insn_mcr_extract_crm(u32 insn)
1423 return insn & CRM_MASK;
1426 static bool __kprobes __check_eq(unsigned long pstate)
1428 return (pstate & PSR_Z_BIT) != 0;
1431 static bool __kprobes __check_ne(unsigned long pstate)
1433 return (pstate & PSR_Z_BIT) == 0;
1436 static bool __kprobes __check_cs(unsigned long pstate)
1438 return (pstate & PSR_C_BIT) != 0;
1441 static bool __kprobes __check_cc(unsigned long pstate)
1443 return (pstate & PSR_C_BIT) == 0;
1446 static bool __kprobes __check_mi(unsigned long pstate)
1448 return (pstate & PSR_N_BIT) != 0;
1451 static bool __kprobes __check_pl(unsigned long pstate)
1453 return (pstate & PSR_N_BIT) == 0;
1456 static bool __kprobes __check_vs(unsigned long pstate)
1458 return (pstate & PSR_V_BIT) != 0;
1461 static bool __kprobes __check_vc(unsigned long pstate)
1463 return (pstate & PSR_V_BIT) == 0;
1466 static bool __kprobes __check_hi(unsigned long pstate)
1468 pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
1469 return (pstate & PSR_C_BIT) != 0;
1472 static bool __kprobes __check_ls(unsigned long pstate)
1474 pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
1475 return (pstate & PSR_C_BIT) == 0;
1478 static bool __kprobes __check_ge(unsigned long pstate)
1480 pstate ^= (pstate << 3); /* PSR_N_BIT ^= PSR_V_BIT */
1481 return (pstate & PSR_N_BIT) == 0;
1484 static bool __kprobes __check_lt(unsigned long pstate)
1486 pstate ^= (pstate << 3); /* PSR_N_BIT ^= PSR_V_BIT */
1487 return (pstate & PSR_N_BIT) != 0;
1490 static bool __kprobes __check_gt(unsigned long pstate)
1492 /*PSR_N_BIT ^= PSR_V_BIT */
1493 unsigned long temp = pstate ^ (pstate << 3);
1495 temp |= (pstate << 1); /*PSR_N_BIT |= PSR_Z_BIT */
1496 return (temp & PSR_N_BIT) == 0;
1499 static bool __kprobes __check_le(unsigned long pstate)
1501 /*PSR_N_BIT ^= PSR_V_BIT */
1502 unsigned long temp = pstate ^ (pstate << 3);
1504 temp |= (pstate << 1); /*PSR_N_BIT |= PSR_Z_BIT */
1505 return (temp & PSR_N_BIT) != 0;
1508 static bool __kprobes __check_al(unsigned long pstate)
1514 * Note that the ARMv8 ARM calls condition code 0b1111 "nv", but states that
1515 * it behaves identically to 0b1110 ("al").
1517 pstate_check_t * const aarch32_opcode_cond_checks[16] = {
1518 __check_eq, __check_ne, __check_cs, __check_cc,
1519 __check_mi, __check_pl, __check_vs, __check_vc,
1520 __check_hi, __check_ls, __check_ge, __check_lt,
1521 __check_gt, __check_le, __check_al, __check_al
1524 static bool range_of_ones(u64 val)
1526 /* Doesn't handle full ones or full zeroes */
1527 u64 sval = val >> __ffs64(val);
1529 /* One of Sean Eron Anderson's bithack tricks */
1530 return ((sval + 1) & (sval)) == 0;
1533 static u32 aarch64_encode_immediate(u64 imm,
1534 enum aarch64_insn_variant variant,
1537 unsigned int immr, imms, n, ones, ror, esz, tmp;
1540 /* Can't encode full zeroes or full ones */
1542 return AARCH64_BREAK_FAULT;
1545 case AARCH64_INSN_VARIANT_32BIT:
1546 if (upper_32_bits(imm))
1547 return AARCH64_BREAK_FAULT;
1550 case AARCH64_INSN_VARIANT_64BIT:
1551 insn |= AARCH64_INSN_SF_BIT;
1555 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1556 return AARCH64_BREAK_FAULT;
1560 * Inverse of Replicate(). Try to spot a repeating pattern
1561 * with a pow2 stride.
1563 for (tmp = esz / 2; tmp >= 2; tmp /= 2) {
1564 u64 emask = BIT(tmp) - 1;
1566 if ((imm & emask) != ((imm >> tmp) & emask))
1573 /* N is only set if we're encoding a 64bit value */
1576 /* Trim imm to the element size */
1579 /* That's how many ones we need to encode */
1580 ones = hweight64(imm);
1583 * imms is set to (ones - 1), prefixed with a string of ones
1584 * and a zero if they fit. Cap it to 6 bits.
1587 imms |= 0xf << ffs(esz);
1590 /* Compute the rotation */
1591 if (range_of_ones(imm)) {
1593 * Pattern: 0..01..10..0
1595 * Compute how many rotate we need to align it right
1600 * Pattern: 0..01..10..01..1
1602 * Fill the unused top bits with ones, and check if
1603 * the result is a valid immediate (all ones with a
1604 * contiguous ranges of zeroes).
1607 if (!range_of_ones(~imm))
1608 return AARCH64_BREAK_FAULT;
1611 * Compute the rotation to get a continuous set of
1612 * ones, with the first bit set at position 0
1618 * immr is the number of bits we need to rotate back to the
1619 * original set of ones. Note that this is relative to the
1622 immr = (esz - ror) % esz;
1624 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_N, insn, n);
1625 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_R, insn, immr);
1626 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_S, insn, imms);
1629 u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type,
1630 enum aarch64_insn_variant variant,
1631 enum aarch64_insn_register Rn,
1632 enum aarch64_insn_register Rd,
1638 case AARCH64_INSN_LOGIC_AND:
1639 insn = aarch64_insn_get_and_imm_value();
1641 case AARCH64_INSN_LOGIC_ORR:
1642 insn = aarch64_insn_get_orr_imm_value();
1644 case AARCH64_INSN_LOGIC_EOR:
1645 insn = aarch64_insn_get_eor_imm_value();
1647 case AARCH64_INSN_LOGIC_AND_SETFLAGS:
1648 insn = aarch64_insn_get_ands_imm_value();
1651 pr_err("%s: unknown logical encoding %d\n", __func__, type);
1652 return AARCH64_BREAK_FAULT;
1655 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, Rd);
1656 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, Rn);
1657 return aarch64_encode_immediate(imm, variant, insn);
1660 u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant,
1661 enum aarch64_insn_register Rm,
1662 enum aarch64_insn_register Rn,
1663 enum aarch64_insn_register Rd,
1668 insn = aarch64_insn_get_extr_value();
1671 case AARCH64_INSN_VARIANT_32BIT:
1673 return AARCH64_BREAK_FAULT;
1675 case AARCH64_INSN_VARIANT_64BIT:
1677 return AARCH64_BREAK_FAULT;
1678 insn |= AARCH64_INSN_SF_BIT;
1679 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_N, insn, 1);
1682 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1683 return AARCH64_BREAK_FAULT;
1686 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_S, insn, lsb);
1687 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, Rd);
1688 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, Rn);
1689 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, Rm);