1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2012 ARM Ltd.
6 * Author: Marc Zyngier <marc.zyngier@arm.com>
9 #include <linux/init.h>
10 #include <linux/linkage.h>
12 #include <asm/assembler.h>
13 #include <asm/el2_setup.h>
14 #include <asm/kvm_arm.h>
15 #include <asm/kvm_asm.h>
16 #include <asm/ptrace.h>
19 // Warning, hardcoded register allocation
20 // This will clobber x1 and x2, and expect x1 to contain
21 // the id register value as read from the HW
22 .macro __check_override idreg, fld, width, pass, fail
23 ubfx x1, x1, #\fld, #\width
26 adr_l x1, \idreg\()_override
27 ldr x2, [x1, FTR_OVR_VAL_OFFSET]
28 ldr x1, [x1, FTR_OVR_MASK_OFFSET]
29 ubfx x2, x2, #\fld, #\width
30 ubfx x1, x1, #\fld, #\width
38 .macro check_override idreg, fld, pass, fail
40 __check_override \idreg \fld 4 \pass \fail
44 .pushsection .hyp.text, "ax"
48 SYM_CODE_START(__hyp_stub_vectors)
49 ventry el2_sync_invalid // Synchronous EL2t
50 ventry el2_irq_invalid // IRQ EL2t
51 ventry el2_fiq_invalid // FIQ EL2t
52 ventry el2_error_invalid // Error EL2t
54 ventry elx_sync // Synchronous EL2h
55 ventry el2_irq_invalid // IRQ EL2h
56 ventry el2_fiq_invalid // FIQ EL2h
57 ventry el2_error_invalid // Error EL2h
59 ventry elx_sync // Synchronous 64-bit EL1
60 ventry el1_irq_invalid // IRQ 64-bit EL1
61 ventry el1_fiq_invalid // FIQ 64-bit EL1
62 ventry el1_error_invalid // Error 64-bit EL1
64 ventry el1_sync_invalid // Synchronous 32-bit EL1
65 ventry el1_irq_invalid // IRQ 32-bit EL1
66 ventry el1_fiq_invalid // FIQ 32-bit EL1
67 ventry el1_error_invalid // Error 32-bit EL1
68 SYM_CODE_END(__hyp_stub_vectors)
72 SYM_CODE_START_LOCAL(elx_sync)
73 cmp x0, #HVC_SET_VECTORS
78 1: cmp x0, #HVC_FINALISE_EL2
81 2: cmp x0, #HVC_SOFT_RESTART
89 3: cmp x0, #HVC_RESET_VECTORS
90 beq 9f // Nothing to reset!
92 /* Someone called kvm_call_hyp() against the hyp-stub... */
93 mov_q x0, HVC_STUB_ERR
98 SYM_CODE_END(elx_sync)
100 SYM_CODE_START_LOCAL(__finalise_el2)
101 check_override id_aa64pfr0 ID_AA64PFR0_SVE_SHIFT .Linit_sve .Lskip_sve
103 .Linit_sve: /* SVE register access */
104 mrs x0, cptr_el2 // Disable SVE traps
105 bic x0, x0, #CPTR_EL2_TZ
108 mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector
109 msr_s SYS_ZCR_EL2, x1 // length for EL1.
112 check_override id_aa64pfr1 ID_AA64PFR1_SME_SHIFT .Linit_sme .Lskip_sme
114 .Linit_sme: /* SME register access and priority mapping */
115 mrs x0, cptr_el2 // Disable SME traps
116 bic x0, x0, #CPTR_EL2_TSM
121 orr x1, x1, #SCTLR_ELx_ENTP2 // Disable TPIDR2 traps
125 mov x0, #0 // SMCR controls
128 mrs_s x1, SYS_ID_AA64SMFR0_EL1
129 __check_override id_aa64smfr0 ID_AA64SMFR0_EL1_FA64_SHIFT 1 .Linit_sme_fa64 .Lskip_sme_fa64
132 orr x0, x0, SMCR_ELx_FA64_MASK
135 orr x0, x0, #SMCR_ELx_LEN_MASK // Enable full SME vector
136 msr_s SYS_SMCR_EL2, x0 // length for EL1.
138 mrs_s x1, SYS_SMIDR_EL1 // Priority mapping supported?
139 ubfx x1, x1, #SMIDR_EL1_SMPS_SHIFT, #1
142 msr_s SYS_SMPRIMAP_EL2, xzr // Make all priorities equal
144 mrs x1, id_aa64mmfr1_el1 // HCRX_EL2 present?
145 ubfx x1, x1, #ID_AA64MMFR1_HCX_SHIFT, #4
148 mrs_s x1, SYS_HCRX_EL2
149 orr x1, x1, #HCRX_EL2_SMPME_MASK // Enable priority mapping
150 msr_s SYS_HCRX_EL2, x1
154 // nVHE? No way! Give me the real thing!
155 // Sanity check: MMU *must* be off
159 // Needs to be VHE capable, obviously
160 check_override id_aa64mmfr1 ID_AA64MMFR1_VHE_SHIFT 2f 1f
162 1: mov_q x0, HVC_STUB_ERR
165 // Engage the VHE magic!
166 mov_q x0, HCR_HOST_VHE_FLAGS
170 // Use the EL1 allocated stack, per-cpu offset
176 // FP configuration, vectors
177 mrs_s x0, SYS_CPACR_EL12
179 mrs_s x0, SYS_VBAR_EL12
182 // Use EL2 translations for SPE & TRBE and disable access from EL1
184 bic x0, x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)
185 bic x0, x0, #(MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT)
188 // Transfer the MM state from EL1 to EL2
189 mrs_s x0, SYS_TCR_EL12
191 mrs_s x0, SYS_TTBR0_EL12
193 mrs_s x0, SYS_TTBR1_EL12
195 mrs_s x0, SYS_MAIR_EL12
199 // Hack the exception return to stay at EL2
201 and x0, x0, #~PSR_MODE_MASK
202 mov x1, #PSR_MODE_EL2h
207 SYM_CODE_END(__finalise_el2)
209 // At the point where we reach enter_vhe(), we run with
210 // the MMU off (which is enforced by __finalise_el2()).
211 // We thus need to be in the idmap, or everything will
212 // explode when enabling the MMU.
214 .pushsection .idmap.text, "ax"
216 SYM_CODE_START_LOCAL(enter_vhe)
217 // Invalidate TLBs before enabling the MMU
222 // Enable the EL2 S1 MMU, as set up from EL1
223 mrs_s x0, SYS_SCTLR_EL12
226 // Disable the EL1 S1 MMU for a good measure
227 mov_q x0, INIT_SCTLR_EL1_MMU_OFF
228 msr_s SYS_SCTLR_EL12, x0
233 SYM_CODE_END(enter_vhe)
237 .macro invalid_vector label
238 SYM_CODE_START_LOCAL(\label)
243 invalid_vector el2_sync_invalid
244 invalid_vector el2_irq_invalid
245 invalid_vector el2_fiq_invalid
246 invalid_vector el2_error_invalid
247 invalid_vector el1_sync_invalid
248 invalid_vector el1_irq_invalid
249 invalid_vector el1_fiq_invalid
250 invalid_vector el1_error_invalid
255 * __hyp_set_vectors: Call this after boot to set the initial hypervisor
256 * vectors as part of hypervisor installation. On an SMP system, this should
257 * be called on each CPU.
259 * x0 must be the physical address of the new vector table, and must be
262 * Before calling this, you must check that the stub hypervisor is installed
263 * everywhere, by waiting for any secondary CPUs to be brought up and then
264 * checking that is_hyp_mode_available() is true.
266 * If not, there is a pre-existing hypervisor, some CPUs failed to boot, or
267 * something else went wrong... in such cases, trying to install a new
268 * hypervisor is unlikely to work as desired.
270 * When you call into your shiny new hypervisor, sp_el2 will contain junk,
271 * so you will need to set that to something sensible at the new hypervisor's
272 * initialisation entry point.
275 SYM_FUNC_START(__hyp_set_vectors)
277 mov x0, #HVC_SET_VECTORS
280 SYM_FUNC_END(__hyp_set_vectors)
282 SYM_FUNC_START(__hyp_reset_vectors)
283 mov x0, #HVC_RESET_VECTORS
286 SYM_FUNC_END(__hyp_reset_vectors)
289 * Entry point to finalise EL2 and switch to VHE if deemed capable
291 * w0: boot mode, as returned by init_kernel_el()
293 SYM_FUNC_START(finalise_el2)
294 // Need to have booted at EL2
295 cmp w0, #BOOT_CPU_MODE_EL2
298 // and still be at EL1
300 cmp x0, #CurrentEL_EL1
303 mov x0, #HVC_FINALISE_EL2
307 SYM_FUNC_END(finalise_el2)