1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Low-level CPU initialisation
4 * Based on arch/arm/kernel/head.S
6 * Copyright (C) 1994-2002 Russell King
7 * Copyright (C) 2003-2012 ARM Ltd.
8 * Authors: Catalin Marinas <catalin.marinas@arm.com>
9 * Will Deacon <will.deacon@arm.com>
12 #include <linux/linkage.h>
13 #include <linux/init.h>
14 #include <linux/pgtable.h>
16 #include <asm/asm_pointer_auth.h>
17 #include <asm/assembler.h>
20 #include <asm/ptrace.h>
21 #include <asm/asm-offsets.h>
22 #include <asm/cache.h>
23 #include <asm/cputype.h>
24 #include <asm/el2_setup.h>
26 #include <asm/image.h>
27 #include <asm/kernel-pgtable.h>
28 #include <asm/kvm_arm.h>
29 #include <asm/memory.h>
30 #include <asm/pgtable-hwdef.h>
34 #include <asm/sysreg.h>
35 #include <asm/thread_info.h>
38 #include "efi-header.S"
40 #if (PAGE_OFFSET & 0x1fffff) != 0
41 #error PAGE_OFFSET must be at least 2MB aligned
45 * Kernel startup entry point.
46 * ---------------------------
48 * The requirements are:
49 * MMU = off, D-cache = off, I-cache = on or off,
50 * x0 = physical address to the FDT blob.
52 * Note that the callee-saved registers are used for storing variables
53 * that are useful before the MMU is enabled. The allocations are described
54 * in the entry routines.
58 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
60 efi_signature_nop // special NOP to identity as PE/COFF executable
61 b primary_entry // branch to kernel start, magic
62 .quad 0 // Image load offset from start of RAM, little-endian
63 le64sym _kernel_size_le // Effective size of kernel image, little-endian
64 le64sym _kernel_flags_le // Informative flags, little-endian
68 .ascii ARM64_IMAGE_MAGIC // Magic number
69 .long .Lpe_header_offset // Offset to the PE header.
73 .section ".idmap.text","a"
76 * The following callee saved general purpose registers are used on the
77 * primary lowlevel boot path:
79 * Register Scope Purpose
80 * x19 primary_entry() .. start_kernel() whether we entered with the MMU on
81 * x20 primary_entry() .. __primary_switch() CPU boot mode
82 * x21 primary_entry() .. start_kernel() FDT pointer passed at boot in x0
84 SYM_CODE_START(primary_entry)
88 adrp x1, early_init_stack
91 adrp x0, init_idmap_pg_dir
93 bl __pi_create_init_idmap
96 * If the page tables have been populated with non-cacheable
97 * accesses (MMU disabled), invalidate those tables again to
98 * remove any speculatively loaded cache lines.
102 mov x1, x0 // end of used region
103 adrp x0, init_idmap_pg_dir
104 adr_l x2, dcache_inval_poc
109 * If we entered with the MMU and caches on, clean the ID mapped part
110 * of the primary boot code to the PoC so we can safely execute it with
113 0: adrp x0, __idmap_text_start
114 adr_l x1, __idmap_text_end
115 adr_l x2, dcache_clean_poc
119 bl init_kernel_el // w0=cpu_boot_mode
123 * The following calls CPU setup code, see arch/arm64/mm/proc.S for
125 * On return, the CPU will be ready for the MMU to be turned on and
126 * the TCR will have been set.
128 bl __cpu_setup // initialise processor
130 SYM_CODE_END(primary_entry)
133 SYM_CODE_START_LOCAL(record_mmu_state)
135 cmp x19, #CurrentEL_EL2
140 CPU_LE( tbnz x19, #SCTLR_ELx_EE_SHIFT, 1f )
141 CPU_BE( tbz x19, #SCTLR_ELx_EE_SHIFT, 1f )
142 tst x19, #SCTLR_ELx_C // Z := (C == 0)
143 and x19, x19, #SCTLR_ELx_M // isolate M bit
144 csel x19, xzr, x19, eq // clear x19 if Z
148 * Set the correct endianness early so all memory accesses issued
149 * before init_kernel_el() occur in the correct byte order. Note that
150 * this means the MMU must be disabled, or the active ID map will end
151 * up getting interpreted with the wrong byte order.
153 1: eor x19, x19, #SCTLR_ELx_EE
154 bic x19, x19, #SCTLR_ELx_M
156 pre_disable_mmu_workaround
159 2: pre_disable_mmu_workaround
164 SYM_CODE_END(record_mmu_state)
167 * Preserve the arguments passed by the bootloader in x0 .. x3
169 SYM_CODE_START_LOCAL(preserve_boot_args)
170 mov x21, x0 // x21=FDT
172 adr_l x0, boot_args // record the contents of
173 stp x21, x1, [x0] // x0 .. x3 at kernel entry
174 stp x2, x3, [x0, #16]
176 cbnz x19, 0f // skip cache invalidation if MMU is on
177 dmb sy // needed before dc ivac with
180 add x1, x0, #0x20 // 4 x 8 bytes
181 b dcache_inval_poc // tail call
182 0: str_l x19, mmu_enabled_at_boot, x0
184 SYM_CODE_END(preserve_boot_args)
187 * Initialize CPU registers with task-specific and cpu-specific context.
189 * Create a final frame record at task_pt_regs(current)->stackframe, so
190 * that the unwinder can identify the final frame record of any task by
191 * its location in the task stack. We reserve the entire pt_regs space
192 * for consistency with user tasks and kthreads.
194 .macro init_cpu_task tsk, tmp1, tmp2
197 ldr \tmp1, [\tsk, #TSK_STACK]
198 add sp, \tmp1, #THREAD_SIZE
199 sub sp, sp, #PT_REGS_SIZE
201 stp xzr, xzr, [sp, #S_STACKFRAME]
202 add x29, sp, #S_STACKFRAME
206 adr_l \tmp1, __per_cpu_offset
207 ldr w\tmp2, [\tsk, #TSK_TI_CPU]
208 ldr \tmp1, [\tmp1, \tmp2, lsl #3]
209 set_this_cpu_offset \tmp1
213 * The following fragment of code is executed with the MMU enabled.
215 * x0 = __pa(KERNEL_START)
217 SYM_FUNC_START_LOCAL(__primary_switched)
219 init_cpu_task x4, x5, x6
221 adr_l x8, vectors // load VBAR_EL1 with virtual
222 msr vbar_el1, x8 // vector table address
225 stp x29, x30, [sp, #-16]!
228 str_l x21, __fdt_pointer, x5 // Save FDT pointer
230 adrp x4, _text // Save the offset between
231 sub x4, x4, x0 // the kernel virtual and
232 str_l x4, kimage_voffset, x5 // physical mappings
235 bl set_cpu_boot_mode_flag
237 #if defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS)
241 bl finalise_el2 // Prefer VHE if possible
242 ldp x29, x30, [sp], #16
245 SYM_FUNC_END(__primary_switched)
248 * end early head section, begin head code that is also used for
249 * hotplug and needs to have the same protections as the text region
251 .section ".idmap.text","a"
254 * Starting from EL2 or EL1, configure the CPU to execute at the highest
255 * reachable EL supported by the kernel in a chosen default state. If dropping
256 * from EL2 to EL1, configure EL2 before configuring EL1.
258 * Since we cannot always rely on ERET synchronizing writes to sysregs (e.g. if
259 * SCTLR_ELx.EOS is clear), we place an ISB prior to ERET.
261 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x0 if
262 * booted in EL1 or EL2 respectively, with the top 32 bits containing
263 * potential context flags. These flags are *not* stored in __boot_cpu_mode.
265 * x0: whether we are being called from the primary boot path with the MMU on
267 SYM_FUNC_START(init_kernel_el)
269 cmp x1, #CurrentEL_EL2
272 SYM_INNER_LABEL(init_el1, SYM_L_LOCAL)
273 mov_q x0, INIT_SCTLR_EL1_MMU_OFF
274 pre_disable_mmu_workaround
277 mov_q x0, INIT_PSTATE_EL1
280 mov w0, #BOOT_CPU_MODE_EL1
283 SYM_INNER_LABEL(init_el2, SYM_L_LOCAL)
286 // clean all HYP code to the PoC if we booted at EL2 with the MMU on
288 adrp x0, __hyp_idmap_text_start
289 adr_l x1, __hyp_text_end
290 adr_l x2, dcache_clean_poc
293 mov_q x0, HCR_HOST_NVHE_FLAGS
299 /* Hypervisor stub */
300 adr_l x0, __hyp_stub_vectors
304 mov_q x1, INIT_SCTLR_EL1_MMU_OFF
307 * Compliant CPUs advertise their VHE-onlyness with
308 * ID_AA64MMFR4_EL1.E2H0 < 0. HCR_EL2.E2H can be
311 * Fruity CPUs seem to have HCR_EL2.E2H set to RES1, but
312 * don't advertise it (they predate this relaxation).
314 mrs_s x0, SYS_ID_AA64MMFR4_EL1
315 ubfx x0, x0, #ID_AA64MMFR4_EL1_E2H0_SHIFT, #ID_AA64MMFR4_EL1_E2H0_WIDTH
316 tbnz x0, #(ID_AA64MMFR4_EL1_E2H0_SHIFT + ID_AA64MMFR4_EL1_E2H0_WIDTH - 1), 1f
322 /* Set a sane SCTLR_EL1, the VHE way */
323 pre_disable_mmu_workaround
324 msr_s SYS_SCTLR_EL12, x1
325 mov x2, #BOOT_CPU_FLAG_E2H
329 pre_disable_mmu_workaround
333 __init_el2_nvhe_prepare_eret
335 mov w0, #BOOT_CPU_MODE_EL2
338 SYM_FUNC_END(init_kernel_el)
341 * This provides a "holding pen" for platforms to hold all secondary
342 * cores are held until we're ready for them to initialise.
344 SYM_FUNC_START(secondary_holding_pen)
346 bl init_kernel_el // w0=cpu_boot_mode
348 mov_q x1, MPIDR_HWID_BITMASK
350 adr_l x3, secondary_holding_pen_release
353 b.eq secondary_startup
356 SYM_FUNC_END(secondary_holding_pen)
359 * Secondary entry point that jumps straight into the kernel. Only to
360 * be used where CPUs are brought online dynamically by the kernel.
362 SYM_FUNC_START(secondary_entry)
364 bl init_kernel_el // w0=cpu_boot_mode
366 SYM_FUNC_END(secondary_entry)
368 SYM_FUNC_START_LOCAL(secondary_startup)
370 * Common entry point for secondary CPUs.
372 mov x20, x0 // preserve boot mode
374 #ifdef CONFIG_ARM64_VA_BITS_52
375 alternative_if ARM64_HAS_VA52
376 bl __cpu_secondary_check52bitva
377 alternative_else_nop_endif
380 bl __cpu_setup // initialise processor
381 adrp x1, swapper_pg_dir
382 adrp x2, idmap_pg_dir
384 ldr x8, =__secondary_switched
386 SYM_FUNC_END(secondary_startup)
389 SYM_FUNC_START_LOCAL(__secondary_switched)
391 bl set_cpu_boot_mode_flag
396 str_l xzr, __early_cpu_boot_status, x3
401 adr_l x0, secondary_data
402 ldr x2, [x0, #CPU_BOOT_TASK]
403 cbz x2, __secondary_too_slow
405 init_cpu_task x2, x1, x3
407 #ifdef CONFIG_ARM64_PTR_AUTH
408 ptrauth_keys_init_cpu x2, x3, x4, x5
411 bl secondary_start_kernel
413 SYM_FUNC_END(__secondary_switched)
415 SYM_FUNC_START_LOCAL(__secondary_too_slow)
418 b __secondary_too_slow
419 SYM_FUNC_END(__secondary_too_slow)
422 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
423 * in w0. See arch/arm64/include/asm/virt.h for more info.
425 SYM_FUNC_START_LOCAL(set_cpu_boot_mode_flag)
426 adr_l x1, __boot_cpu_mode
427 cmp w0, #BOOT_CPU_MODE_EL2
430 1: str w0, [x1] // Save CPU boot mode
432 SYM_FUNC_END(set_cpu_boot_mode_flag)
435 * The booting CPU updates the failed status @__early_cpu_boot_status,
436 * with MMU turned off.
438 * update_early_cpu_boot_status tmp, status
439 * - Corrupts tmp1, tmp2
440 * - Writes 'status' to __early_cpu_boot_status and makes sure
441 * it is committed to memory.
444 .macro update_early_cpu_boot_status status, tmp1, tmp2
446 adr_l \tmp1, __early_cpu_boot_status
449 dc ivac, \tmp1 // Invalidate potentially stale cache line
455 * x0 = SCTLR_EL1 value for turning on the MMU.
456 * x1 = TTBR1_EL1 value
457 * x2 = ID map root table address
459 * Returns to the caller via x30/lr. This requires the caller to be covered
460 * by the .idmap.text section.
462 * Checks if the selected granule size is supported by the CPU.
463 * If it isn't, park the CPU
465 .section ".idmap.text","a"
466 SYM_FUNC_START(__enable_mmu)
467 mrs x3, ID_AA64MMFR0_EL1
468 ubfx x3, x3, #ID_AA64MMFR0_EL1_TGRAN_SHIFT, 4
469 cmp x3, #ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN
470 b.lt __no_granule_support
471 cmp x3, #ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX
472 b.gt __no_granule_support
474 msr ttbr0_el1, x2 // load TTBR0
475 load_ttbr1 x1, x1, x3
480 SYM_FUNC_END(__enable_mmu)
482 #ifdef CONFIG_ARM64_VA_BITS_52
483 SYM_FUNC_START(__cpu_secondary_check52bitva)
484 #ifndef CONFIG_ARM64_LPA2
485 mrs_s x0, SYS_ID_AA64MMFR2_EL1
486 and x0, x0, ID_AA64MMFR2_EL1_VARange_MASK
489 mrs x0, id_aa64mmfr0_el1
490 sbfx x0, x0, #ID_AA64MMFR0_EL1_TGRAN_SHIFT, 4
491 cmp x0, #ID_AA64MMFR0_EL1_TGRAN_LPA2
495 update_early_cpu_boot_status \
496 CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_52_BIT_VA, x0, x1
502 SYM_FUNC_END(__cpu_secondary_check52bitva)
505 SYM_FUNC_START_LOCAL(__no_granule_support)
506 /* Indicate that this CPU can't boot and is stuck in the kernel */
507 update_early_cpu_boot_status \
508 CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_NO_GRAN, x1, x2
513 SYM_FUNC_END(__no_granule_support)
515 SYM_FUNC_START_LOCAL(__primary_switch)
516 adrp x1, reserved_pg_dir
517 adrp x2, init_idmap_pg_dir
520 adrp x1, early_init_stack
523 mov x0, x20 // pass the full boot status
524 mov x1, x21 // pass the FDT
525 bl __pi_early_map_kernel // Map and relocate the kernel
527 ldr x8, =__primary_switched
528 adrp x0, KERNEL_START // __pa(KERNEL_START)
530 SYM_FUNC_END(__primary_switch)