1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Low-level CPU initialisation
4 * Based on arch/arm/kernel/head.S
6 * Copyright (C) 1994-2002 Russell King
7 * Copyright (C) 2003-2012 ARM Ltd.
8 * Authors: Catalin Marinas <catalin.marinas@arm.com>
9 * Will Deacon <will.deacon@arm.com>
12 #include <linux/linkage.h>
13 #include <linux/init.h>
14 #include <linux/pgtable.h>
16 #include <asm/asm_pointer_auth.h>
17 #include <asm/assembler.h>
19 #include <asm/ptrace.h>
20 #include <asm/asm-offsets.h>
21 #include <asm/cache.h>
22 #include <asm/cputype.h>
23 #include <asm/el2_setup.h>
25 #include <asm/image.h>
26 #include <asm/kernel-pgtable.h>
27 #include <asm/kvm_arm.h>
28 #include <asm/memory.h>
29 #include <asm/pgtable-hwdef.h>
33 #include <asm/sysreg.h>
34 #include <asm/thread_info.h>
37 #include "efi-header.S"
39 #define __PHYS_OFFSET KERNEL_START
41 #if (PAGE_OFFSET & 0x1fffff) != 0
42 #error PAGE_OFFSET must be at least 2MB aligned
46 * Kernel startup entry point.
47 * ---------------------------
49 * The requirements are:
50 * MMU = off, D-cache = off, I-cache = on or off,
51 * x0 = physical address to the FDT blob.
53 * This code is mostly position independent so you call this at
56 * Note that the callee-saved registers are used for storing variables
57 * that are useful before the MMU is enabled. The allocations are described
58 * in the entry routines.
62 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
64 efi_signature_nop // special NOP to identity as PE/COFF executable
65 b primary_entry // branch to kernel start, magic
66 .quad 0 // Image load offset from start of RAM, little-endian
67 le64sym _kernel_size_le // Effective size of kernel image, little-endian
68 le64sym _kernel_flags_le // Informative flags, little-endian
72 .ascii ARM64_IMAGE_MAGIC // Magic number
73 .long .Lpe_header_offset // Offset to the PE header.
80 * The following callee saved general purpose registers are used on the
81 * primary lowlevel boot path:
83 * Register Scope Purpose
84 * x21 primary_entry() .. start_kernel() FDT pointer passed at boot in x0
85 * x23 primary_entry() .. start_kernel() physical misalignment/KASLR offset
86 * x28 __create_page_tables() callee preserved temp register
87 * x19/x20 __primary_switch() callee preserved temp registers
88 * x24 __primary_switch() .. relocate_kernel() current RELR displacement
90 SYM_CODE_START(primary_entry)
92 bl init_kernel_el // w0=cpu_boot_mode
93 adrp x23, __PHYS_OFFSET
94 and x23, x23, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0
95 bl set_cpu_boot_mode_flag
96 bl __create_page_tables
98 * The following calls CPU setup code, see arch/arm64/mm/proc.S for
100 * On return, the CPU will be ready for the MMU to be turned on and
101 * the TCR will have been set.
103 bl __cpu_setup // initialise processor
105 SYM_CODE_END(primary_entry)
108 * Preserve the arguments passed by the bootloader in x0 .. x3
110 SYM_CODE_START_LOCAL(preserve_boot_args)
111 mov x21, x0 // x21=FDT
113 adr_l x0, boot_args // record the contents of
114 stp x21, x1, [x0] // x0 .. x3 at kernel entry
115 stp x2, x3, [x0, #16]
117 dmb sy // needed before dc ivac with
120 mov x1, #0x20 // 4 x 8 bytes
121 b __inval_dcache_area // tail call
122 SYM_CODE_END(preserve_boot_args)
125 * Macro to create a table entry to the next page.
127 * tbl: page table address
128 * virt: virtual address
129 * shift: #imm page table shift
130 * ptrs: #imm pointers per table page
133 * Corrupts: ptrs, tmp1, tmp2
134 * Returns: tbl -> next level table page address
136 .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2
137 add \tmp1, \tbl, #PAGE_SIZE
138 phys_to_pte \tmp2, \tmp1
139 orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type
140 lsr \tmp1, \virt, #\shift
142 and \tmp1, \tmp1, \ptrs // table index
143 str \tmp2, [\tbl, \tmp1, lsl #3]
144 add \tbl, \tbl, #PAGE_SIZE // next level table page
148 * Macro to populate page table entries, these entries can be pointers to the next level
149 * or last level entries pointing to physical memory.
151 * tbl: page table address
152 * rtbl: pointer to page table or physical memory
153 * index: start index to write
154 * eindex: end index to write - [index, eindex] written to
155 * flags: flags for pagetable entry to or in
156 * inc: increment to rtbl between each entry
157 * tmp1: temporary variable
159 * Preserves: tbl, eindex, flags, inc
160 * Corrupts: index, tmp1
163 .macro populate_entries, tbl, rtbl, index, eindex, flags, inc, tmp1
164 .Lpe\@: phys_to_pte \tmp1, \rtbl
165 orr \tmp1, \tmp1, \flags // tmp1 = table entry
166 str \tmp1, [\tbl, \index, lsl #3]
167 add \rtbl, \rtbl, \inc // rtbl = pa next level
168 add \index, \index, #1
174 * Compute indices of table entries from virtual address range. If multiple entries
175 * were needed in the previous page table level then the next page table level is assumed
176 * to be composed of multiple pages. (This effectively scales the end index).
178 * vstart: virtual address of start of range
179 * vend: virtual address of end of range
180 * shift: shift used to transform virtual address into index
181 * ptrs: number of entries in page table
182 * istart: index in table corresponding to vstart
183 * iend: index in table corresponding to vend
184 * count: On entry: how many extra entries were required in previous level, scales
186 * On exit: returns how many extra entries required for next page table level
188 * Preserves: vstart, vend, shift, ptrs
189 * Returns: istart, iend, count
191 .macro compute_indices, vstart, vend, shift, ptrs, istart, iend, count
192 lsr \iend, \vend, \shift
194 sub \istart, \istart, #1
195 and \iend, \iend, \istart // iend = (vend >> shift) & (ptrs - 1)
197 mul \istart, \istart, \count
198 add \iend, \iend, \istart // iend += (count - 1) * ptrs
199 // our entries span multiple tables
201 lsr \istart, \vstart, \shift
203 sub \count, \count, #1
204 and \istart, \istart, \count
206 sub \count, \iend, \istart
210 * Map memory for specified virtual address range. Each level of page table needed supports
211 * multiple entries. If a level requires n entries the next page table level is assumed to be
212 * formed from n pages.
214 * tbl: location of page table
215 * rtbl: address to be used for first level page table entry (typically tbl + PAGE_SIZE)
216 * vstart: start address to map
217 * vend: end address to map - we map [vstart, vend]
218 * flags: flags to use to map last level entries
219 * phys: physical address corresponding to vstart - physical memory is contiguous
220 * pgds: the number of pgd entries
222 * Temporaries: istart, iend, tmp, count, sv - these need to be different registers
223 * Preserves: vstart, vend, flags
224 * Corrupts: tbl, rtbl, istart, iend, tmp, count, sv
226 .macro map_memory, tbl, rtbl, vstart, vend, flags, phys, pgds, istart, iend, tmp, count, sv
227 add \rtbl, \tbl, #PAGE_SIZE
230 compute_indices \vstart, \vend, #PGDIR_SHIFT, \pgds, \istart, \iend, \count
231 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
235 #if SWAPPER_PGTABLE_LEVELS > 3
236 compute_indices \vstart, \vend, #PUD_SHIFT, #PTRS_PER_PUD, \istart, \iend, \count
237 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
242 #if SWAPPER_PGTABLE_LEVELS > 2
243 compute_indices \vstart, \vend, #SWAPPER_TABLE_SHIFT, #PTRS_PER_PMD, \istart, \iend, \count
244 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
248 compute_indices \vstart, \vend, #SWAPPER_BLOCK_SHIFT, #PTRS_PER_PTE, \istart, \iend, \count
249 bic \count, \phys, #SWAPPER_BLOCK_SIZE - 1
250 populate_entries \tbl, \count, \istart, \iend, \flags, #SWAPPER_BLOCK_SIZE, \tmp
254 * Setup the initial page tables. We only setup the barest amount which is
255 * required to get the kernel running. The following sections are required:
256 * - identity mapping to enable the MMU (low address, TTBR0)
257 * - first few MB of the kernel linear mapping to jump to once the MMU has
260 SYM_FUNC_START_LOCAL(__create_page_tables)
264 * Invalidate the init page tables to avoid potential dirty cache lines
265 * being evicted. Other page tables are allocated in rodata as part of
266 * the kernel image, and thus are clean to the PoC per the boot
272 bl __inval_dcache_area
275 * Clear the init page tables.
280 1: stp xzr, xzr, [x0], #16
281 stp xzr, xzr, [x0], #16
282 stp xzr, xzr, [x0], #16
283 stp xzr, xzr, [x0], #16
287 mov x7, SWAPPER_MM_MMUFLAGS
290 * Create the identity mapping.
292 adrp x0, idmap_pg_dir
293 adrp x3, __idmap_text_start // __pa(__idmap_text_start)
295 #ifdef CONFIG_ARM64_VA_BITS_52
296 mrs_s x6, SYS_ID_AA64MMFR2_EL1
297 and x6, x6, #(0xf << ID_AA64MMFR2_LVA_SHIFT)
303 adr_l x6, vabits_actual
306 dc ivac, x6 // Invalidate potentially stale cache line
309 * VA_BITS may be too small to allow for an ID mapping to be created
310 * that covers system RAM if that is located sufficiently high in the
311 * physical address space. So for the ID map, use an extended virtual
312 * range in that case, and configure an additional translation level
315 * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the
316 * entire ID map region can be mapped. As T0SZ == (64 - #bits used),
317 * this number conveniently equals the number of leading zeroes in
318 * the physical address of __idmap_text_end.
320 adrp x5, __idmap_text_end
322 cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough?
323 b.ge 1f // .. then skip VA range extension
328 dc ivac, x6 // Invalidate potentially stale cache line
331 #define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3)
332 #define EXTRA_PTRS (1 << (PHYS_MASK_SHIFT - EXTRA_SHIFT))
335 * If VA_BITS < 48, we have to configure an additional table level.
336 * First, we have to verify our assumption that the current value of
337 * VA_BITS was chosen such that all translation levels are fully
338 * utilised, and that lowering T0SZ will always result in an additional
339 * translation level to be configured.
341 #if VA_BITS != EXTRA_SHIFT
342 #error "Mismatch between VA_BITS and page size/number of translation levels"
346 create_table_entry x0, x3, EXTRA_SHIFT, x4, x5, x6
349 * If VA_BITS == 48, we don't have to configure an additional
350 * translation level, but the top-level table has more entries.
352 mov x4, #1 << (PHYS_MASK_SHIFT - PGDIR_SHIFT)
353 str_l x4, idmap_ptrs_per_pgd, x5
356 ldr_l x4, idmap_ptrs_per_pgd
357 mov x5, x3 // __pa(__idmap_text_start)
358 adr_l x6, __idmap_text_end // __pa(__idmap_text_end)
360 map_memory x0, x1, x3, x6, x7, x3, x4, x10, x11, x12, x13, x14
363 * Map the kernel image (starting with PHYS_OFFSET).
366 mov_q x5, KIMAGE_VADDR // compile time __va(_text)
367 add x5, x5, x23 // add KASLR displacement
369 adrp x6, _end // runtime __pa(_end)
370 adrp x3, _text // runtime __pa(_text)
371 sub x6, x6, x3 // _end - _text
372 add x6, x6, x5 // runtime __va(_end)
374 map_memory x0, x1, x5, x6, x7, x3, x4, x10, x11, x12, x13, x14
377 * Since the page tables have been populated with non-cacheable
378 * accesses (MMU disabled), invalidate those tables again to
379 * remove any speculatively loaded cache lines.
383 adrp x0, idmap_pg_dir
384 adrp x1, idmap_pg_end
386 bl __inval_dcache_area
391 bl __inval_dcache_area
394 SYM_FUNC_END(__create_page_tables)
397 * The following fragment of code is executed with the MMU enabled.
401 SYM_FUNC_START_LOCAL(__primary_switched)
402 adrp x4, init_thread_union
403 add sp, x4, #THREAD_SIZE
405 msr sp_el0, x5 // Save thread_info
407 #ifdef CONFIG_ARM64_PTR_AUTH
408 __ptrauth_keys_init_cpu x5, x6, x7, x8
411 adr_l x8, vectors // load VBAR_EL1 with virtual
412 msr vbar_el1, x8 // vector table address
415 stp xzr, x30, [sp, #-16]!
418 #ifdef CONFIG_SHADOW_CALL_STACK
419 adr_l scs_sp, init_shadow_call_stack // Set shadow call stack
422 str_l x21, __fdt_pointer, x5 // Save FDT pointer
424 ldr_l x4, kimage_vaddr // Save the offset between
425 sub x4, x4, x0 // the kernel virtual and
426 str_l x4, kimage_voffset, x5 // physical mappings
429 adr_l x0, __bss_start
434 dsb ishst // Make zero page visible to PTW
436 #if defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS)
439 mov x0, x21 // pass FDT address in x0
440 bl early_fdt_map // Try mapping the FDT early
441 #ifdef CONFIG_RANDOMIZE_BASE
442 tst x23, ~(MIN_KIMG_ALIGN - 1) // already running randomized?
444 bl kaslr_early_init // parse FDT for KASLR options
445 cbz x0, 0f // KASLR disabled? just proceed
446 orr x23, x23, x0 // record KASLR offset
447 ldp x29, x30, [sp], #16 // we must enable KASLR, return
448 ret // to __primary_switch()
451 bl switch_to_vhe // Prefer VHE if possible
456 SYM_FUNC_END(__primary_switched)
458 .pushsection ".rodata", "a"
459 SYM_DATA_START(kimage_vaddr)
461 SYM_DATA_END(kimage_vaddr)
462 EXPORT_SYMBOL(kimage_vaddr)
466 * end early head section, begin head code that is also used for
467 * hotplug and needs to have the same protections as the text region
469 .section ".idmap.text","awx"
472 * Starting from EL2 or EL1, configure the CPU to execute at the highest
473 * reachable EL supported by the kernel in a chosen default state. If dropping
474 * from EL2 to EL1, configure EL2 before configuring EL1.
476 * Since we cannot always rely on ERET synchronizing writes to sysregs (e.g. if
477 * SCTLR_ELx.EOS is clear), we place an ISB prior to ERET.
479 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in w0 if
480 * booted in EL1 or EL2 respectively.
482 SYM_FUNC_START(init_kernel_el)
483 mov_q x0, INIT_SCTLR_EL1_MMU_OFF
487 cmp x0, #CurrentEL_EL2
490 SYM_INNER_LABEL(init_el1, SYM_L_LOCAL)
492 mov_q x0, INIT_PSTATE_EL1
495 mov w0, #BOOT_CPU_MODE_EL1
498 SYM_INNER_LABEL(init_el2, SYM_L_LOCAL)
499 mov_q x0, HCR_HOST_NVHE_FLAGS
505 /* Hypervisor stub */
506 adr_l x0, __hyp_stub_vectors
511 mov w0, #BOOT_CPU_MODE_EL2
513 SYM_FUNC_END(init_kernel_el)
516 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
517 * in w0. See arch/arm64/include/asm/virt.h for more info.
519 SYM_FUNC_START_LOCAL(set_cpu_boot_mode_flag)
520 adr_l x1, __boot_cpu_mode
521 cmp w0, #BOOT_CPU_MODE_EL2
524 1: str w0, [x1] // This CPU has booted in EL1
526 dc ivac, x1 // Invalidate potentially stale cache line
528 SYM_FUNC_END(set_cpu_boot_mode_flag)
531 * These values are written with the MMU off, but read with the MMU on.
532 * Writers will invalidate the corresponding address, discarding up to a
533 * 'Cache Writeback Granule' (CWG) worth of data. The linker script ensures
534 * sufficient alignment that the CWG doesn't overlap another section.
536 .pushsection ".mmuoff.data.write", "aw"
538 * We need to find out the CPU boot mode long after boot, so we need to
539 * store it in a writable variable.
541 * This is not in .bss, because we set it sufficiently early that the boot-time
542 * zeroing of .bss would clobber it.
544 SYM_DATA_START(__boot_cpu_mode)
545 .long BOOT_CPU_MODE_EL2
546 .long BOOT_CPU_MODE_EL1
547 SYM_DATA_END(__boot_cpu_mode)
549 * The booting CPU updates the failed status @__early_cpu_boot_status,
550 * with MMU turned off.
552 SYM_DATA_START(__early_cpu_boot_status)
554 SYM_DATA_END(__early_cpu_boot_status)
559 * This provides a "holding pen" for platforms to hold all secondary
560 * cores are held until we're ready for them to initialise.
562 SYM_FUNC_START(secondary_holding_pen)
563 bl init_kernel_el // w0=cpu_boot_mode
564 bl set_cpu_boot_mode_flag
566 mov_q x1, MPIDR_HWID_BITMASK
568 adr_l x3, secondary_holding_pen_release
571 b.eq secondary_startup
574 SYM_FUNC_END(secondary_holding_pen)
577 * Secondary entry point that jumps straight into the kernel. Only to
578 * be used where CPUs are brought online dynamically by the kernel.
580 SYM_FUNC_START(secondary_entry)
581 bl init_kernel_el // w0=cpu_boot_mode
582 bl set_cpu_boot_mode_flag
584 SYM_FUNC_END(secondary_entry)
586 SYM_FUNC_START_LOCAL(secondary_startup)
588 * Common entry point for secondary CPUs.
591 bl __cpu_secondary_check52bitva
592 bl __cpu_setup // initialise processor
593 adrp x1, swapper_pg_dir
595 ldr x8, =__secondary_switched
597 SYM_FUNC_END(secondary_startup)
599 SYM_FUNC_START_LOCAL(__secondary_switched)
604 adr_l x0, secondary_data
605 ldr x1, [x0, #CPU_BOOT_STACK] // get secondary_data.stack
606 cbz x1, __secondary_too_slow
608 ldr x2, [x0, #CPU_BOOT_TASK]
609 cbz x2, __secondary_too_slow
615 #ifdef CONFIG_ARM64_PTR_AUTH
616 ptrauth_keys_init_cpu x2, x3, x4, x5
619 b secondary_start_kernel
620 SYM_FUNC_END(__secondary_switched)
622 SYM_FUNC_START_LOCAL(__secondary_too_slow)
625 b __secondary_too_slow
626 SYM_FUNC_END(__secondary_too_slow)
629 * The booting CPU updates the failed status @__early_cpu_boot_status,
630 * with MMU turned off.
632 * update_early_cpu_boot_status tmp, status
633 * - Corrupts tmp1, tmp2
634 * - Writes 'status' to __early_cpu_boot_status and makes sure
635 * it is committed to memory.
638 .macro update_early_cpu_boot_status status, tmp1, tmp2
640 adr_l \tmp1, __early_cpu_boot_status
643 dc ivac, \tmp1 // Invalidate potentially stale cache line
649 * x0 = SCTLR_EL1 value for turning on the MMU.
650 * x1 = TTBR1_EL1 value
652 * Returns to the caller via x30/lr. This requires the caller to be covered
653 * by the .idmap.text section.
655 * Checks if the selected granule size is supported by the CPU.
656 * If it isn't, park the CPU
658 SYM_FUNC_START(__enable_mmu)
659 mrs x2, ID_AA64MMFR0_EL1
660 ubfx x2, x2, #ID_AA64MMFR0_TGRAN_SHIFT, 4
661 cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED
662 b.ne __no_granule_support
663 update_early_cpu_boot_status 0, x2, x3
664 adrp x2, idmap_pg_dir
667 msr ttbr0_el1, x2 // load TTBR0
669 msr ttbr1_el1, x1 // load TTBR1
675 SYM_FUNC_END(__enable_mmu)
677 SYM_FUNC_START(__cpu_secondary_check52bitva)
678 #ifdef CONFIG_ARM64_VA_BITS_52
679 ldr_l x0, vabits_actual
683 mrs_s x0, SYS_ID_AA64MMFR2_EL1
684 and x0, x0, #(0xf << ID_AA64MMFR2_LVA_SHIFT)
687 update_early_cpu_boot_status \
688 CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_52_BIT_VA, x0, x1
695 SYM_FUNC_END(__cpu_secondary_check52bitva)
697 SYM_FUNC_START_LOCAL(__no_granule_support)
698 /* Indicate that this CPU can't boot and is stuck in the kernel */
699 update_early_cpu_boot_status \
700 CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_NO_GRAN, x1, x2
705 SYM_FUNC_END(__no_granule_support)
707 #ifdef CONFIG_RELOCATABLE
708 SYM_FUNC_START_LOCAL(__relocate_kernel)
710 * Iterate over each entry in the relocation table, and apply the
711 * relocations in place.
713 ldr w9, =__rela_offset // offset to reloc table
714 ldr w10, =__rela_size // size of reloc table
716 mov_q x11, KIMAGE_VADDR // default virtual offset
717 add x11, x11, x23 // actual virtual offset
718 add x9, x9, x11 // __va(.rela)
719 add x10, x9, x10 // __va(.rela) + sizeof(.rela)
723 ldp x12, x13, [x9], #24
725 cmp w13, #R_AARCH64_RELATIVE
727 add x14, x14, x23 // relocate
734 * Apply RELR relocations.
736 * RELR is a compressed format for storing relative relocations. The
737 * encoded sequence of entries looks like:
738 * [ AAAAAAAA BBBBBBB1 BBBBBBB1 ... AAAAAAAA BBBBBB1 ... ]
740 * i.e. start with an address, followed by any number of bitmaps. The
741 * address entry encodes 1 relocation. The subsequent bitmap entries
742 * encode up to 63 relocations each, at subsequent offsets following
743 * the last address entry.
745 * The bitmap entries must have 1 in the least significant bit. The
746 * assumption here is that an address cannot have 1 in lsb. Odd
747 * addresses are not supported. Any odd addresses are stored in the RELA
748 * section, which is handled above.
750 * Excluding the least significant bit in the bitmap, each non-zero
751 * bit in the bitmap represents a relocation to be applied to
752 * a corresponding machine word that follows the base address
753 * word. The second least significant bit represents the machine
754 * word immediately following the initial address, and each bit
755 * that follows represents the next word, in linear order. As such,
756 * a single bitmap can encode up to 63 relocations in a 64-bit object.
758 * In this implementation we store the address of the next RELR table
759 * entry in x9, the address being relocated by the current address or
760 * bitmap entry in x13 and the address being relocated by the current
763 * Because addends are stored in place in the binary, RELR relocations
764 * cannot be applied idempotently. We use x24 to keep track of the
765 * currently applied displacement so that we can correctly relocate if
766 * __relocate_kernel is called twice with non-zero displacements (i.e.
767 * if there is both a physical misalignment and a KASLR displacement).
769 ldr w9, =__relr_offset // offset to reloc table
770 ldr w10, =__relr_size // size of reloc table
771 add x9, x9, x11 // __va(.relr)
772 add x10, x9, x10 // __va(.relr) + sizeof(.relr)
774 sub x15, x23, x24 // delta from previous offset
775 cbz x15, 7f // nothing to do if unchanged
776 mov x24, x23 // save new offset
781 tbnz x11, #0, 3f // branch to handle bitmaps
783 ldr x12, [x13] // relocate address entry
785 str x12, [x13], #8 // adjust to start of bitmap
791 tbz x11, #0, 5f // skip bit if not set
792 ldr x12, [x14] // relocate bit
796 5: add x14, x14, #8 // move to next bit's address
800 * Move to the next bitmap's address. 8 is the word size, and 63 is the
801 * number of significant bits in a bitmap entry.
803 add x13, x13, #(8 * 63)
810 SYM_FUNC_END(__relocate_kernel)
813 SYM_FUNC_START_LOCAL(__primary_switch)
814 #ifdef CONFIG_RANDOMIZE_BASE
815 mov x19, x0 // preserve new SCTLR_EL1 value
816 mrs x20, sctlr_el1 // preserve old SCTLR_EL1 value
821 #ifdef CONFIG_RELOCATABLE
823 mov x24, #0 // no RELR displacement yet
826 #ifdef CONFIG_RANDOMIZE_BASE
827 ldr x8, =__primary_switched
828 adrp x0, __PHYS_OFFSET
832 * If we return here, we have a KASLR displacement in x23 which we need
833 * to take into account by discarding the current kernel mapping and
834 * creating a new one.
836 pre_disable_mmu_workaround
837 msr sctlr_el1, x20 // disable the MMU
839 bl __create_page_tables // recreate kernel mapping
841 tlbi vmalle1 // Remove any stale TLB entries
844 set_sctlr_el1 x19 // re-enable the MMU
849 ldr x8, =__primary_switched
850 adrp x0, __PHYS_OFFSET
852 SYM_FUNC_END(__primary_switch)