1 // SPDX-License-Identifier: GPL-2.0-only
3 * FP/SIMD context switching and fault handling
5 * Copyright (C) 2012 ARM Ltd.
6 * Author: Catalin Marinas <catalin.marinas@arm.com>
9 #include <linux/bitmap.h>
10 #include <linux/bitops.h>
11 #include <linux/bottom_half.h>
12 #include <linux/bug.h>
13 #include <linux/cache.h>
14 #include <linux/compat.h>
15 #include <linux/compiler.h>
16 #include <linux/cpu.h>
17 #include <linux/cpu_pm.h>
18 #include <linux/ctype.h>
19 #include <linux/kernel.h>
20 #include <linux/linkage.h>
21 #include <linux/irqflags.h>
22 #include <linux/init.h>
23 #include <linux/percpu.h>
24 #include <linux/prctl.h>
25 #include <linux/preempt.h>
26 #include <linux/ptrace.h>
27 #include <linux/sched/signal.h>
28 #include <linux/sched/task_stack.h>
29 #include <linux/signal.h>
30 #include <linux/slab.h>
31 #include <linux/stddef.h>
32 #include <linux/sysctl.h>
33 #include <linux/swab.h>
36 #include <asm/exception.h>
37 #include <asm/fpsimd.h>
38 #include <asm/cpufeature.h>
39 #include <asm/cputype.h>
41 #include <asm/processor.h>
43 #include <asm/sigcontext.h>
44 #include <asm/sysreg.h>
45 #include <asm/traps.h>
48 #define FPEXC_IOF (1 << 0)
49 #define FPEXC_DZF (1 << 1)
50 #define FPEXC_OFF (1 << 2)
51 #define FPEXC_UFF (1 << 3)
52 #define FPEXC_IXF (1 << 4)
53 #define FPEXC_IDF (1 << 7)
56 * (Note: in this discussion, statements about FPSIMD apply equally to SVE.)
58 * In order to reduce the number of times the FPSIMD state is needlessly saved
59 * and restored, we need to keep track of two things:
60 * (a) for each task, we need to remember which CPU was the last one to have
61 * the task's FPSIMD state loaded into its FPSIMD registers;
62 * (b) for each CPU, we need to remember which task's userland FPSIMD state has
63 * been loaded into its FPSIMD registers most recently, or whether it has
64 * been used to perform kernel mode NEON in the meantime.
66 * For (a), we add a fpsimd_cpu field to thread_struct, which gets updated to
67 * the id of the current CPU every time the state is loaded onto a CPU. For (b),
68 * we add the per-cpu variable 'fpsimd_last_state' (below), which contains the
69 * address of the userland FPSIMD state of the task that was loaded onto the CPU
70 * the most recently, or NULL if kernel mode NEON has been performed after that.
72 * With this in place, we no longer have to restore the next FPSIMD state right
73 * when switching between tasks. Instead, we can defer this check to userland
74 * resume, at which time we verify whether the CPU's fpsimd_last_state and the
75 * task's fpsimd_cpu are still mutually in sync. If this is the case, we
76 * can omit the FPSIMD restore.
78 * As an optimization, we use the thread_info flag TIF_FOREIGN_FPSTATE to
79 * indicate whether or not the userland FPSIMD state of the current task is
80 * present in the registers. The flag is set unless the FPSIMD registers of this
81 * CPU currently contain the most recent userland FPSIMD state of the current
82 * task. If the task is behaving as a VMM, then this is will be managed by
83 * KVM which will clear it to indicate that the vcpu FPSIMD state is currently
84 * loaded on the CPU, allowing the state to be saved if a FPSIMD-aware
85 * softirq kicks in. Upon vcpu_put(), KVM will save the vcpu FP state and
86 * flag the register state as invalid.
88 * In order to allow softirq handlers to use FPSIMD, kernel_neon_begin() may
89 * save the task's FPSIMD context back to task_struct from softirq context.
90 * To prevent this from racing with the manipulation of the task's FPSIMD state
91 * from task context and thereby corrupting the state, it is necessary to
92 * protect any manipulation of a task's fpsimd_state or TIF_FOREIGN_FPSTATE
93 * flag with {, __}get_cpu_fpsimd_context(). This will still allow softirqs to
94 * run but prevent them to use FPSIMD.
96 * For a certain task, the sequence may look something like this:
97 * - the task gets scheduled in; if both the task's fpsimd_cpu field
98 * contains the id of the current CPU, and the CPU's fpsimd_last_state per-cpu
99 * variable points to the task's fpsimd_state, the TIF_FOREIGN_FPSTATE flag is
100 * cleared, otherwise it is set;
102 * - the task returns to userland; if TIF_FOREIGN_FPSTATE is set, the task's
103 * userland FPSIMD state is copied from memory to the registers, the task's
104 * fpsimd_cpu field is set to the id of the current CPU, the current
105 * CPU's fpsimd_last_state pointer is set to this task's fpsimd_state and the
106 * TIF_FOREIGN_FPSTATE flag is cleared;
108 * - the task executes an ordinary syscall; upon return to userland, the
109 * TIF_FOREIGN_FPSTATE flag will still be cleared, so no FPSIMD state is
112 * - the task executes a syscall which executes some NEON instructions; this is
113 * preceded by a call to kernel_neon_begin(), which copies the task's FPSIMD
114 * register contents to memory, clears the fpsimd_last_state per-cpu variable
115 * and sets the TIF_FOREIGN_FPSTATE flag;
117 * - the task gets preempted after kernel_neon_end() is called; as we have not
118 * returned from the 2nd syscall yet, TIF_FOREIGN_FPSTATE is still set so
119 * whatever is in the FPSIMD registers is not saved to memory, but discarded.
122 static DEFINE_PER_CPU(struct cpu_fp_state, fpsimd_last_state);
124 __ro_after_init struct vl_info vl_info[ARM64_VEC_MAX] = {
125 #ifdef CONFIG_ARM64_SVE
127 .type = ARM64_VEC_SVE,
129 .min_vl = SVE_VL_MIN,
130 .max_vl = SVE_VL_MIN,
131 .max_virtualisable_vl = SVE_VL_MIN,
134 #ifdef CONFIG_ARM64_SME
136 .type = ARM64_VEC_SME,
142 static unsigned int vec_vl_inherit_flag(enum vec_type type)
146 return TIF_SVE_VL_INHERIT;
148 return TIF_SME_VL_INHERIT;
156 int __default_vl; /* Default VL for tasks */
159 static struct vl_config vl_config[ARM64_VEC_MAX];
161 static inline int get_default_vl(enum vec_type type)
163 return READ_ONCE(vl_config[type].__default_vl);
166 #ifdef CONFIG_ARM64_SVE
168 static inline int get_sve_default_vl(void)
170 return get_default_vl(ARM64_VEC_SVE);
173 static inline void set_default_vl(enum vec_type type, int val)
175 WRITE_ONCE(vl_config[type].__default_vl, val);
178 static inline void set_sve_default_vl(int val)
180 set_default_vl(ARM64_VEC_SVE, val);
183 static void __percpu *efi_sve_state;
185 #else /* ! CONFIG_ARM64_SVE */
187 /* Dummy declaration for code that will be optimised out: */
188 extern void __percpu *efi_sve_state;
190 #endif /* ! CONFIG_ARM64_SVE */
192 #ifdef CONFIG_ARM64_SME
194 static int get_sme_default_vl(void)
196 return get_default_vl(ARM64_VEC_SME);
199 static void set_sme_default_vl(int val)
201 set_default_vl(ARM64_VEC_SME, val);
204 static void sme_free(struct task_struct *);
208 static inline void sme_free(struct task_struct *t) { }
212 DEFINE_PER_CPU(bool, fpsimd_context_busy);
213 EXPORT_PER_CPU_SYMBOL(fpsimd_context_busy);
215 static void fpsimd_bind_task_to_cpu(void);
217 static void __get_cpu_fpsimd_context(void)
219 bool busy = __this_cpu_xchg(fpsimd_context_busy, true);
225 * Claim ownership of the CPU FPSIMD context for use by the calling context.
227 * The caller may freely manipulate the FPSIMD context metadata until
228 * put_cpu_fpsimd_context() is called.
230 * The double-underscore version must only be called if you know the task
231 * can't be preempted.
233 * On RT kernels local_bh_disable() is not sufficient because it only
234 * serializes soft interrupt related sections via a local lock, but stays
235 * preemptible. Disabling preemption is the right choice here as bottom
236 * half processing is always in thread context on RT kernels so it
237 * implicitly prevents bottom half processing as well.
239 static void get_cpu_fpsimd_context(void)
241 if (!IS_ENABLED(CONFIG_PREEMPT_RT))
245 __get_cpu_fpsimd_context();
248 static void __put_cpu_fpsimd_context(void)
250 bool busy = __this_cpu_xchg(fpsimd_context_busy, false);
252 WARN_ON(!busy); /* No matching get_cpu_fpsimd_context()? */
256 * Release the CPU FPSIMD context.
258 * Must be called from a context in which get_cpu_fpsimd_context() was
259 * previously called, with no call to put_cpu_fpsimd_context() in the
262 static void put_cpu_fpsimd_context(void)
264 __put_cpu_fpsimd_context();
265 if (!IS_ENABLED(CONFIG_PREEMPT_RT))
271 static bool have_cpu_fpsimd_context(void)
273 return !preemptible() && __this_cpu_read(fpsimd_context_busy);
276 unsigned int task_get_vl(const struct task_struct *task, enum vec_type type)
278 return task->thread.vl[type];
281 void task_set_vl(struct task_struct *task, enum vec_type type,
284 task->thread.vl[type] = vl;
287 unsigned int task_get_vl_onexec(const struct task_struct *task,
290 return task->thread.vl_onexec[type];
293 void task_set_vl_onexec(struct task_struct *task, enum vec_type type,
296 task->thread.vl_onexec[type] = vl;
300 * TIF_SME controls whether a task can use SME without trapping while
301 * in userspace, when TIF_SME is set then we must have storage
302 * allocated in sve_state and sme_state to store the contents of both ZA
303 * and the SVE registers for both streaming and non-streaming modes.
305 * If both SVCR.ZA and SVCR.SM are disabled then at any point we
306 * may disable TIF_SME and reenable traps.
311 * TIF_SVE controls whether a task can use SVE without trapping while
312 * in userspace, and also (together with TIF_SME) the way a task's
313 * FPSIMD/SVE state is stored in thread_struct.
315 * The kernel uses this flag to track whether a user task is actively
316 * using SVE, and therefore whether full SVE register state needs to
317 * be tracked. If not, the cheaper FPSIMD context handling code can
318 * be used instead of the more costly SVE equivalents.
320 * * TIF_SVE or SVCR.SM set:
322 * The task can execute SVE instructions while in userspace without
323 * trapping to the kernel.
325 * During any syscall, the kernel may optionally clear TIF_SVE and
326 * discard the vector state except for the FPSIMD subset.
330 * An attempt by the user task to execute an SVE instruction causes
331 * do_sve_acc() to be called, which does some preparation and then
334 * During any syscall, the kernel may optionally clear TIF_SVE and
335 * discard the vector state except for the FPSIMD subset.
337 * The data will be stored in one of two formats:
339 * * FPSIMD only - FP_STATE_FPSIMD:
341 * When the FPSIMD only state stored task->thread.fp_type is set to
342 * FP_STATE_FPSIMD, the FPSIMD registers V0-V31 are encoded in
343 * task->thread.uw.fpsimd_state; bits [max : 128] for each of Z0-Z31 are
344 * logically zero but not stored anywhere; P0-P15 and FFR are not
345 * stored and have unspecified values from userspace's point of
346 * view. For hygiene purposes, the kernel zeroes them on next use,
347 * but userspace is discouraged from relying on this.
349 * task->thread.sve_state does not need to be non-NULL, valid or any
350 * particular size: it must not be dereferenced and any data stored
351 * there should be considered stale and not referenced.
353 * * SVE state - FP_STATE_SVE:
355 * When the full SVE state is stored task->thread.fp_type is set to
356 * FP_STATE_SVE and Z0-Z31 (incorporating Vn in bits[127:0] or the
357 * corresponding Zn), P0-P15 and FFR are encoded in in
358 * task->thread.sve_state, formatted appropriately for vector
359 * length task->thread.sve_vl or, if SVCR.SM is set,
360 * task->thread.sme_vl. The storage for the vector registers in
361 * task->thread.uw.fpsimd_state should be ignored.
363 * task->thread.sve_state must point to a valid buffer at least
364 * sve_state_size(task) bytes in size. The data stored in
365 * task->thread.uw.fpsimd_state.vregs should be considered stale
366 * and not referenced.
368 * * FPSR and FPCR are always stored in task->thread.uw.fpsimd_state
369 * irrespective of whether TIF_SVE is clear or set, since these are
370 * not vector length dependent.
374 * Update current's FPSIMD/SVE registers from thread_struct.
376 * This function should be called only when the FPSIMD/SVE state in
377 * thread_struct is known to be up to date, when preparing to enter
380 static void task_fpsimd_load(void)
382 bool restore_sve_regs = false;
385 WARN_ON(!system_supports_fpsimd());
386 WARN_ON(!have_cpu_fpsimd_context());
388 if (system_supports_sve() || system_supports_sme()) {
389 switch (current->thread.fp_type) {
390 case FP_STATE_FPSIMD:
391 /* Stop tracking SVE for this task until next use. */
392 if (test_and_clear_thread_flag(TIF_SVE))
396 if (!thread_sm_enabled(¤t->thread) &&
397 !WARN_ON_ONCE(!test_and_set_thread_flag(TIF_SVE)))
400 if (test_thread_flag(TIF_SVE))
401 sve_set_vq(sve_vq_from_vl(task_get_sve_vl(current)) - 1);
403 restore_sve_regs = true;
408 * This indicates either a bug in
409 * fpsimd_save() or memory corruption, we
410 * should always record an explicit format
411 * when we save. We always at least have the
412 * memory allocated for FPSMID registers so
413 * try that and hope for the best.
416 clear_thread_flag(TIF_SVE);
421 /* Restore SME, override SVE register configuration if needed */
422 if (system_supports_sme()) {
423 unsigned long sme_vl = task_get_sme_vl(current);
425 /* Ensure VL is set up for restoring data */
426 if (test_thread_flag(TIF_SME))
427 sme_set_vq(sve_vq_from_vl(sme_vl) - 1);
429 write_sysreg_s(current->thread.svcr, SYS_SVCR);
431 if (thread_za_enabled(¤t->thread))
432 sme_load_state(current->thread.sme_state,
433 system_supports_sme2());
435 if (thread_sm_enabled(¤t->thread))
436 restore_ffr = system_supports_fa64();
439 if (restore_sve_regs) {
440 WARN_ON_ONCE(current->thread.fp_type != FP_STATE_SVE);
441 sve_load_state(sve_pffr(¤t->thread),
442 ¤t->thread.uw.fpsimd_state.fpsr,
445 WARN_ON_ONCE(current->thread.fp_type != FP_STATE_FPSIMD);
446 fpsimd_load_state(¤t->thread.uw.fpsimd_state);
451 * Ensure FPSIMD/SVE storage in memory for the loaded context is up to
452 * date with respect to the CPU registers. Note carefully that the
453 * current context is the context last bound to the CPU stored in
454 * last, if KVM is involved this may be the guest VM context rather
455 * than the host thread for the VM pointed to by current. This means
456 * that we must always reference the state storage via last rather
457 * than via current, if we are saving KVM state then it will have
458 * ensured that the type of registers to save is set in last->to_save.
460 static void fpsimd_save(void)
462 struct cpu_fp_state const *last =
463 this_cpu_ptr(&fpsimd_last_state);
464 /* set by fpsimd_bind_task_to_cpu() or fpsimd_bind_state_to_cpu() */
465 bool save_sve_regs = false;
469 WARN_ON(!system_supports_fpsimd());
470 WARN_ON(!have_cpu_fpsimd_context());
472 if (test_thread_flag(TIF_FOREIGN_FPSTATE))
476 * If a task is in a syscall the ABI allows us to only
477 * preserve the state shared with FPSIMD so don't bother
478 * saving the full SVE state in that case.
480 if ((last->to_save == FP_STATE_CURRENT && test_thread_flag(TIF_SVE) &&
481 !in_syscall(current_pt_regs())) ||
482 last->to_save == FP_STATE_SVE) {
483 save_sve_regs = true;
488 if (system_supports_sme()) {
489 u64 *svcr = last->svcr;
491 *svcr = read_sysreg_s(SYS_SVCR);
493 if (*svcr & SVCR_ZA_MASK)
494 sme_save_state(last->sme_state,
495 system_supports_sme2());
497 /* If we are in streaming mode override regular SVE. */
498 if (*svcr & SVCR_SM_MASK) {
499 save_sve_regs = true;
500 save_ffr = system_supports_fa64();
505 if (IS_ENABLED(CONFIG_ARM64_SVE) && save_sve_regs) {
506 /* Get the configured VL from RDVL, will account for SM */
507 if (WARN_ON(sve_get_vl() != vl)) {
509 * Can't save the user regs, so current would
510 * re-enter user with corrupt state.
511 * There's no way to recover, so kill it:
513 force_signal_inject(SIGKILL, SI_KERNEL, 0, 0);
517 sve_save_state((char *)last->sve_state +
519 &last->st->fpsr, save_ffr);
520 *last->fp_type = FP_STATE_SVE;
522 fpsimd_save_state(last->st);
523 *last->fp_type = FP_STATE_FPSIMD;
528 * All vector length selection from userspace comes through here.
529 * We're on a slow path, so some sanity-checks are included.
530 * If things go wrong there's a bug somewhere, but try to fall back to a
533 static unsigned int find_supported_vector_length(enum vec_type type,
536 struct vl_info *info = &vl_info[type];
538 int max_vl = info->max_vl;
540 if (WARN_ON(!sve_vl_valid(vl)))
543 if (WARN_ON(!sve_vl_valid(max_vl)))
544 max_vl = info->min_vl;
548 if (vl < info->min_vl)
551 bit = find_next_bit(info->vq_map, SVE_VQ_MAX,
552 __vq_to_bit(sve_vq_from_vl(vl)));
553 return sve_vl_from_vq(__bit_to_vq(bit));
556 #if defined(CONFIG_ARM64_SVE) && defined(CONFIG_SYSCTL)
558 static int vec_proc_do_default_vl(struct ctl_table *table, int write,
559 void *buffer, size_t *lenp, loff_t *ppos)
561 struct vl_info *info = table->extra1;
562 enum vec_type type = info->type;
564 int vl = get_default_vl(type);
565 struct ctl_table tmp_table = {
567 .maxlen = sizeof(vl),
570 ret = proc_dointvec(&tmp_table, write, buffer, lenp, ppos);
574 /* Writing -1 has the special meaning "set to max": */
578 if (!sve_vl_valid(vl))
581 set_default_vl(type, find_supported_vector_length(type, vl));
585 static struct ctl_table sve_default_vl_table[] = {
587 .procname = "sve_default_vector_length",
589 .proc_handler = vec_proc_do_default_vl,
590 .extra1 = &vl_info[ARM64_VEC_SVE],
595 static int __init sve_sysctl_init(void)
597 if (system_supports_sve())
598 if (!register_sysctl("abi", sve_default_vl_table))
604 #else /* ! (CONFIG_ARM64_SVE && CONFIG_SYSCTL) */
605 static int __init sve_sysctl_init(void) { return 0; }
606 #endif /* ! (CONFIG_ARM64_SVE && CONFIG_SYSCTL) */
608 #if defined(CONFIG_ARM64_SME) && defined(CONFIG_SYSCTL)
609 static struct ctl_table sme_default_vl_table[] = {
611 .procname = "sme_default_vector_length",
613 .proc_handler = vec_proc_do_default_vl,
614 .extra1 = &vl_info[ARM64_VEC_SME],
619 static int __init sme_sysctl_init(void)
621 if (system_supports_sme())
622 if (!register_sysctl("abi", sme_default_vl_table))
628 #else /* ! (CONFIG_ARM64_SME && CONFIG_SYSCTL) */
629 static int __init sme_sysctl_init(void) { return 0; }
630 #endif /* ! (CONFIG_ARM64_SME && CONFIG_SYSCTL) */
632 #define ZREG(sve_state, vq, n) ((char *)(sve_state) + \
633 (SVE_SIG_ZREG_OFFSET(vq, n) - SVE_SIG_REGS_OFFSET))
635 #ifdef CONFIG_CPU_BIG_ENDIAN
636 static __uint128_t arm64_cpu_to_le128(__uint128_t x)
639 u64 b = swab64(x >> 64);
641 return ((__uint128_t)a << 64) | b;
644 static __uint128_t arm64_cpu_to_le128(__uint128_t x)
650 #define arm64_le128_to_cpu(x) arm64_cpu_to_le128(x)
652 static void __fpsimd_to_sve(void *sst, struct user_fpsimd_state const *fst,
658 for (i = 0; i < SVE_NUM_ZREGS; ++i) {
659 p = (__uint128_t *)ZREG(sst, vq, i);
660 *p = arm64_cpu_to_le128(fst->vregs[i]);
665 * Transfer the FPSIMD state in task->thread.uw.fpsimd_state to
666 * task->thread.sve_state.
668 * Task can be a non-runnable task, or current. In the latter case,
669 * the caller must have ownership of the cpu FPSIMD context before calling
671 * task->thread.sve_state must point to at least sve_state_size(task)
672 * bytes of allocated kernel memory.
673 * task->thread.uw.fpsimd_state must be up to date before calling this
676 static void fpsimd_to_sve(struct task_struct *task)
679 void *sst = task->thread.sve_state;
680 struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state;
682 if (!system_supports_sve() && !system_supports_sme())
685 vq = sve_vq_from_vl(thread_get_cur_vl(&task->thread));
686 __fpsimd_to_sve(sst, fst, vq);
690 * Transfer the SVE state in task->thread.sve_state to
691 * task->thread.uw.fpsimd_state.
693 * Task can be a non-runnable task, or current. In the latter case,
694 * the caller must have ownership of the cpu FPSIMD context before calling
696 * task->thread.sve_state must point to at least sve_state_size(task)
697 * bytes of allocated kernel memory.
698 * task->thread.sve_state must be up to date before calling this function.
700 static void sve_to_fpsimd(struct task_struct *task)
703 void const *sst = task->thread.sve_state;
704 struct user_fpsimd_state *fst = &task->thread.uw.fpsimd_state;
706 __uint128_t const *p;
708 if (!system_supports_sve() && !system_supports_sme())
711 vl = thread_get_cur_vl(&task->thread);
712 vq = sve_vq_from_vl(vl);
713 for (i = 0; i < SVE_NUM_ZREGS; ++i) {
714 p = (__uint128_t const *)ZREG(sst, vq, i);
715 fst->vregs[i] = arm64_le128_to_cpu(*p);
719 #ifdef CONFIG_ARM64_SVE
721 * Call __sve_free() directly only if you know task can't be scheduled
724 static void __sve_free(struct task_struct *task)
726 kfree(task->thread.sve_state);
727 task->thread.sve_state = NULL;
730 static void sve_free(struct task_struct *task)
732 WARN_ON(test_tsk_thread_flag(task, TIF_SVE));
738 * Return how many bytes of memory are required to store the full SVE
739 * state for task, given task's currently configured vector length.
741 size_t sve_state_size(struct task_struct const *task)
745 if (system_supports_sve())
746 vl = task_get_sve_vl(task);
747 if (system_supports_sme())
748 vl = max(vl, task_get_sme_vl(task));
750 return SVE_SIG_REGS_SIZE(sve_vq_from_vl(vl));
754 * Ensure that task->thread.sve_state is allocated and sufficiently large.
756 * This function should be used only in preparation for replacing
757 * task->thread.sve_state with new data. The memory is always zeroed
758 * here to prevent stale data from showing through: this is done in
759 * the interest of testability and predictability: except in the
760 * do_sve_acc() case, there is no ABI requirement to hide stale data
761 * written previously be task.
763 void sve_alloc(struct task_struct *task, bool flush)
765 if (task->thread.sve_state) {
767 memset(task->thread.sve_state, 0,
768 sve_state_size(task));
772 /* This is a small allocation (maximum ~8KB) and Should Not Fail. */
773 task->thread.sve_state =
774 kzalloc(sve_state_size(task), GFP_KERNEL);
779 * Force the FPSIMD state shared with SVE to be updated in the SVE state
780 * even if the SVE state is the current active state.
782 * This should only be called by ptrace. task must be non-runnable.
783 * task->thread.sve_state must point to at least sve_state_size(task)
784 * bytes of allocated kernel memory.
786 void fpsimd_force_sync_to_sve(struct task_struct *task)
792 * Ensure that task->thread.sve_state is up to date with respect to
793 * the user task, irrespective of when SVE is in use or not.
795 * This should only be called by ptrace. task must be non-runnable.
796 * task->thread.sve_state must point to at least sve_state_size(task)
797 * bytes of allocated kernel memory.
799 void fpsimd_sync_to_sve(struct task_struct *task)
801 if (!test_tsk_thread_flag(task, TIF_SVE) &&
802 !thread_sm_enabled(&task->thread))
807 * Ensure that task->thread.uw.fpsimd_state is up to date with respect to
808 * the user task, irrespective of whether SVE is in use or not.
810 * This should only be called by ptrace. task must be non-runnable.
811 * task->thread.sve_state must point to at least sve_state_size(task)
812 * bytes of allocated kernel memory.
814 void sve_sync_to_fpsimd(struct task_struct *task)
816 if (task->thread.fp_type == FP_STATE_SVE)
821 * Ensure that task->thread.sve_state is up to date with respect to
822 * the task->thread.uw.fpsimd_state.
824 * This should only be called by ptrace to merge new FPSIMD register
825 * values into a task for which SVE is currently active.
826 * task must be non-runnable.
827 * task->thread.sve_state must point to at least sve_state_size(task)
828 * bytes of allocated kernel memory.
829 * task->thread.uw.fpsimd_state must already have been initialised with
830 * the new FPSIMD register values to be merged in.
832 void sve_sync_from_fpsimd_zeropad(struct task_struct *task)
835 void *sst = task->thread.sve_state;
836 struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state;
838 if (!test_tsk_thread_flag(task, TIF_SVE) &&
839 !thread_sm_enabled(&task->thread))
842 vq = sve_vq_from_vl(thread_get_cur_vl(&task->thread));
844 memset(sst, 0, SVE_SIG_REGS_SIZE(vq));
845 __fpsimd_to_sve(sst, fst, vq);
848 int vec_set_vector_length(struct task_struct *task, enum vec_type type,
849 unsigned long vl, unsigned long flags)
851 bool free_sme = false;
853 if (flags & ~(unsigned long)(PR_SVE_VL_INHERIT |
854 PR_SVE_SET_VL_ONEXEC))
857 if (!sve_vl_valid(vl))
861 * Clamp to the maximum vector length that VL-agnostic code
862 * can work with. A flag may be assigned in the future to
863 * allow setting of larger vector lengths without confusing
866 if (vl > VL_ARCH_MAX)
869 vl = find_supported_vector_length(type, vl);
871 if (flags & (PR_SVE_VL_INHERIT |
872 PR_SVE_SET_VL_ONEXEC))
873 task_set_vl_onexec(task, type, vl);
875 /* Reset VL to system default on next exec: */
876 task_set_vl_onexec(task, type, 0);
878 /* Only actually set the VL if not deferred: */
879 if (flags & PR_SVE_SET_VL_ONEXEC)
882 if (vl == task_get_vl(task, type))
886 * To ensure the FPSIMD bits of the SVE vector registers are preserved,
887 * write any live register state back to task_struct, and convert to a
888 * regular FPSIMD thread.
890 if (task == current) {
891 get_cpu_fpsimd_context();
896 fpsimd_flush_task_state(task);
897 if (test_and_clear_tsk_thread_flag(task, TIF_SVE) ||
898 thread_sm_enabled(&task->thread)) {
900 task->thread.fp_type = FP_STATE_FPSIMD;
903 if (system_supports_sme()) {
904 if (type == ARM64_VEC_SME ||
905 !(task->thread.svcr & (SVCR_SM_MASK | SVCR_ZA_MASK))) {
907 * We are changing the SME VL or weren't using
908 * SME anyway, discard the state and force a
911 task->thread.svcr &= ~(SVCR_SM_MASK |
913 clear_tsk_thread_flag(task, TIF_SME);
919 put_cpu_fpsimd_context();
921 task_set_vl(task, type, vl);
924 * Free the changed states if they are not in use, SME will be
925 * reallocated to the correct size on next use and we just
926 * allocate SVE now in case it is needed for use in streaming
929 if (system_supports_sve()) {
931 sve_alloc(task, true);
938 update_tsk_thread_flag(task, vec_vl_inherit_flag(type),
939 flags & PR_SVE_VL_INHERIT);
945 * Encode the current vector length and flags for return.
946 * This is only required for prctl(): ptrace has separate fields.
947 * SVE and SME use the same bits for _ONEXEC and _INHERIT.
949 * flags are as for vec_set_vector_length().
951 static int vec_prctl_status(enum vec_type type, unsigned long flags)
955 if (flags & PR_SVE_SET_VL_ONEXEC)
956 ret = task_get_vl_onexec(current, type);
958 ret = task_get_vl(current, type);
960 if (test_thread_flag(vec_vl_inherit_flag(type)))
961 ret |= PR_SVE_VL_INHERIT;
967 int sve_set_current_vl(unsigned long arg)
969 unsigned long vl, flags;
972 vl = arg & PR_SVE_VL_LEN_MASK;
975 if (!system_supports_sve() || is_compat_task())
978 ret = vec_set_vector_length(current, ARM64_VEC_SVE, vl, flags);
982 return vec_prctl_status(ARM64_VEC_SVE, flags);
986 int sve_get_current_vl(void)
988 if (!system_supports_sve() || is_compat_task())
991 return vec_prctl_status(ARM64_VEC_SVE, 0);
994 #ifdef CONFIG_ARM64_SME
996 int sme_set_current_vl(unsigned long arg)
998 unsigned long vl, flags;
1001 vl = arg & PR_SME_VL_LEN_MASK;
1004 if (!system_supports_sme() || is_compat_task())
1007 ret = vec_set_vector_length(current, ARM64_VEC_SME, vl, flags);
1011 return vec_prctl_status(ARM64_VEC_SME, flags);
1015 int sme_get_current_vl(void)
1017 if (!system_supports_sme() || is_compat_task())
1020 return vec_prctl_status(ARM64_VEC_SME, 0);
1022 #endif /* CONFIG_ARM64_SME */
1024 static void vec_probe_vqs(struct vl_info *info,
1025 DECLARE_BITMAP(map, SVE_VQ_MAX))
1027 unsigned int vq, vl;
1029 bitmap_zero(map, SVE_VQ_MAX);
1031 for (vq = SVE_VQ_MAX; vq >= SVE_VQ_MIN; --vq) {
1032 write_vl(info->type, vq - 1); /* self-syncing */
1034 switch (info->type) {
1046 /* Minimum VL identified? */
1047 if (sve_vq_from_vl(vl) > vq)
1050 vq = sve_vq_from_vl(vl); /* skip intervening lengths */
1051 set_bit(__vq_to_bit(vq), map);
1056 * Initialise the set of known supported VQs for the boot CPU.
1057 * This is called during kernel boot, before secondary CPUs are brought up.
1059 void __init vec_init_vq_map(enum vec_type type)
1061 struct vl_info *info = &vl_info[type];
1062 vec_probe_vqs(info, info->vq_map);
1063 bitmap_copy(info->vq_partial_map, info->vq_map, SVE_VQ_MAX);
1067 * If we haven't committed to the set of supported VQs yet, filter out
1068 * those not supported by the current CPU.
1069 * This function is called during the bring-up of early secondary CPUs only.
1071 void vec_update_vq_map(enum vec_type type)
1073 struct vl_info *info = &vl_info[type];
1074 DECLARE_BITMAP(tmp_map, SVE_VQ_MAX);
1076 vec_probe_vqs(info, tmp_map);
1077 bitmap_and(info->vq_map, info->vq_map, tmp_map, SVE_VQ_MAX);
1078 bitmap_or(info->vq_partial_map, info->vq_partial_map, tmp_map,
1083 * Check whether the current CPU supports all VQs in the committed set.
1084 * This function is called during the bring-up of late secondary CPUs only.
1086 int vec_verify_vq_map(enum vec_type type)
1088 struct vl_info *info = &vl_info[type];
1089 DECLARE_BITMAP(tmp_map, SVE_VQ_MAX);
1092 vec_probe_vqs(info, tmp_map);
1094 bitmap_complement(tmp_map, tmp_map, SVE_VQ_MAX);
1095 if (bitmap_intersects(tmp_map, info->vq_map, SVE_VQ_MAX)) {
1096 pr_warn("%s: cpu%d: Required vector length(s) missing\n",
1097 info->name, smp_processor_id());
1101 if (!IS_ENABLED(CONFIG_KVM) || !is_hyp_mode_available())
1105 * For KVM, it is necessary to ensure that this CPU doesn't
1106 * support any vector length that guests may have probed as
1110 /* Recover the set of supported VQs: */
1111 bitmap_complement(tmp_map, tmp_map, SVE_VQ_MAX);
1112 /* Find VQs supported that are not globally supported: */
1113 bitmap_andnot(tmp_map, tmp_map, info->vq_map, SVE_VQ_MAX);
1115 /* Find the lowest such VQ, if any: */
1116 b = find_last_bit(tmp_map, SVE_VQ_MAX);
1117 if (b >= SVE_VQ_MAX)
1118 return 0; /* no mismatches */
1121 * Mismatches above sve_max_virtualisable_vl are fine, since
1122 * no guest is allowed to configure ZCR_EL2.LEN to exceed this:
1124 if (sve_vl_from_vq(__bit_to_vq(b)) <= info->max_virtualisable_vl) {
1125 pr_warn("%s: cpu%d: Unsupported vector length(s) present\n",
1126 info->name, smp_processor_id());
1133 static void __init sve_efi_setup(void)
1138 if (!IS_ENABLED(CONFIG_EFI))
1141 for (i = 0; i < ARRAY_SIZE(vl_info); i++)
1142 max_vl = max(vl_info[i].max_vl, max_vl);
1145 * alloc_percpu() warns and prints a backtrace if this goes wrong.
1146 * This is evidence of a crippled system and we are returning void,
1147 * so no attempt is made to handle this situation here.
1149 if (!sve_vl_valid(max_vl))
1152 efi_sve_state = __alloc_percpu(
1153 SVE_SIG_REGS_SIZE(sve_vq_from_vl(max_vl)), SVE_VQ_BYTES);
1160 panic("Cannot allocate percpu memory for EFI SVE save/restore");
1164 * Enable SVE for EL1.
1165 * Intended for use by the cpufeatures code during CPU boot.
1167 void sve_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p)
1169 write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_ZEN_EL1EN, CPACR_EL1);
1174 * Read the pseudo-ZCR used by cpufeatures to identify the supported SVE
1177 * Use only if SVE is present.
1178 * This function clobbers the SVE vector length.
1180 u64 read_zcr_features(void)
1183 unsigned int vq_max;
1186 * Set the maximum possible VL, and write zeroes to all other
1187 * bits to see if they stick.
1189 sve_kernel_enable(NULL);
1190 write_sysreg_s(ZCR_ELx_LEN_MASK, SYS_ZCR_EL1);
1192 zcr = read_sysreg_s(SYS_ZCR_EL1);
1193 zcr &= ~(u64)ZCR_ELx_LEN_MASK; /* find sticky 1s outside LEN field */
1194 vq_max = sve_vq_from_vl(sve_get_vl());
1195 zcr |= vq_max - 1; /* set LEN field to maximum effective value */
1200 void __init sve_setup(void)
1202 struct vl_info *info = &vl_info[ARM64_VEC_SVE];
1204 DECLARE_BITMAP(tmp_map, SVE_VQ_MAX);
1207 if (!system_supports_sve())
1211 * The SVE architecture mandates support for 128-bit vectors,
1212 * so sve_vq_map must have at least SVE_VQ_MIN set.
1213 * If something went wrong, at least try to patch it up:
1215 if (WARN_ON(!test_bit(__vq_to_bit(SVE_VQ_MIN), info->vq_map)))
1216 set_bit(__vq_to_bit(SVE_VQ_MIN), info->vq_map);
1218 zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
1219 info->max_vl = sve_vl_from_vq((zcr & ZCR_ELx_LEN_MASK) + 1);
1222 * Sanity-check that the max VL we determined through CPU features
1223 * corresponds properly to sve_vq_map. If not, do our best:
1225 if (WARN_ON(info->max_vl != find_supported_vector_length(ARM64_VEC_SVE,
1227 info->max_vl = find_supported_vector_length(ARM64_VEC_SVE,
1231 * For the default VL, pick the maximum supported value <= 64.
1232 * VL == 64 is guaranteed not to grow the signal frame.
1234 set_sve_default_vl(find_supported_vector_length(ARM64_VEC_SVE, 64));
1236 bitmap_andnot(tmp_map, info->vq_partial_map, info->vq_map,
1239 b = find_last_bit(tmp_map, SVE_VQ_MAX);
1240 if (b >= SVE_VQ_MAX)
1241 /* No non-virtualisable VLs found */
1242 info->max_virtualisable_vl = SVE_VQ_MAX;
1243 else if (WARN_ON(b == SVE_VQ_MAX - 1))
1244 /* No virtualisable VLs? This is architecturally forbidden. */
1245 info->max_virtualisable_vl = SVE_VQ_MIN;
1246 else /* b + 1 < SVE_VQ_MAX */
1247 info->max_virtualisable_vl = sve_vl_from_vq(__bit_to_vq(b + 1));
1249 if (info->max_virtualisable_vl > info->max_vl)
1250 info->max_virtualisable_vl = info->max_vl;
1252 pr_info("%s: maximum available vector length %u bytes per vector\n",
1253 info->name, info->max_vl);
1254 pr_info("%s: default vector length %u bytes per vector\n",
1255 info->name, get_sve_default_vl());
1257 /* KVM decides whether to support mismatched systems. Just warn here: */
1258 if (sve_max_virtualisable_vl() < sve_max_vl())
1259 pr_warn("%s: unvirtualisable vector lengths present\n",
1266 * Called from the put_task_struct() path, which cannot get here
1267 * unless dead_task is really dead and not schedulable.
1269 void fpsimd_release_task(struct task_struct *dead_task)
1271 __sve_free(dead_task);
1272 sme_free(dead_task);
1275 #endif /* CONFIG_ARM64_SVE */
1277 #ifdef CONFIG_ARM64_SME
1280 * Ensure that task->thread.sme_state is allocated and sufficiently large.
1282 * This function should be used only in preparation for replacing
1283 * task->thread.sme_state with new data. The memory is always zeroed
1284 * here to prevent stale data from showing through: this is done in
1285 * the interest of testability and predictability, the architecture
1286 * guarantees that when ZA is enabled it will be zeroed.
1288 void sme_alloc(struct task_struct *task, bool flush)
1290 if (task->thread.sme_state && flush) {
1291 memset(task->thread.sme_state, 0, sme_state_size(task));
1295 /* This could potentially be up to 64K. */
1296 task->thread.sme_state =
1297 kzalloc(sme_state_size(task), GFP_KERNEL);
1300 static void sme_free(struct task_struct *task)
1302 kfree(task->thread.sme_state);
1303 task->thread.sme_state = NULL;
1306 void sme_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p)
1308 /* Set priority for all PEs to architecturally defined minimum */
1309 write_sysreg_s(read_sysreg_s(SYS_SMPRI_EL1) & ~SMPRI_EL1_PRIORITY_MASK,
1312 /* Allow SME in kernel */
1313 write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_SMEN_EL1EN, CPACR_EL1);
1316 /* Allow EL0 to access TPIDR2 */
1317 write_sysreg(read_sysreg(SCTLR_EL1) | SCTLR_ELx_ENTP2, SCTLR_EL1);
1322 * This must be called after sme_kernel_enable(), we rely on the
1323 * feature table being sorted to ensure this.
1325 void sme2_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p)
1327 /* Allow use of ZT0 */
1328 write_sysreg_s(read_sysreg_s(SYS_SMCR_EL1) | SMCR_ELx_EZT0_MASK,
1333 * This must be called after sme_kernel_enable(), we rely on the
1334 * feature table being sorted to ensure this.
1336 void fa64_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p)
1338 /* Allow use of FA64 */
1339 write_sysreg_s(read_sysreg_s(SYS_SMCR_EL1) | SMCR_ELx_FA64_MASK,
1344 * Read the pseudo-SMCR used by cpufeatures to identify the supported
1347 * Use only if SME is present.
1348 * This function clobbers the SME vector length.
1350 u64 read_smcr_features(void)
1353 unsigned int vq_max;
1355 sme_kernel_enable(NULL);
1358 * Set the maximum possible VL.
1360 write_sysreg_s(read_sysreg_s(SYS_SMCR_EL1) | SMCR_ELx_LEN_MASK,
1363 smcr = read_sysreg_s(SYS_SMCR_EL1);
1364 smcr &= ~(u64)SMCR_ELx_LEN_MASK; /* Only the LEN field */
1365 vq_max = sve_vq_from_vl(sme_get_vl());
1366 smcr |= vq_max - 1; /* set LEN field to maximum effective value */
1371 void __init sme_setup(void)
1373 struct vl_info *info = &vl_info[ARM64_VEC_SME];
1377 if (!system_supports_sme())
1381 * SME doesn't require any particular vector length be
1382 * supported but it does require at least one. We should have
1383 * disabled the feature entirely while bringing up CPUs but
1384 * let's double check here.
1386 WARN_ON(bitmap_empty(info->vq_map, SVE_VQ_MAX));
1388 min_bit = find_last_bit(info->vq_map, SVE_VQ_MAX);
1389 info->min_vl = sve_vl_from_vq(__bit_to_vq(min_bit));
1391 smcr = read_sanitised_ftr_reg(SYS_SMCR_EL1);
1392 info->max_vl = sve_vl_from_vq((smcr & SMCR_ELx_LEN_MASK) + 1);
1395 * Sanity-check that the max VL we determined through CPU features
1396 * corresponds properly to sme_vq_map. If not, do our best:
1398 if (WARN_ON(info->max_vl != find_supported_vector_length(ARM64_VEC_SME,
1400 info->max_vl = find_supported_vector_length(ARM64_VEC_SME,
1403 WARN_ON(info->min_vl > info->max_vl);
1406 * For the default VL, pick the maximum supported value <= 32
1407 * (256 bits) if there is one since this is guaranteed not to
1408 * grow the signal frame when in streaming mode, otherwise the
1409 * minimum available VL will be used.
1411 set_sme_default_vl(find_supported_vector_length(ARM64_VEC_SME, 32));
1413 pr_info("SME: minimum available vector length %u bytes per vector\n",
1415 pr_info("SME: maximum available vector length %u bytes per vector\n",
1417 pr_info("SME: default vector length %u bytes per vector\n",
1418 get_sme_default_vl());
1421 #endif /* CONFIG_ARM64_SME */
1423 static void sve_init_regs(void)
1426 * Convert the FPSIMD state to SVE, zeroing all the state that
1427 * is not shared with FPSIMD. If (as is likely) the current
1428 * state is live in the registers then do this there and
1429 * update our metadata for the current task including
1430 * disabling the trap, otherwise update our in-memory copy.
1431 * We are guaranteed to not be in streaming mode, we can only
1432 * take a SVE trap when not in streaming mode and we can't be
1433 * in streaming mode when taking a SME trap.
1435 if (!test_thread_flag(TIF_FOREIGN_FPSTATE)) {
1436 unsigned long vq_minus_one =
1437 sve_vq_from_vl(task_get_sve_vl(current)) - 1;
1438 sve_set_vq(vq_minus_one);
1439 sve_flush_live(true, vq_minus_one);
1440 fpsimd_bind_task_to_cpu();
1442 fpsimd_to_sve(current);
1443 current->thread.fp_type = FP_STATE_SVE;
1448 * Trapped SVE access
1450 * Storage is allocated for the full SVE state, the current FPSIMD
1451 * register contents are migrated across, and the access trap is
1454 * TIF_SVE should be clear on entry: otherwise, fpsimd_restore_current_state()
1455 * would have disabled the SVE access trap for userspace during
1456 * ret_to_user, making an SVE access trap impossible in that case.
1458 void do_sve_acc(unsigned long esr, struct pt_regs *regs)
1460 /* Even if we chose not to use SVE, the hardware could still trap: */
1461 if (unlikely(!system_supports_sve()) || WARN_ON(is_compat_task())) {
1462 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
1466 sve_alloc(current, true);
1467 if (!current->thread.sve_state) {
1472 get_cpu_fpsimd_context();
1474 if (test_and_set_thread_flag(TIF_SVE))
1475 WARN_ON(1); /* SVE access shouldn't have trapped */
1478 * Even if the task can have used streaming mode we can only
1479 * generate SVE access traps in normal SVE mode and
1480 * transitioning out of streaming mode may discard any
1481 * streaming mode state. Always clear the high bits to avoid
1482 * any potential errors tracking what is properly initialised.
1486 put_cpu_fpsimd_context();
1490 * Trapped SME access
1492 * Storage is allocated for the full SVE and SME state, the current
1493 * FPSIMD register contents are migrated to SVE if SVE is not already
1494 * active, and the access trap is disabled.
1496 * TIF_SME should be clear on entry: otherwise, fpsimd_restore_current_state()
1497 * would have disabled the SME access trap for userspace during
1498 * ret_to_user, making an SME access trap impossible in that case.
1500 void do_sme_acc(unsigned long esr, struct pt_regs *regs)
1502 /* Even if we chose not to use SME, the hardware could still trap: */
1503 if (unlikely(!system_supports_sme()) || WARN_ON(is_compat_task())) {
1504 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
1509 * If this not a trap due to SME being disabled then something
1510 * is being used in the wrong mode, report as SIGILL.
1512 if (ESR_ELx_ISS(esr) != ESR_ELx_SME_ISS_SME_DISABLED) {
1513 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
1517 sve_alloc(current, false);
1518 sme_alloc(current, true);
1519 if (!current->thread.sve_state || !current->thread.sme_state) {
1524 get_cpu_fpsimd_context();
1526 /* With TIF_SME userspace shouldn't generate any traps */
1527 if (test_and_set_thread_flag(TIF_SME))
1530 if (!test_thread_flag(TIF_FOREIGN_FPSTATE)) {
1531 unsigned long vq_minus_one =
1532 sve_vq_from_vl(task_get_sme_vl(current)) - 1;
1533 sme_set_vq(vq_minus_one);
1535 fpsimd_bind_task_to_cpu();
1538 put_cpu_fpsimd_context();
1542 * Trapped FP/ASIMD access.
1544 void do_fpsimd_acc(unsigned long esr, struct pt_regs *regs)
1546 /* TODO: implement lazy context saving/restoring */
1551 * Raise a SIGFPE for the current process.
1553 void do_fpsimd_exc(unsigned long esr, struct pt_regs *regs)
1555 unsigned int si_code = FPE_FLTUNK;
1557 if (esr & ESR_ELx_FP_EXC_TFV) {
1558 if (esr & FPEXC_IOF)
1559 si_code = FPE_FLTINV;
1560 else if (esr & FPEXC_DZF)
1561 si_code = FPE_FLTDIV;
1562 else if (esr & FPEXC_OFF)
1563 si_code = FPE_FLTOVF;
1564 else if (esr & FPEXC_UFF)
1565 si_code = FPE_FLTUND;
1566 else if (esr & FPEXC_IXF)
1567 si_code = FPE_FLTRES;
1570 send_sig_fault(SIGFPE, si_code,
1571 (void __user *)instruction_pointer(regs),
1575 void fpsimd_thread_switch(struct task_struct *next)
1577 bool wrong_task, wrong_cpu;
1579 if (!system_supports_fpsimd())
1582 __get_cpu_fpsimd_context();
1584 /* Save unsaved fpsimd state, if any: */
1588 * Fix up TIF_FOREIGN_FPSTATE to correctly describe next's
1589 * state. For kernel threads, FPSIMD registers are never loaded
1590 * and wrong_task and wrong_cpu will always be true.
1592 wrong_task = __this_cpu_read(fpsimd_last_state.st) !=
1593 &next->thread.uw.fpsimd_state;
1594 wrong_cpu = next->thread.fpsimd_cpu != smp_processor_id();
1596 update_tsk_thread_flag(next, TIF_FOREIGN_FPSTATE,
1597 wrong_task || wrong_cpu);
1599 __put_cpu_fpsimd_context();
1602 static void fpsimd_flush_thread_vl(enum vec_type type)
1604 int vl, supported_vl;
1607 * Reset the task vector length as required. This is where we
1608 * ensure that all user tasks have a valid vector length
1609 * configured: no kernel task can become a user task without
1610 * an exec and hence a call to this function. By the time the
1611 * first call to this function is made, all early hardware
1612 * probing is complete, so __sve_default_vl should be valid.
1613 * If a bug causes this to go wrong, we make some noise and
1614 * try to fudge thread.sve_vl to a safe value here.
1616 vl = task_get_vl_onexec(current, type);
1618 vl = get_default_vl(type);
1620 if (WARN_ON(!sve_vl_valid(vl)))
1621 vl = vl_info[type].min_vl;
1623 supported_vl = find_supported_vector_length(type, vl);
1624 if (WARN_ON(supported_vl != vl))
1627 task_set_vl(current, type, vl);
1630 * If the task is not set to inherit, ensure that the vector
1631 * length will be reset by a subsequent exec:
1633 if (!test_thread_flag(vec_vl_inherit_flag(type)))
1634 task_set_vl_onexec(current, type, 0);
1637 void fpsimd_flush_thread(void)
1639 void *sve_state = NULL;
1640 void *sme_state = NULL;
1642 if (!system_supports_fpsimd())
1645 get_cpu_fpsimd_context();
1647 fpsimd_flush_task_state(current);
1648 memset(¤t->thread.uw.fpsimd_state, 0,
1649 sizeof(current->thread.uw.fpsimd_state));
1651 if (system_supports_sve()) {
1652 clear_thread_flag(TIF_SVE);
1654 /* Defer kfree() while in atomic context */
1655 sve_state = current->thread.sve_state;
1656 current->thread.sve_state = NULL;
1658 fpsimd_flush_thread_vl(ARM64_VEC_SVE);
1661 if (system_supports_sme()) {
1662 clear_thread_flag(TIF_SME);
1664 /* Defer kfree() while in atomic context */
1665 sme_state = current->thread.sme_state;
1666 current->thread.sme_state = NULL;
1668 fpsimd_flush_thread_vl(ARM64_VEC_SME);
1669 current->thread.svcr = 0;
1672 current->thread.fp_type = FP_STATE_FPSIMD;
1674 put_cpu_fpsimd_context();
1680 * Save the userland FPSIMD state of 'current' to memory, but only if the state
1681 * currently held in the registers does in fact belong to 'current'
1683 void fpsimd_preserve_current_state(void)
1685 if (!system_supports_fpsimd())
1688 get_cpu_fpsimd_context();
1690 put_cpu_fpsimd_context();
1694 * Like fpsimd_preserve_current_state(), but ensure that
1695 * current->thread.uw.fpsimd_state is updated so that it can be copied to
1698 void fpsimd_signal_preserve_current_state(void)
1700 fpsimd_preserve_current_state();
1701 if (test_thread_flag(TIF_SVE))
1702 sve_to_fpsimd(current);
1706 * Called by KVM when entering the guest.
1708 void fpsimd_kvm_prepare(void)
1710 if (!system_supports_sve())
1714 * KVM does not save host SVE state since we can only enter
1715 * the guest from a syscall so the ABI means that only the
1716 * non-saved SVE state needs to be saved. If we have left
1717 * SVE enabled for performance reasons then update the task
1718 * state to be FPSIMD only.
1720 get_cpu_fpsimd_context();
1722 if (test_and_clear_thread_flag(TIF_SVE)) {
1723 sve_to_fpsimd(current);
1724 current->thread.fp_type = FP_STATE_FPSIMD;
1727 put_cpu_fpsimd_context();
1731 * Associate current's FPSIMD context with this cpu
1732 * The caller must have ownership of the cpu FPSIMD context before calling
1735 static void fpsimd_bind_task_to_cpu(void)
1737 struct cpu_fp_state *last = this_cpu_ptr(&fpsimd_last_state);
1739 WARN_ON(!system_supports_fpsimd());
1740 last->st = ¤t->thread.uw.fpsimd_state;
1741 last->sve_state = current->thread.sve_state;
1742 last->sme_state = current->thread.sme_state;
1743 last->sve_vl = task_get_sve_vl(current);
1744 last->sme_vl = task_get_sme_vl(current);
1745 last->svcr = ¤t->thread.svcr;
1746 last->fp_type = ¤t->thread.fp_type;
1747 last->to_save = FP_STATE_CURRENT;
1748 current->thread.fpsimd_cpu = smp_processor_id();
1751 * Toggle SVE and SME trapping for userspace if needed, these
1752 * are serialsied by ret_to_user().
1754 if (system_supports_sme()) {
1755 if (test_thread_flag(TIF_SME))
1761 if (system_supports_sve()) {
1762 if (test_thread_flag(TIF_SVE))
1769 void fpsimd_bind_state_to_cpu(struct cpu_fp_state *state)
1771 struct cpu_fp_state *last = this_cpu_ptr(&fpsimd_last_state);
1773 WARN_ON(!system_supports_fpsimd());
1774 WARN_ON(!in_softirq() && !irqs_disabled());
1780 * Load the userland FPSIMD state of 'current' from memory, but only if the
1781 * FPSIMD state already held in the registers is /not/ the most recent FPSIMD
1782 * state of 'current'. This is called when we are preparing to return to
1783 * userspace to ensure that userspace sees a good register state.
1785 void fpsimd_restore_current_state(void)
1788 * For the tasks that were created before we detected the absence of
1789 * FP/SIMD, the TIF_FOREIGN_FPSTATE could be set via fpsimd_thread_switch(),
1790 * e.g, init. This could be then inherited by the children processes.
1791 * If we later detect that the system doesn't support FP/SIMD,
1792 * we must clear the flag for all the tasks to indicate that the
1793 * FPSTATE is clean (as we can't have one) to avoid looping for ever in
1794 * do_notify_resume().
1796 if (!system_supports_fpsimd()) {
1797 clear_thread_flag(TIF_FOREIGN_FPSTATE);
1801 get_cpu_fpsimd_context();
1803 if (test_and_clear_thread_flag(TIF_FOREIGN_FPSTATE)) {
1805 fpsimd_bind_task_to_cpu();
1808 put_cpu_fpsimd_context();
1812 * Load an updated userland FPSIMD state for 'current' from memory and set the
1813 * flag that indicates that the FPSIMD register contents are the most recent
1814 * FPSIMD state of 'current'. This is used by the signal code to restore the
1815 * register state when returning from a signal handler in FPSIMD only cases,
1816 * any SVE context will be discarded.
1818 void fpsimd_update_current_state(struct user_fpsimd_state const *state)
1820 if (WARN_ON(!system_supports_fpsimd()))
1823 get_cpu_fpsimd_context();
1825 current->thread.uw.fpsimd_state = *state;
1826 if (test_thread_flag(TIF_SVE))
1827 fpsimd_to_sve(current);
1830 fpsimd_bind_task_to_cpu();
1832 clear_thread_flag(TIF_FOREIGN_FPSTATE);
1834 put_cpu_fpsimd_context();
1838 * Invalidate live CPU copies of task t's FPSIMD state
1840 * This function may be called with preemption enabled. The barrier()
1841 * ensures that the assignment to fpsimd_cpu is visible to any
1842 * preemption/softirq that could race with set_tsk_thread_flag(), so
1843 * that TIF_FOREIGN_FPSTATE cannot be spuriously re-cleared.
1845 * The final barrier ensures that TIF_FOREIGN_FPSTATE is seen set by any
1848 void fpsimd_flush_task_state(struct task_struct *t)
1850 t->thread.fpsimd_cpu = NR_CPUS;
1852 * If we don't support fpsimd, bail out after we have
1853 * reset the fpsimd_cpu for this task and clear the
1856 if (!system_supports_fpsimd())
1859 set_tsk_thread_flag(t, TIF_FOREIGN_FPSTATE);
1865 * Invalidate any task's FPSIMD state that is present on this cpu.
1866 * The FPSIMD context should be acquired with get_cpu_fpsimd_context()
1867 * before calling this function.
1869 static void fpsimd_flush_cpu_state(void)
1871 WARN_ON(!system_supports_fpsimd());
1872 __this_cpu_write(fpsimd_last_state.st, NULL);
1875 * Leaving streaming mode enabled will cause issues for any kernel
1876 * NEON and leaving streaming mode or ZA enabled may increase power
1879 if (system_supports_sme())
1882 set_thread_flag(TIF_FOREIGN_FPSTATE);
1886 * Save the FPSIMD state to memory and invalidate cpu view.
1887 * This function must be called with preemption disabled.
1889 void fpsimd_save_and_flush_cpu_state(void)
1891 if (!system_supports_fpsimd())
1893 WARN_ON(preemptible());
1894 __get_cpu_fpsimd_context();
1896 fpsimd_flush_cpu_state();
1897 __put_cpu_fpsimd_context();
1900 #ifdef CONFIG_KERNEL_MODE_NEON
1903 * Kernel-side NEON support functions
1907 * kernel_neon_begin(): obtain the CPU FPSIMD registers for use by the calling
1910 * Must not be called unless may_use_simd() returns true.
1911 * Task context in the FPSIMD registers is saved back to memory as necessary.
1913 * A matching call to kernel_neon_end() must be made before returning from the
1916 * The caller may freely use the FPSIMD registers until kernel_neon_end() is
1919 void kernel_neon_begin(void)
1921 if (WARN_ON(!system_supports_fpsimd()))
1924 BUG_ON(!may_use_simd());
1926 get_cpu_fpsimd_context();
1928 /* Save unsaved fpsimd state, if any: */
1931 /* Invalidate any task state remaining in the fpsimd regs: */
1932 fpsimd_flush_cpu_state();
1934 EXPORT_SYMBOL_GPL(kernel_neon_begin);
1937 * kernel_neon_end(): give the CPU FPSIMD registers back to the current task
1939 * Must be called from a context in which kernel_neon_begin() was previously
1940 * called, with no call to kernel_neon_end() in the meantime.
1942 * The caller must not use the FPSIMD registers after this function is called,
1943 * unless kernel_neon_begin() is called again in the meantime.
1945 void kernel_neon_end(void)
1947 if (!system_supports_fpsimd())
1950 put_cpu_fpsimd_context();
1952 EXPORT_SYMBOL_GPL(kernel_neon_end);
1956 static DEFINE_PER_CPU(struct user_fpsimd_state, efi_fpsimd_state);
1957 static DEFINE_PER_CPU(bool, efi_fpsimd_state_used);
1958 static DEFINE_PER_CPU(bool, efi_sve_state_used);
1959 static DEFINE_PER_CPU(bool, efi_sm_state);
1962 * EFI runtime services support functions
1964 * The ABI for EFI runtime services allows EFI to use FPSIMD during the call.
1965 * This means that for EFI (and only for EFI), we have to assume that FPSIMD
1966 * is always used rather than being an optional accelerator.
1968 * These functions provide the necessary support for ensuring FPSIMD
1969 * save/restore in the contexts from which EFI is used.
1971 * Do not use them for any other purpose -- if tempted to do so, you are
1972 * either doing something wrong or you need to propose some refactoring.
1976 * __efi_fpsimd_begin(): prepare FPSIMD for making an EFI runtime services call
1978 void __efi_fpsimd_begin(void)
1980 if (!system_supports_fpsimd())
1983 WARN_ON(preemptible());
1985 if (may_use_simd()) {
1986 kernel_neon_begin();
1989 * If !efi_sve_state, SVE can't be in use yet and doesn't need
1992 if (system_supports_sve() && likely(efi_sve_state)) {
1993 char *sve_state = this_cpu_ptr(efi_sve_state);
1997 __this_cpu_write(efi_sve_state_used, true);
1999 if (system_supports_sme()) {
2000 svcr = read_sysreg_s(SYS_SVCR);
2002 __this_cpu_write(efi_sm_state,
2003 svcr & SVCR_SM_MASK);
2006 * Unless we have FA64 FFR does not
2007 * exist in streaming mode.
2009 if (!system_supports_fa64())
2010 ffr = !(svcr & SVCR_SM_MASK);
2013 sve_save_state(sve_state + sve_ffr_offset(sve_max_vl()),
2014 &this_cpu_ptr(&efi_fpsimd_state)->fpsr,
2017 if (system_supports_sme())
2018 sysreg_clear_set_s(SYS_SVCR,
2022 fpsimd_save_state(this_cpu_ptr(&efi_fpsimd_state));
2025 __this_cpu_write(efi_fpsimd_state_used, true);
2030 * __efi_fpsimd_end(): clean up FPSIMD after an EFI runtime services call
2032 void __efi_fpsimd_end(void)
2034 if (!system_supports_fpsimd())
2037 if (!__this_cpu_xchg(efi_fpsimd_state_used, false)) {
2040 if (system_supports_sve() &&
2041 likely(__this_cpu_read(efi_sve_state_used))) {
2042 char const *sve_state = this_cpu_ptr(efi_sve_state);
2046 * Restore streaming mode; EFI calls are
2047 * normal function calls so should not return in
2050 if (system_supports_sme()) {
2051 if (__this_cpu_read(efi_sm_state)) {
2052 sysreg_clear_set_s(SYS_SVCR,
2057 * Unless we have FA64 FFR does not
2058 * exist in streaming mode.
2060 if (!system_supports_fa64())
2065 sve_load_state(sve_state + sve_ffr_offset(sve_max_vl()),
2066 &this_cpu_ptr(&efi_fpsimd_state)->fpsr,
2069 __this_cpu_write(efi_sve_state_used, false);
2071 fpsimd_load_state(this_cpu_ptr(&efi_fpsimd_state));
2076 #endif /* CONFIG_EFI */
2078 #endif /* CONFIG_KERNEL_MODE_NEON */
2080 #ifdef CONFIG_CPU_PM
2081 static int fpsimd_cpu_pm_notifier(struct notifier_block *self,
2082 unsigned long cmd, void *v)
2086 fpsimd_save_and_flush_cpu_state();
2090 case CPU_PM_ENTER_FAILED:
2097 static struct notifier_block fpsimd_cpu_pm_notifier_block = {
2098 .notifier_call = fpsimd_cpu_pm_notifier,
2101 static void __init fpsimd_pm_init(void)
2103 cpu_pm_register_notifier(&fpsimd_cpu_pm_notifier_block);
2107 static inline void fpsimd_pm_init(void) { }
2108 #endif /* CONFIG_CPU_PM */
2110 #ifdef CONFIG_HOTPLUG_CPU
2111 static int fpsimd_cpu_dead(unsigned int cpu)
2113 per_cpu(fpsimd_last_state.st, cpu) = NULL;
2117 static inline void fpsimd_hotplug_init(void)
2119 cpuhp_setup_state_nocalls(CPUHP_ARM64_FPSIMD_DEAD, "arm64/fpsimd:dead",
2120 NULL, fpsimd_cpu_dead);
2124 static inline void fpsimd_hotplug_init(void) { }
2128 * FP/SIMD support code initialisation.
2130 static int __init fpsimd_init(void)
2132 if (cpu_have_named_feature(FP)) {
2134 fpsimd_hotplug_init();
2136 pr_notice("Floating-point is not implemented\n");
2139 if (!cpu_have_named_feature(ASIMD))
2140 pr_notice("Advanced SIMD is not implemented\n");
2148 core_initcall(fpsimd_init);