1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Low-level exception handling code
5 * Copyright (C) 2012 ARM Ltd.
6 * Authors: Catalin Marinas <catalin.marinas@arm.com>
7 * Will Deacon <will.deacon@arm.com>
10 #include <linux/arm-smccc.h>
11 #include <linux/init.h>
12 #include <linux/linkage.h>
14 #include <asm/alternative.h>
15 #include <asm/assembler.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/asm_pointer_auth.h>
19 #include <asm/cpufeature.h>
20 #include <asm/errno.h>
23 #include <asm/memory.h>
25 #include <asm/processor.h>
26 #include <asm/ptrace.h>
28 #include <asm/thread_info.h>
29 #include <asm/asm-uaccess.h>
30 #include <asm/unistd.h>
33 * Context tracking subsystem. Used to instrument transitions
34 * between user and kernel mode.
36 .macro ct_user_exit_irqoff
37 #ifdef CONFIG_CONTEXT_TRACKING
38 bl enter_from_user_mode
43 #ifdef CONFIG_CONTEXT_TRACKING
44 bl context_tracking_user_enter
49 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
63 .macro kernel_ventry, el, label, regsize = 64
65 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
67 alternative_if ARM64_UNMAP_KERNEL_AT_EL0
74 alternative_else_nop_endif
78 sub sp, sp, #S_FRAME_SIZE
79 #ifdef CONFIG_VMAP_STACK
81 * Test whether the SP has overflowed, without corrupting a GPR.
82 * Task and IRQ stacks are aligned so that SP & (1 << THREAD_SHIFT)
83 * should always be zero.
85 add sp, sp, x0 // sp' = sp + x0
86 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp
87 tbnz x0, #THREAD_SHIFT, 0f
88 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0
89 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp
94 * Either we've just detected an overflow, or we've taken an exception
95 * while on the overflow stack. Either way, we won't return to
96 * userspace, and can clobber EL0 registers to free up GPRs.
99 /* Stash the original SP (minus S_FRAME_SIZE) in tpidr_el0. */
102 /* Recover the original x0 value and stash it in tpidrro_el0 */
106 /* Switch to the overflow stack */
107 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0
110 * Check whether we were already on the overflow stack. This may happen
111 * after panic() re-enables interrupts.
113 mrs x0, tpidr_el0 // sp of interrupted context
114 sub x0, sp, x0 // delta with top of overflow stack
115 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range?
116 b.ne __bad_stack // no? -> bad stack pointer
118 /* We were already on the overflow stack. Restore sp/x0 and carry on. */
125 .macro tramp_alias, dst, sym
126 mov_q \dst, TRAMP_VALIAS
127 add \dst, \dst, #(\sym - .entry.tramp.text)
130 // This macro corrupts x0-x3. It is the caller's duty
131 // to save/restore them if required.
132 .macro apply_ssbd, state, tmp1, tmp2
133 #ifdef CONFIG_ARM64_SSBD
134 alternative_cb arm64_enable_wa2_handling
135 b .L__asm_ssbd_skip\@
137 ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1
138 cbz \tmp2, .L__asm_ssbd_skip\@
139 ldr \tmp2, [tsk, #TSK_TI_FLAGS]
140 tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@
141 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2
143 alternative_cb arm64_update_smccc_conduit
144 nop // Patched to SMC/HVC #0
150 .macro kernel_entry, el, regsize = 64
152 mov w0, w0 // zero upper 32 bits of x0
154 stp x0, x1, [sp, #16 * 0]
155 stp x2, x3, [sp, #16 * 1]
156 stp x4, x5, [sp, #16 * 2]
157 stp x6, x7, [sp, #16 * 3]
158 stp x8, x9, [sp, #16 * 4]
159 stp x10, x11, [sp, #16 * 5]
160 stp x12, x13, [sp, #16 * 6]
161 stp x14, x15, [sp, #16 * 7]
162 stp x16, x17, [sp, #16 * 8]
163 stp x18, x19, [sp, #16 * 9]
164 stp x20, x21, [sp, #16 * 10]
165 stp x22, x23, [sp, #16 * 11]
166 stp x24, x25, [sp, #16 * 12]
167 stp x26, x27, [sp, #16 * 13]
168 stp x28, x29, [sp, #16 * 14]
173 ldr_this_cpu tsk, __entry_task, x20
176 // Ensure MDSCR_EL1.SS is clear, since we can unmask debug exceptions
178 ldr x19, [tsk, #TSK_TI_FLAGS]
179 disable_step_tsk x19, x20
181 apply_ssbd 1, x22, x23
183 ptrauth_keys_install_kernel tsk, x20, x22, x23
187 add x21, sp, #S_FRAME_SIZE
189 /* Save the task's original addr_limit and set USER_DS */
190 ldr x20, [tsk, #TSK_TI_ADDR_LIMIT]
191 str x20, [sp, #S_ORIG_ADDR_LIMIT]
193 str x20, [tsk, #TSK_TI_ADDR_LIMIT]
194 /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */
195 .endif /* \el == 0 */
198 stp lr, x21, [sp, #S_LR]
201 * In order to be able to dump the contents of struct pt_regs at the
202 * time the exception was taken (in case we attempt to walk the call
203 * stack later), chain it together with the stack frames.
206 stp xzr, xzr, [sp, #S_STACKFRAME]
208 stp x29, x22, [sp, #S_STACKFRAME]
210 add x29, sp, #S_STACKFRAME
212 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
213 alternative_if_not ARM64_HAS_PAN
214 bl __swpan_entry_el\el
215 alternative_else_nop_endif
218 stp x22, x23, [sp, #S_PC]
220 /* Not in a syscall by default (el0_svc overwrites for real syscall) */
223 str w21, [sp, #S_SYSCALLNO]
227 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
228 mrs_s x20, SYS_ICC_PMR_EL1
229 str x20, [sp, #S_PMR_SAVE]
230 alternative_else_nop_endif
233 * Registers that may be useful after this macro is invoked:
238 * x23 - aborted PSTATE
242 .macro kernel_exit, el
246 /* Restore the task's original addr_limit. */
247 ldr x20, [sp, #S_ORIG_ADDR_LIMIT]
248 str x20, [tsk, #TSK_TI_ADDR_LIMIT]
250 /* No need to restore UAO, it will be restored from SPSR_EL1 */
254 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
255 ldr x20, [sp, #S_PMR_SAVE]
256 msr_s SYS_ICC_PMR_EL1, x20
257 mrs_s x21, SYS_ICC_CTLR_EL1
258 tbz x21, #6, .L__skip_pmr_sync\@ // Check for ICC_CTLR_EL1.PMHE
259 dsb sy // Ensure priority change is seen by redistributor
261 alternative_else_nop_endif
263 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
268 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
269 alternative_if_not ARM64_HAS_PAN
270 bl __swpan_exit_el\el
271 alternative_else_nop_endif
275 ldr x23, [sp, #S_SP] // load return stack pointer
277 tst x22, #PSR_MODE32_BIT // native task?
280 #ifdef CONFIG_ARM64_ERRATUM_845719
281 alternative_if ARM64_WORKAROUND_845719
282 #ifdef CONFIG_PID_IN_CONTEXTIDR
283 mrs x29, contextidr_el1
284 msr contextidr_el1, x29
286 msr contextidr_el1, xzr
288 alternative_else_nop_endif
291 #ifdef CONFIG_ARM64_ERRATUM_1418040
292 alternative_if_not ARM64_WORKAROUND_1418040
294 alternative_else_nop_endif
296 * if (x22.mode32 == cntkctl_el1.el0vcten)
297 * cntkctl_el1.el0vcten = ~cntkctl_el1.el0vcten
300 eon x0, x1, x22, lsr #3
302 eor x1, x1, #2 // ARCH_TIMER_USR_VCT_ACCESS_EN
308 /* No kernel C function calls after this as user keys are set. */
309 ptrauth_keys_install_user tsk, x0, x1, x2
314 msr elr_el1, x21 // set up the return data
316 ldp x0, x1, [sp, #16 * 0]
317 ldp x2, x3, [sp, #16 * 1]
318 ldp x4, x5, [sp, #16 * 2]
319 ldp x6, x7, [sp, #16 * 3]
320 ldp x8, x9, [sp, #16 * 4]
321 ldp x10, x11, [sp, #16 * 5]
322 ldp x12, x13, [sp, #16 * 6]
323 ldp x14, x15, [sp, #16 * 7]
324 ldp x16, x17, [sp, #16 * 8]
325 ldp x18, x19, [sp, #16 * 9]
326 ldp x20, x21, [sp, #16 * 10]
327 ldp x22, x23, [sp, #16 * 11]
328 ldp x24, x25, [sp, #16 * 12]
329 ldp x26, x27, [sp, #16 * 13]
330 ldp x28, x29, [sp, #16 * 14]
332 add sp, sp, #S_FRAME_SIZE // restore sp
335 alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0
336 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
339 tramp_alias x30, tramp_exit_native
342 tramp_alias x30, tramp_exit_compat
351 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
353 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from
354 * EL0, there is no need to check the state of TTBR0_EL1 since
355 * accesses are always enabled.
356 * Note that the meaning of this bit differs from the ARMv8.1 PAN
357 * feature as all TTBR0_EL1 accesses are disabled, not just those to
360 SYM_CODE_START_LOCAL(__swpan_entry_el1)
362 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID
363 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR
364 b.eq 1f // TTBR0 access already disabled
365 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR
366 SYM_INNER_LABEL(__swpan_entry_el0, SYM_L_LOCAL)
367 __uaccess_ttbr0_disable x21
369 SYM_CODE_END(__swpan_entry_el1)
372 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR
375 SYM_CODE_START_LOCAL(__swpan_exit_el1)
376 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set
377 __uaccess_ttbr0_enable x0, x1
378 1: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
380 SYM_CODE_END(__swpan_exit_el1)
382 SYM_CODE_START_LOCAL(__swpan_exit_el0)
383 __uaccess_ttbr0_enable x0, x1
385 * Enable errata workarounds only if returning to user. The only
386 * workaround currently required for TTBR0_EL1 changes are for the
387 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
390 b post_ttbr_update_workaround
391 SYM_CODE_END(__swpan_exit_el0)
394 .macro irq_stack_entry
395 mov x19, sp // preserve the original sp
396 #ifdef CONFIG_SHADOW_CALL_STACK
397 mov x24, scs_sp // preserve the original shadow stack
401 * Compare sp with the base of the task stack.
402 * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack,
403 * and should switch to the irq stack.
405 ldr x25, [tsk, TSK_STACK]
407 and x25, x25, #~(THREAD_SIZE - 1)
410 ldr_this_cpu x25, irq_stack_ptr, x26
411 mov x26, #IRQ_STACK_SIZE
414 /* switch to the irq stack */
417 #ifdef CONFIG_SHADOW_CALL_STACK
418 /* also switch to the irq shadow stack */
419 adr_this_cpu scs_sp, irq_shadow_call_stack, x26
426 * The callee-saved regs (x19-x29) should be preserved between
427 * irq_stack_entry and irq_stack_exit, but note that kernel_entry
428 * uses x20-x23 to store data for later use.
430 .macro irq_stack_exit
432 #ifdef CONFIG_SHADOW_CALL_STACK
437 /* GPRs used by entry code */
438 tsk .req x28 // current thread_info
441 * Interrupt handling.
444 ldr_l x1, handle_arch_irq
451 #ifdef CONFIG_ARM64_PSEUDO_NMI
453 * Set res to 0 if irqs were unmasked in interrupted context.
454 * Otherwise set res to non-0 value.
456 .macro test_irqs_unmasked res:req, pmr:req
457 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
458 sub \res, \pmr, #GIC_PRIO_IRQON
465 .macro gic_prio_kentry_setup, tmp:req
466 #ifdef CONFIG_ARM64_PSEUDO_NMI
467 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
468 mov \tmp, #(GIC_PRIO_PSR_I_SET | GIC_PRIO_IRQON)
469 msr_s SYS_ICC_PMR_EL1, \tmp
470 alternative_else_nop_endif
474 .macro gic_prio_irq_setup, pmr:req, tmp:req
475 #ifdef CONFIG_ARM64_PSEUDO_NMI
476 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
477 orr \tmp, \pmr, #GIC_PRIO_PSR_I_SET
478 msr_s SYS_ICC_PMR_EL1, \tmp
479 alternative_else_nop_endif
488 .pushsection ".entry.text", "ax"
491 SYM_CODE_START(vectors)
492 kernel_ventry 1, sync_invalid // Synchronous EL1t
493 kernel_ventry 1, irq_invalid // IRQ EL1t
494 kernel_ventry 1, fiq_invalid // FIQ EL1t
495 kernel_ventry 1, error_invalid // Error EL1t
497 kernel_ventry 1, sync // Synchronous EL1h
498 kernel_ventry 1, irq // IRQ EL1h
499 kernel_ventry 1, fiq_invalid // FIQ EL1h
500 kernel_ventry 1, error // Error EL1h
502 kernel_ventry 0, sync // Synchronous 64-bit EL0
503 kernel_ventry 0, irq // IRQ 64-bit EL0
504 kernel_ventry 0, fiq_invalid // FIQ 64-bit EL0
505 kernel_ventry 0, error // Error 64-bit EL0
508 kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0
509 kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0
510 kernel_ventry 0, fiq_invalid_compat, 32 // FIQ 32-bit EL0
511 kernel_ventry 0, error_compat, 32 // Error 32-bit EL0
513 kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0
514 kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0
515 kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0
516 kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0
518 SYM_CODE_END(vectors)
520 #ifdef CONFIG_VMAP_STACK
522 * We detected an overflow in kernel_ventry, which switched to the
523 * overflow stack. Stash the exception regs, and head to our overflow
527 /* Restore the original x0 value */
531 * Store the original GPRs to the new stack. The orginal SP (minus
532 * S_FRAME_SIZE) was stashed in tpidr_el0 by kernel_ventry.
534 sub sp, sp, #S_FRAME_SIZE
537 add x0, x0, #S_FRAME_SIZE
540 /* Stash the regs for handle_bad_stack */
546 #endif /* CONFIG_VMAP_STACK */
549 * Invalid mode handlers
551 .macro inv_entry, el, reason, regsize = 64
552 kernel_entry \el, \regsize
560 SYM_CODE_START_LOCAL(el0_sync_invalid)
561 inv_entry 0, BAD_SYNC
562 SYM_CODE_END(el0_sync_invalid)
564 SYM_CODE_START_LOCAL(el0_irq_invalid)
566 SYM_CODE_END(el0_irq_invalid)
568 SYM_CODE_START_LOCAL(el0_fiq_invalid)
570 SYM_CODE_END(el0_fiq_invalid)
572 SYM_CODE_START_LOCAL(el0_error_invalid)
573 inv_entry 0, BAD_ERROR
574 SYM_CODE_END(el0_error_invalid)
577 SYM_CODE_START_LOCAL(el0_fiq_invalid_compat)
578 inv_entry 0, BAD_FIQ, 32
579 SYM_CODE_END(el0_fiq_invalid_compat)
582 SYM_CODE_START_LOCAL(el1_sync_invalid)
583 inv_entry 1, BAD_SYNC
584 SYM_CODE_END(el1_sync_invalid)
586 SYM_CODE_START_LOCAL(el1_irq_invalid)
588 SYM_CODE_END(el1_irq_invalid)
590 SYM_CODE_START_LOCAL(el1_fiq_invalid)
592 SYM_CODE_END(el1_fiq_invalid)
594 SYM_CODE_START_LOCAL(el1_error_invalid)
595 inv_entry 1, BAD_ERROR
596 SYM_CODE_END(el1_error_invalid)
602 SYM_CODE_START_LOCAL_NOALIGN(el1_sync)
607 SYM_CODE_END(el1_sync)
610 SYM_CODE_START_LOCAL_NOALIGN(el1_irq)
612 gic_prio_irq_setup pmr=x20, tmp=x1
615 #ifdef CONFIG_ARM64_PSEUDO_NMI
616 test_irqs_unmasked res=x0, pmr=x20
622 #ifdef CONFIG_TRACE_IRQFLAGS
623 bl trace_hardirqs_off
628 #ifdef CONFIG_PREEMPTION
629 ldr x24, [tsk, #TSK_TI_PREEMPT] // get preempt count
630 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
632 * DA_F were cleared at start of handling. If anything is set in DAIF,
633 * we come back from an NMI, so skip preemption
637 alternative_else_nop_endif
638 cbnz x24, 1f // preempt count != 0 || NMI return path
639 bl arm64_preempt_schedule_irq // irq en/disable is done inside
643 #ifdef CONFIG_ARM64_PSEUDO_NMI
645 * When using IRQ priority masking, we can get spurious interrupts while
646 * PMR is set to GIC_PRIO_IRQOFF. An NMI might also have occurred in a
647 * section with interrupts disabled. Skip tracing in those cases.
649 test_irqs_unmasked res=x0, pmr=x20
655 #ifdef CONFIG_TRACE_IRQFLAGS
656 #ifdef CONFIG_ARM64_PSEUDO_NMI
657 test_irqs_unmasked res=x0, pmr=x20
665 SYM_CODE_END(el1_irq)
671 SYM_CODE_START_LOCAL_NOALIGN(el0_sync)
676 SYM_CODE_END(el0_sync)
680 SYM_CODE_START_LOCAL_NOALIGN(el0_sync_compat)
683 bl el0_sync_compat_handler
685 SYM_CODE_END(el0_sync_compat)
688 SYM_CODE_START_LOCAL_NOALIGN(el0_irq_compat)
691 SYM_CODE_END(el0_irq_compat)
693 SYM_CODE_START_LOCAL_NOALIGN(el0_error_compat)
696 SYM_CODE_END(el0_error_compat)
700 SYM_CODE_START_LOCAL_NOALIGN(el0_irq)
703 gic_prio_irq_setup pmr=x20, tmp=x0
707 #ifdef CONFIG_TRACE_IRQFLAGS
708 bl trace_hardirqs_off
711 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
713 bl do_el0_irq_bp_hardening
718 #ifdef CONFIG_TRACE_IRQFLAGS
722 SYM_CODE_END(el0_irq)
724 SYM_CODE_START_LOCAL(el1_error)
727 gic_prio_kentry_setup tmp=x2
732 SYM_CODE_END(el1_error)
734 SYM_CODE_START_LOCAL(el0_error)
738 gic_prio_kentry_setup tmp=x2
746 SYM_CODE_END(el0_error)
749 * "slow" syscall return path.
751 SYM_CODE_START_LOCAL(ret_to_user)
753 gic_prio_kentry_setup tmp=x3
754 ldr x1, [tsk, #TSK_TI_FLAGS]
755 and x2, x1, #_TIF_WORK_MASK
756 cbnz x2, work_pending
758 enable_step_tsk x1, x2
759 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK
765 * Ok, we need to do extra processing, enter the slow path.
770 #ifdef CONFIG_TRACE_IRQFLAGS
771 bl trace_hardirqs_on // enabled while in userspace
773 ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for single-step
775 SYM_CODE_END(ret_to_user)
777 .popsection // .entry.text
779 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
781 * Exception vectors trampoline.
783 .pushsection ".entry.tramp.text", "ax"
785 .macro tramp_map_kernel, tmp
787 add \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE)
788 bic \tmp, \tmp, #USER_ASID_FLAG
790 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
791 alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003
792 /* ASID already in \tmp[63:48] */
793 movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12)
794 movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12)
795 /* 2MB boundary containing the vectors, so we nobble the walk cache */
796 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12)
800 alternative_else_nop_endif
801 #endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */
804 .macro tramp_unmap_kernel, tmp
806 sub \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE)
807 orr \tmp, \tmp, #USER_ASID_FLAG
810 * We avoid running the post_ttbr_update_workaround here because
811 * it's only needed by Cavium ThunderX, which requires KPTI to be
816 .macro tramp_ventry, regsize = 64
820 msr tpidrro_el0, x30 // Restored in kernel_ventry
823 * Defend against branch aliasing attacks by pushing a dummy
824 * entry onto the return stack and using a RET instruction to
825 * enter the full-fat kernel vectors.
831 #ifdef CONFIG_RANDOMIZE_BASE
832 adr x30, tramp_vectors + PAGE_SIZE
833 alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003
838 alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM
839 prfm plil1strm, [x30, #(1b - tramp_vectors)]
840 alternative_else_nop_endif
842 add x30, x30, #(1b - tramp_vectors)
847 .macro tramp_exit, regsize = 64
848 adr x30, tramp_vectors
850 tramp_unmap_kernel x30
859 SYM_CODE_START_NOALIGN(tramp_vectors)
871 SYM_CODE_END(tramp_vectors)
873 SYM_CODE_START(tramp_exit_native)
875 SYM_CODE_END(tramp_exit_native)
877 SYM_CODE_START(tramp_exit_compat)
879 SYM_CODE_END(tramp_exit_compat)
882 .popsection // .entry.tramp.text
883 #ifdef CONFIG_RANDOMIZE_BASE
884 .pushsection ".rodata", "a"
886 SYM_DATA_START(__entry_tramp_data_start)
888 SYM_DATA_END(__entry_tramp_data_start)
889 .popsection // .rodata
890 #endif /* CONFIG_RANDOMIZE_BASE */
891 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
894 * Register switch for AArch64. The callee-saved registers need to be saved
895 * and restored. On entry:
896 * x0 = previous task_struct (must be preserved across the switch)
897 * x1 = next task_struct
898 * Previous and next are guaranteed not to be the same.
901 SYM_FUNC_START(cpu_switch_to)
902 mov x10, #THREAD_CPU_CONTEXT
905 stp x19, x20, [x8], #16 // store callee-saved registers
906 stp x21, x22, [x8], #16
907 stp x23, x24, [x8], #16
908 stp x25, x26, [x8], #16
909 stp x27, x28, [x8], #16
910 stp x29, x9, [x8], #16
913 ldp x19, x20, [x8], #16 // restore callee-saved registers
914 ldp x21, x22, [x8], #16
915 ldp x23, x24, [x8], #16
916 ldp x25, x26, [x8], #16
917 ldp x27, x28, [x8], #16
918 ldp x29, x9, [x8], #16
922 ptrauth_keys_install_kernel x1, x8, x9, x10
926 SYM_FUNC_END(cpu_switch_to)
927 NOKPROBE(cpu_switch_to)
930 * This is how we return from a fork.
932 SYM_CODE_START(ret_from_fork)
934 cbz x19, 1f // not a kernel thread
937 1: get_current_task tsk
939 SYM_CODE_END(ret_from_fork)
940 NOKPROBE(ret_from_fork)
942 #ifdef CONFIG_ARM_SDE_INTERFACE
944 #include <asm/sdei.h>
945 #include <uapi/linux/arm_sdei.h>
947 .macro sdei_handler_exit exit_mode
948 /* On success, this call never returns... */
949 cmp \exit_mode, #SDEI_EXIT_SMC
957 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
959 * The regular SDEI entry point may have been unmapped along with the rest of
960 * the kernel. This trampoline restores the kernel mapping to make the x1 memory
961 * argument accessible.
963 * This clobbers x4, __sdei_handler() will restore this from firmware's
967 .pushsection ".entry.tramp.text", "ax"
968 SYM_CODE_START(__sdei_asm_entry_trampoline)
970 tbz x4, #USER_ASID_BIT, 1f
972 tramp_map_kernel tmp=x4
977 * Use reg->interrupted_regs.addr_limit to remember whether to unmap
978 * the kernel on exit.
980 1: str x4, [x1, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)]
982 #ifdef CONFIG_RANDOMIZE_BASE
983 adr x4, tramp_vectors + PAGE_SIZE
984 add x4, x4, #:lo12:__sdei_asm_trampoline_next_handler
987 ldr x4, =__sdei_asm_handler
990 SYM_CODE_END(__sdei_asm_entry_trampoline)
991 NOKPROBE(__sdei_asm_entry_trampoline)
994 * Make the exit call and restore the original ttbr1_el1
996 * x0 & x1: setup for the exit API call
998 * x4: struct sdei_registered_event argument from registration time.
1000 SYM_CODE_START(__sdei_asm_exit_trampoline)
1001 ldr x4, [x4, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)]
1004 tramp_unmap_kernel tmp=x4
1006 1: sdei_handler_exit exit_mode=x2
1007 SYM_CODE_END(__sdei_asm_exit_trampoline)
1008 NOKPROBE(__sdei_asm_exit_trampoline)
1010 .popsection // .entry.tramp.text
1011 #ifdef CONFIG_RANDOMIZE_BASE
1012 .pushsection ".rodata", "a"
1013 SYM_DATA_START(__sdei_asm_trampoline_next_handler)
1014 .quad __sdei_asm_handler
1015 SYM_DATA_END(__sdei_asm_trampoline_next_handler)
1016 .popsection // .rodata
1017 #endif /* CONFIG_RANDOMIZE_BASE */
1018 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1021 * Software Delegated Exception entry point.
1024 * x1: struct sdei_registered_event argument from registration time.
1025 * x2: interrupted PC
1026 * x3: interrupted PSTATE
1027 * x4: maybe clobbered by the trampoline
1029 * Firmware has preserved x0->x17 for us, we must save/restore the rest to
1030 * follow SMC-CC. We save (or retrieve) all the registers as the handler may
1033 SYM_CODE_START(__sdei_asm_handler)
1034 stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC]
1035 stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2]
1036 stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3]
1037 stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4]
1038 stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5]
1039 stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6]
1040 stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7]
1041 stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8]
1042 stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9]
1043 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10]
1044 stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11]
1045 stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12]
1046 stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13]
1047 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14]
1049 stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR]
1053 #if defined(CONFIG_VMAP_STACK) || defined(CONFIG_SHADOW_CALL_STACK)
1054 ldrb w4, [x19, #SDEI_EVENT_PRIORITY]
1057 #ifdef CONFIG_VMAP_STACK
1059 * entry.S may have been using sp as a scratch register, find whether
1060 * this is a normal or critical event and switch to the appropriate
1061 * stack for this CPU.
1064 ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6
1066 1: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6
1067 2: mov x6, #SDEI_STACK_SIZE
1072 #ifdef CONFIG_SHADOW_CALL_STACK
1073 /* Use a separate shadow call stack for normal and critical events */
1075 adr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_normal, tmp=x6
1077 3: adr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_critical, tmp=x6
1082 * We may have interrupted userspace, or a guest, or exit-from or
1083 * return-to either of these. We can't trust sp_el0, restore it.
1086 ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1
1089 /* If we interrupted the kernel point to the previous stack/frame. */
1093 csel x29, x29, xzr, eq // fp, or zero
1094 csel x4, x2, xzr, eq // elr, or zero
1096 stp x29, x4, [sp, #-16]!
1099 add x0, x19, #SDEI_EVENT_INTREGS
1104 /* restore regs >x17 that we clobbered */
1105 mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline
1106 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14]
1107 ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9]
1108 ldp lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR]
1111 mov x1, x0 // address to complete_and_resume
1112 /* x0 = (x0 <= 1) ? EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME */
1114 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE
1115 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME
1118 ldr_l x2, sdei_exit_mode
1120 alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0
1121 sdei_handler_exit exit_mode=x2
1122 alternative_else_nop_endif
1124 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1125 tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline
1128 SYM_CODE_END(__sdei_asm_handler)
1129 NOKPROBE(__sdei_asm_handler)
1130 #endif /* CONFIG_ARM_SDE_INTERFACE */