1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Low-level exception handling code
5 * Copyright (C) 2012 ARM Ltd.
6 * Authors: Catalin Marinas <catalin.marinas@arm.com>
7 * Will Deacon <will.deacon@arm.com>
10 #include <linux/arm-smccc.h>
11 #include <linux/init.h>
12 #include <linux/linkage.h>
14 #include <asm/alternative.h>
15 #include <asm/assembler.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/asm_pointer_auth.h>
19 #include <asm/cpufeature.h>
20 #include <asm/errno.h>
23 #include <asm/memory.h>
25 #include <asm/processor.h>
26 #include <asm/ptrace.h>
28 #include <asm/thread_info.h>
29 #include <asm/asm-uaccess.h>
30 #include <asm/unistd.h>
33 * Context tracking and irqflag tracing need to instrument transitions between
34 * user and kernel mode.
36 .macro user_enter_irqoff
37 #if defined(CONFIG_CONTEXT_TRACKING) || defined(CONFIG_TRACE_IRQFLAGS)
43 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
57 .macro kernel_ventry, el, label, regsize = 64
59 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
61 alternative_if ARM64_UNMAP_KERNEL_AT_EL0
68 alternative_else_nop_endif
72 sub sp, sp, #PT_REGS_SIZE
73 #ifdef CONFIG_VMAP_STACK
75 * Test whether the SP has overflowed, without corrupting a GPR.
76 * Task and IRQ stacks are aligned so that SP & (1 << THREAD_SHIFT)
77 * should always be zero.
79 add sp, sp, x0 // sp' = sp + x0
80 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp
81 tbnz x0, #THREAD_SHIFT, 0f
82 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0
83 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp
88 * Either we've just detected an overflow, or we've taken an exception
89 * while on the overflow stack. Either way, we won't return to
90 * userspace, and can clobber EL0 registers to free up GPRs.
93 /* Stash the original SP (minus PT_REGS_SIZE) in tpidr_el0. */
96 /* Recover the original x0 value and stash it in tpidrro_el0 */
100 /* Switch to the overflow stack */
101 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0
104 * Check whether we were already on the overflow stack. This may happen
105 * after panic() re-enables interrupts.
107 mrs x0, tpidr_el0 // sp of interrupted context
108 sub x0, sp, x0 // delta with top of overflow stack
109 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range?
110 b.ne __bad_stack // no? -> bad stack pointer
112 /* We were already on the overflow stack. Restore sp/x0 and carry on. */
119 .macro tramp_alias, dst, sym
120 mov_q \dst, TRAMP_VALIAS
121 add \dst, \dst, #(\sym - .entry.tramp.text)
125 * This macro corrupts x0-x3. It is the caller's duty to save/restore
128 .macro apply_ssbd, state, tmp1, tmp2
129 alternative_cb spectre_v4_patch_fw_mitigation_enable
130 b .L__asm_ssbd_skip\@ // Patched to NOP
132 ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1
133 cbz \tmp2, .L__asm_ssbd_skip\@
134 ldr \tmp2, [tsk, #TSK_TI_FLAGS]
135 tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@
136 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2
138 alternative_cb spectre_v4_patch_fw_mitigation_conduit
139 nop // Patched to SMC/HVC #0
144 /* Check for MTE asynchronous tag check faults */
145 .macro check_mte_async_tcf, tmp, ti_flags
146 #ifdef CONFIG_ARM64_MTE
148 alternative_if_not ARM64_MTE
150 alternative_else_nop_endif
151 mrs_s \tmp, SYS_TFSRE0_EL1
152 tbz \tmp, #SYS_TFSR_EL1_TF0_SHIFT, 1f
153 /* Asynchronous TCF occurred for TTBR0 access, set the TI flag */
154 mov \tmp, #_TIF_MTE_ASYNC_FAULT
155 add \ti_flags, tsk, #TSK_TI_FLAGS
156 stset \tmp, [\ti_flags]
157 msr_s SYS_TFSRE0_EL1, xzr
162 /* Clear the MTE asynchronous tag check faults */
163 .macro clear_mte_async_tcf
164 #ifdef CONFIG_ARM64_MTE
165 alternative_if ARM64_MTE
167 msr_s SYS_TFSRE0_EL1, xzr
168 alternative_else_nop_endif
172 .macro mte_set_gcr, tmp, tmp2
173 #ifdef CONFIG_ARM64_MTE
175 * Calculate and set the exclude mask preserving
176 * the RRND (bit[16]) setting.
178 mrs_s \tmp2, SYS_GCR_EL1
179 bfi \tmp2, \tmp, #0, #16
180 msr_s SYS_GCR_EL1, \tmp2
184 .macro mte_set_kernel_gcr, tmp, tmp2
185 #ifdef CONFIG_KASAN_HW_TAGS
186 alternative_if_not ARM64_MTE
188 alternative_else_nop_endif
189 ldr_l \tmp, gcr_kernel_excl
191 mte_set_gcr \tmp, \tmp2
197 .macro mte_set_user_gcr, tsk, tmp, tmp2
198 #ifdef CONFIG_ARM64_MTE
199 alternative_if_not ARM64_MTE
201 alternative_else_nop_endif
202 ldr \tmp, [\tsk, #THREAD_GCR_EL1_USER]
204 mte_set_gcr \tmp, \tmp2
209 .macro kernel_entry, el, regsize = 64
211 mov w0, w0 // zero upper 32 bits of x0
213 stp x0, x1, [sp, #16 * 0]
214 stp x2, x3, [sp, #16 * 1]
215 stp x4, x5, [sp, #16 * 2]
216 stp x6, x7, [sp, #16 * 3]
217 stp x8, x9, [sp, #16 * 4]
218 stp x10, x11, [sp, #16 * 5]
219 stp x12, x13, [sp, #16 * 6]
220 stp x14, x15, [sp, #16 * 7]
221 stp x16, x17, [sp, #16 * 8]
222 stp x18, x19, [sp, #16 * 9]
223 stp x20, x21, [sp, #16 * 10]
224 stp x22, x23, [sp, #16 * 11]
225 stp x24, x25, [sp, #16 * 12]
226 stp x26, x27, [sp, #16 * 13]
227 stp x28, x29, [sp, #16 * 14]
232 ldr_this_cpu tsk, __entry_task, x20
236 * Ensure MDSCR_EL1.SS is clear, since we can unmask debug exceptions
239 ldr x19, [tsk, #TSK_TI_FLAGS]
240 disable_step_tsk x19, x20
242 /* Check for asynchronous tag check faults in user space */
243 check_mte_async_tcf x22, x23
244 apply_ssbd 1, x22, x23
246 #ifdef CONFIG_ARM64_PTR_AUTH
247 alternative_if ARM64_HAS_ADDRESS_AUTH
249 * Enable IA for in-kernel PAC if the task had it disabled. Although
250 * this could be implemented with an unconditional MRS which would avoid
251 * a load, this was measured to be slower on Cortex-A75 and Cortex-A76.
253 * Install the kernel IA key only if IA was enabled in the task. If IA
254 * was disabled on kernel exit then we would have left the kernel IA
255 * installed so there is no need to install it again.
257 ldr x0, [tsk, THREAD_SCTLR_USER]
258 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f
259 __ptrauth_keys_install_kernel_nosync tsk, x20, x22, x23
263 orr x0, x0, SCTLR_ELx_ENIA
267 alternative_else_nop_endif
270 mte_set_kernel_gcr x22, x23
274 add x21, sp, #PT_REGS_SIZE
276 .endif /* \el == 0 */
279 stp lr, x21, [sp, #S_LR]
282 * For exceptions from EL0, create a terminal frame record.
283 * For exceptions from EL1, create a synthetic frame record so the
284 * interrupted code shows up in the backtrace.
287 stp xzr, xzr, [sp, #S_STACKFRAME]
289 stp x29, x22, [sp, #S_STACKFRAME]
291 add x29, sp, #S_STACKFRAME
293 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
294 alternative_if_not ARM64_HAS_PAN
295 bl __swpan_entry_el\el
296 alternative_else_nop_endif
299 stp x22, x23, [sp, #S_PC]
301 /* Not in a syscall by default (el0_svc overwrites for real syscall) */
304 str w21, [sp, #S_SYSCALLNO]
308 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
309 mrs_s x20, SYS_ICC_PMR_EL1
310 str x20, [sp, #S_PMR_SAVE]
311 mov x20, #GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET
312 msr_s SYS_ICC_PMR_EL1, x20
313 alternative_else_nop_endif
315 /* Re-enable tag checking (TCO set on exception entry) */
316 #ifdef CONFIG_ARM64_MTE
317 alternative_if ARM64_MTE
319 alternative_else_nop_endif
323 * Registers that may be useful after this macro is invoked:
328 * x23 - aborted PSTATE
332 .macro kernel_exit, el
338 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
339 ldr x20, [sp, #S_PMR_SAVE]
340 msr_s SYS_ICC_PMR_EL1, x20
341 mrs_s x21, SYS_ICC_CTLR_EL1
342 tbz x21, #6, .L__skip_pmr_sync\@ // Check for ICC_CTLR_EL1.PMHE
343 dsb sy // Ensure priority change is seen by redistributor
345 alternative_else_nop_endif
347 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
349 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
350 alternative_if_not ARM64_HAS_PAN
351 bl __swpan_exit_el\el
352 alternative_else_nop_endif
356 ldr x23, [sp, #S_SP] // load return stack pointer
358 tst x22, #PSR_MODE32_BIT // native task?
361 #ifdef CONFIG_ARM64_ERRATUM_845719
362 alternative_if ARM64_WORKAROUND_845719
363 #ifdef CONFIG_PID_IN_CONTEXTIDR
364 mrs x29, contextidr_el1
365 msr contextidr_el1, x29
367 msr contextidr_el1, xzr
369 alternative_else_nop_endif
374 #ifdef CONFIG_ARM64_PTR_AUTH
375 alternative_if ARM64_HAS_ADDRESS_AUTH
377 * IA was enabled for in-kernel PAC. Disable it now if needed, or
378 * alternatively install the user's IA. All other per-task keys and
379 * SCTLR bits were updated on task switch.
381 * No kernel C function calls after this.
383 ldr x0, [tsk, THREAD_SCTLR_USER]
384 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f
385 __ptrauth_keys_install_user tsk, x0, x1, x2
389 bic x0, x0, SCTLR_ELx_ENIA
392 alternative_else_nop_endif
395 mte_set_user_gcr tsk, x0, x1
400 msr elr_el1, x21 // set up the return data
402 ldp x0, x1, [sp, #16 * 0]
403 ldp x2, x3, [sp, #16 * 1]
404 ldp x4, x5, [sp, #16 * 2]
405 ldp x6, x7, [sp, #16 * 3]
406 ldp x8, x9, [sp, #16 * 4]
407 ldp x10, x11, [sp, #16 * 5]
408 ldp x12, x13, [sp, #16 * 6]
409 ldp x14, x15, [sp, #16 * 7]
410 ldp x16, x17, [sp, #16 * 8]
411 ldp x18, x19, [sp, #16 * 9]
412 ldp x20, x21, [sp, #16 * 10]
413 ldp x22, x23, [sp, #16 * 11]
414 ldp x24, x25, [sp, #16 * 12]
415 ldp x26, x27, [sp, #16 * 13]
416 ldp x28, x29, [sp, #16 * 14]
418 add sp, sp, #PT_REGS_SIZE // restore sp
421 alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0
422 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
425 tramp_alias x30, tramp_exit_native
428 tramp_alias x30, tramp_exit_compat
432 /* Ensure any device/NC reads complete */
433 alternative_insn nop, "dmb sy", ARM64_WORKAROUND_1508412
440 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
442 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from
443 * EL0, there is no need to check the state of TTBR0_EL1 since
444 * accesses are always enabled.
445 * Note that the meaning of this bit differs from the ARMv8.1 PAN
446 * feature as all TTBR0_EL1 accesses are disabled, not just those to
449 SYM_CODE_START_LOCAL(__swpan_entry_el1)
451 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID
452 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR
453 b.eq 1f // TTBR0 access already disabled
454 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR
455 SYM_INNER_LABEL(__swpan_entry_el0, SYM_L_LOCAL)
456 __uaccess_ttbr0_disable x21
458 SYM_CODE_END(__swpan_entry_el1)
461 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR
464 SYM_CODE_START_LOCAL(__swpan_exit_el1)
465 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set
466 __uaccess_ttbr0_enable x0, x1
467 1: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
469 SYM_CODE_END(__swpan_exit_el1)
471 SYM_CODE_START_LOCAL(__swpan_exit_el0)
472 __uaccess_ttbr0_enable x0, x1
474 * Enable errata workarounds only if returning to user. The only
475 * workaround currently required for TTBR0_EL1 changes are for the
476 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
479 b post_ttbr_update_workaround
480 SYM_CODE_END(__swpan_exit_el0)
483 /* GPRs used by entry code */
484 tsk .req x28 // current thread_info
487 * Interrupt handling.
489 .macro gic_prio_kentry_setup, tmp:req
490 #ifdef CONFIG_ARM64_PSEUDO_NMI
491 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
492 mov \tmp, #(GIC_PRIO_PSR_I_SET | GIC_PRIO_IRQON)
493 msr_s SYS_ICC_PMR_EL1, \tmp
494 alternative_else_nop_endif
503 .pushsection ".entry.text", "ax"
506 SYM_CODE_START(vectors)
507 kernel_ventry 1, sync_invalid // Synchronous EL1t
508 kernel_ventry 1, irq_invalid // IRQ EL1t
509 kernel_ventry 1, fiq_invalid // FIQ EL1t
510 kernel_ventry 1, error_invalid // Error EL1t
512 kernel_ventry 1, sync // Synchronous EL1h
513 kernel_ventry 1, irq // IRQ EL1h
514 kernel_ventry 1, fiq // FIQ EL1h
515 kernel_ventry 1, error // Error EL1h
517 kernel_ventry 0, sync // Synchronous 64-bit EL0
518 kernel_ventry 0, irq // IRQ 64-bit EL0
519 kernel_ventry 0, fiq // FIQ 64-bit EL0
520 kernel_ventry 0, error // Error 64-bit EL0
523 kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0
524 kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0
525 kernel_ventry 0, fiq_compat, 32 // FIQ 32-bit EL0
526 kernel_ventry 0, error_compat, 32 // Error 32-bit EL0
528 kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0
529 kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0
530 kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0
531 kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0
533 SYM_CODE_END(vectors)
535 #ifdef CONFIG_VMAP_STACK
537 * We detected an overflow in kernel_ventry, which switched to the
538 * overflow stack. Stash the exception regs, and head to our overflow
542 /* Restore the original x0 value */
546 * Store the original GPRs to the new stack. The orginal SP (minus
547 * PT_REGS_SIZE) was stashed in tpidr_el0 by kernel_ventry.
549 sub sp, sp, #PT_REGS_SIZE
552 add x0, x0, #PT_REGS_SIZE
555 /* Stash the regs for handle_bad_stack */
561 #endif /* CONFIG_VMAP_STACK */
564 * Invalid mode handlers
566 .macro inv_entry, el, reason, regsize = 64
567 kernel_entry \el, \regsize
575 SYM_CODE_START_LOCAL(el0_sync_invalid)
576 inv_entry 0, BAD_SYNC
577 SYM_CODE_END(el0_sync_invalid)
579 SYM_CODE_START_LOCAL(el0_irq_invalid)
581 SYM_CODE_END(el0_irq_invalid)
583 SYM_CODE_START_LOCAL(el0_fiq_invalid)
585 SYM_CODE_END(el0_fiq_invalid)
587 SYM_CODE_START_LOCAL(el0_error_invalid)
588 inv_entry 0, BAD_ERROR
589 SYM_CODE_END(el0_error_invalid)
591 SYM_CODE_START_LOCAL(el1_sync_invalid)
592 inv_entry 1, BAD_SYNC
593 SYM_CODE_END(el1_sync_invalid)
595 SYM_CODE_START_LOCAL(el1_irq_invalid)
597 SYM_CODE_END(el1_irq_invalid)
599 SYM_CODE_START_LOCAL(el1_fiq_invalid)
601 SYM_CODE_END(el1_fiq_invalid)
603 SYM_CODE_START_LOCAL(el1_error_invalid)
604 inv_entry 1, BAD_ERROR
605 SYM_CODE_END(el1_error_invalid)
611 SYM_CODE_START_LOCAL_NOALIGN(el1_sync)
616 SYM_CODE_END(el1_sync)
619 SYM_CODE_START_LOCAL_NOALIGN(el1_irq)
624 SYM_CODE_END(el1_irq)
626 SYM_CODE_START_LOCAL_NOALIGN(el1_fiq)
631 SYM_CODE_END(el1_fiq)
637 SYM_CODE_START_LOCAL_NOALIGN(el0_sync)
642 SYM_CODE_END(el0_sync)
646 SYM_CODE_START_LOCAL_NOALIGN(el0_sync_compat)
649 bl el0_sync_compat_handler
651 SYM_CODE_END(el0_sync_compat)
654 SYM_CODE_START_LOCAL_NOALIGN(el0_irq_compat)
657 bl el0_irq_compat_handler
659 SYM_CODE_END(el0_irq_compat)
661 SYM_CODE_START_LOCAL_NOALIGN(el0_fiq_compat)
664 bl el0_fiq_compat_handler
666 SYM_CODE_END(el0_fiq_compat)
668 SYM_CODE_START_LOCAL_NOALIGN(el0_error_compat)
671 bl el0_error_compat_handler
673 SYM_CODE_END(el0_error_compat)
677 SYM_CODE_START_LOCAL_NOALIGN(el0_irq)
682 SYM_CODE_END(el0_irq)
684 SYM_CODE_START_LOCAL_NOALIGN(el0_fiq)
689 SYM_CODE_END(el0_fiq)
691 SYM_CODE_START_LOCAL(el1_error)
696 SYM_CODE_END(el1_error)
698 SYM_CODE_START_LOCAL(el0_error)
703 SYM_CODE_END(el0_error)
706 * "slow" syscall return path.
708 SYM_CODE_START_LOCAL(ret_to_user)
710 gic_prio_kentry_setup tmp=x3
711 #ifdef CONFIG_TRACE_IRQFLAGS
712 bl trace_hardirqs_off
714 ldr x19, [tsk, #TSK_TI_FLAGS]
715 and x2, x19, #_TIF_WORK_MASK
716 cbnz x2, work_pending
719 /* Ignore asynchronous tag check faults in the uaccess routines */
721 enable_step_tsk x19, x2
722 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK
728 * Ok, we need to do extra processing, enter the slow path.
734 ldr x19, [tsk, #TSK_TI_FLAGS] // re-check for single-step
736 SYM_CODE_END(ret_to_user)
738 .popsection // .entry.text
740 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
742 * Exception vectors trampoline.
744 .pushsection ".entry.tramp.text", "ax"
746 // Move from tramp_pg_dir to swapper_pg_dir
747 .macro tramp_map_kernel, tmp
749 add \tmp, \tmp, #TRAMP_SWAPPER_OFFSET
750 bic \tmp, \tmp, #USER_ASID_FLAG
752 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
753 alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003
754 /* ASID already in \tmp[63:48] */
755 movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12)
756 movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12)
757 /* 2MB boundary containing the vectors, so we nobble the walk cache */
758 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12)
762 alternative_else_nop_endif
763 #endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */
766 // Move from swapper_pg_dir to tramp_pg_dir
767 .macro tramp_unmap_kernel, tmp
769 sub \tmp, \tmp, #TRAMP_SWAPPER_OFFSET
770 orr \tmp, \tmp, #USER_ASID_FLAG
773 * We avoid running the post_ttbr_update_workaround here because
774 * it's only needed by Cavium ThunderX, which requires KPTI to be
779 .macro tramp_ventry, regsize = 64
783 msr tpidrro_el0, x30 // Restored in kernel_ventry
786 * Defend against branch aliasing attacks by pushing a dummy
787 * entry onto the return stack and using a RET instruction to
788 * enter the full-fat kernel vectors.
794 #ifdef CONFIG_RANDOMIZE_BASE
795 adr x30, tramp_vectors + PAGE_SIZE
796 alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003
801 alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM
802 prfm plil1strm, [x30, #(1b - tramp_vectors)]
803 alternative_else_nop_endif
805 add x30, x30, #(1b - tramp_vectors)
810 .macro tramp_exit, regsize = 64
811 adr x30, tramp_vectors
813 tramp_unmap_kernel x30
822 SYM_CODE_START_NOALIGN(tramp_vectors)
834 SYM_CODE_END(tramp_vectors)
836 SYM_CODE_START(tramp_exit_native)
838 SYM_CODE_END(tramp_exit_native)
840 SYM_CODE_START(tramp_exit_compat)
842 SYM_CODE_END(tramp_exit_compat)
845 .popsection // .entry.tramp.text
846 #ifdef CONFIG_RANDOMIZE_BASE
847 .pushsection ".rodata", "a"
849 SYM_DATA_START(__entry_tramp_data_start)
851 SYM_DATA_END(__entry_tramp_data_start)
852 .popsection // .rodata
853 #endif /* CONFIG_RANDOMIZE_BASE */
854 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
857 * Register switch for AArch64. The callee-saved registers need to be saved
858 * and restored. On entry:
859 * x0 = previous task_struct (must be preserved across the switch)
860 * x1 = next task_struct
861 * Previous and next are guaranteed not to be the same.
864 SYM_FUNC_START(cpu_switch_to)
865 mov x10, #THREAD_CPU_CONTEXT
868 stp x19, x20, [x8], #16 // store callee-saved registers
869 stp x21, x22, [x8], #16
870 stp x23, x24, [x8], #16
871 stp x25, x26, [x8], #16
872 stp x27, x28, [x8], #16
873 stp x29, x9, [x8], #16
876 ldp x19, x20, [x8], #16 // restore callee-saved registers
877 ldp x21, x22, [x8], #16
878 ldp x23, x24, [x8], #16
879 ldp x25, x26, [x8], #16
880 ldp x27, x28, [x8], #16
881 ldp x29, x9, [x8], #16
885 ptrauth_keys_install_kernel x1, x8, x9, x10
889 SYM_FUNC_END(cpu_switch_to)
890 NOKPROBE(cpu_switch_to)
893 * This is how we return from a fork.
895 SYM_CODE_START(ret_from_fork)
897 cbz x19, 1f // not a kernel thread
900 1: get_current_task tsk
902 SYM_CODE_END(ret_from_fork)
903 NOKPROBE(ret_from_fork)
906 * void call_on_irq_stack(struct pt_regs *regs,
907 * void (*func)(struct pt_regs *));
909 * Calls func(regs) using this CPU's irq stack and shadow irq stack.
911 SYM_FUNC_START(call_on_irq_stack)
912 #ifdef CONFIG_SHADOW_CALL_STACK
913 stp scs_sp, xzr, [sp, #-16]!
914 ldr_this_cpu scs_sp, irq_shadow_call_stack_ptr, x17
916 /* Create a frame record to save our LR and SP (implicit in FP) */
917 stp x29, x30, [sp, #-16]!
920 ldr_this_cpu x16, irq_stack_ptr, x17
921 mov x15, #IRQ_STACK_SIZE
924 /* Move to the new stack and call the function there */
929 * Restore the SP from the FP, and restore the FP and LR from the frame
933 ldp x29, x30, [sp], #16
934 #ifdef CONFIG_SHADOW_CALL_STACK
935 ldp scs_sp, xzr, [sp], #16
938 SYM_FUNC_END(call_on_irq_stack)
939 NOKPROBE(call_on_irq_stack)
941 #ifdef CONFIG_ARM_SDE_INTERFACE
943 #include <asm/sdei.h>
944 #include <uapi/linux/arm_sdei.h>
946 .macro sdei_handler_exit exit_mode
947 /* On success, this call never returns... */
948 cmp \exit_mode, #SDEI_EXIT_SMC
956 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
958 * The regular SDEI entry point may have been unmapped along with the rest of
959 * the kernel. This trampoline restores the kernel mapping to make the x1 memory
960 * argument accessible.
962 * This clobbers x4, __sdei_handler() will restore this from firmware's
966 .pushsection ".entry.tramp.text", "ax"
967 SYM_CODE_START(__sdei_asm_entry_trampoline)
969 tbz x4, #USER_ASID_BIT, 1f
971 tramp_map_kernel tmp=x4
976 * Remember whether to unmap the kernel on exit.
978 1: str x4, [x1, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)]
980 #ifdef CONFIG_RANDOMIZE_BASE
981 adr x4, tramp_vectors + PAGE_SIZE
982 add x4, x4, #:lo12:__sdei_asm_trampoline_next_handler
985 ldr x4, =__sdei_asm_handler
988 SYM_CODE_END(__sdei_asm_entry_trampoline)
989 NOKPROBE(__sdei_asm_entry_trampoline)
992 * Make the exit call and restore the original ttbr1_el1
994 * x0 & x1: setup for the exit API call
996 * x4: struct sdei_registered_event argument from registration time.
998 SYM_CODE_START(__sdei_asm_exit_trampoline)
999 ldr x4, [x4, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)]
1002 tramp_unmap_kernel tmp=x4
1004 1: sdei_handler_exit exit_mode=x2
1005 SYM_CODE_END(__sdei_asm_exit_trampoline)
1006 NOKPROBE(__sdei_asm_exit_trampoline)
1008 .popsection // .entry.tramp.text
1009 #ifdef CONFIG_RANDOMIZE_BASE
1010 .pushsection ".rodata", "a"
1011 SYM_DATA_START(__sdei_asm_trampoline_next_handler)
1012 .quad __sdei_asm_handler
1013 SYM_DATA_END(__sdei_asm_trampoline_next_handler)
1014 .popsection // .rodata
1015 #endif /* CONFIG_RANDOMIZE_BASE */
1016 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1019 * Software Delegated Exception entry point.
1022 * x1: struct sdei_registered_event argument from registration time.
1023 * x2: interrupted PC
1024 * x3: interrupted PSTATE
1025 * x4: maybe clobbered by the trampoline
1027 * Firmware has preserved x0->x17 for us, we must save/restore the rest to
1028 * follow SMC-CC. We save (or retrieve) all the registers as the handler may
1031 SYM_CODE_START(__sdei_asm_handler)
1032 stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC]
1033 stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2]
1034 stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3]
1035 stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4]
1036 stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5]
1037 stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6]
1038 stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7]
1039 stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8]
1040 stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9]
1041 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10]
1042 stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11]
1043 stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12]
1044 stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13]
1045 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14]
1047 stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR]
1051 #if defined(CONFIG_VMAP_STACK) || defined(CONFIG_SHADOW_CALL_STACK)
1052 ldrb w4, [x19, #SDEI_EVENT_PRIORITY]
1055 #ifdef CONFIG_VMAP_STACK
1057 * entry.S may have been using sp as a scratch register, find whether
1058 * this is a normal or critical event and switch to the appropriate
1059 * stack for this CPU.
1062 ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6
1064 1: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6
1065 2: mov x6, #SDEI_STACK_SIZE
1070 #ifdef CONFIG_SHADOW_CALL_STACK
1071 /* Use a separate shadow call stack for normal and critical events */
1073 ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_normal_ptr, tmp=x6
1075 3: ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_critical_ptr, tmp=x6
1080 * We may have interrupted userspace, or a guest, or exit-from or
1081 * return-to either of these. We can't trust sp_el0, restore it.
1084 ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1
1087 /* If we interrupted the kernel point to the previous stack/frame. */
1091 csel x29, x29, xzr, eq // fp, or zero
1092 csel x4, x2, xzr, eq // elr, or zero
1094 stp x29, x4, [sp, #-16]!
1097 add x0, x19, #SDEI_EVENT_INTREGS
1102 /* restore regs >x17 that we clobbered */
1103 mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline
1104 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14]
1105 ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9]
1106 ldp lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR]
1109 mov x1, x0 // address to complete_and_resume
1110 /* x0 = (x0 <= 1) ? EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME */
1112 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE
1113 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME
1116 ldr_l x2, sdei_exit_mode
1118 alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0
1119 sdei_handler_exit exit_mode=x2
1120 alternative_else_nop_endif
1122 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1123 tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline
1126 SYM_CODE_END(__sdei_asm_handler)
1127 NOKPROBE(__sdei_asm_handler)
1128 #endif /* CONFIG_ARM_SDE_INTERFACE */