1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Low-level exception handling code
5 * Copyright (C) 2012 ARM Ltd.
6 * Authors: Catalin Marinas <catalin.marinas@arm.com>
7 * Will Deacon <will.deacon@arm.com>
10 #include <linux/arm-smccc.h>
11 #include <linux/init.h>
12 #include <linux/linkage.h>
14 #include <asm/alternative.h>
15 #include <asm/assembler.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/asm_pointer_auth.h>
19 #include <asm/cpufeature.h>
20 #include <asm/errno.h>
23 #include <asm/memory.h>
25 #include <asm/processor.h>
26 #include <asm/ptrace.h>
28 #include <asm/thread_info.h>
29 #include <asm/asm-uaccess.h>
30 #include <asm/unistd.h>
33 * Context tracking and irqflag tracing need to instrument transitions between
34 * user and kernel mode.
36 .macro user_enter_irqoff
37 #if defined(CONFIG_CONTEXT_TRACKING) || defined(CONFIG_TRACE_IRQFLAGS)
43 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
48 .macro kernel_ventry, el:req, ht:req, regsize:req, label:req
50 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
52 alternative_if ARM64_UNMAP_KERNEL_AT_EL0
59 alternative_else_nop_endif
63 sub sp, sp, #PT_REGS_SIZE
64 #ifdef CONFIG_VMAP_STACK
66 * Test whether the SP has overflowed, without corrupting a GPR.
67 * Task and IRQ stacks are aligned so that SP & (1 << THREAD_SHIFT)
68 * should always be zero.
70 add sp, sp, x0 // sp' = sp + x0
71 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp
72 tbnz x0, #THREAD_SHIFT, 0f
73 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0
74 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp
75 b el\el\ht\()_\regsize\()_\label
79 * Either we've just detected an overflow, or we've taken an exception
80 * while on the overflow stack. Either way, we won't return to
81 * userspace, and can clobber EL0 registers to free up GPRs.
84 /* Stash the original SP (minus PT_REGS_SIZE) in tpidr_el0. */
87 /* Recover the original x0 value and stash it in tpidrro_el0 */
91 /* Switch to the overflow stack */
92 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0
95 * Check whether we were already on the overflow stack. This may happen
96 * after panic() re-enables interrupts.
98 mrs x0, tpidr_el0 // sp of interrupted context
99 sub x0, sp, x0 // delta with top of overflow stack
100 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range?
101 b.ne __bad_stack // no? -> bad stack pointer
103 /* We were already on the overflow stack. Restore sp/x0 and carry on. */
107 b el\el\ht\()_\regsize\()_\label
110 .macro tramp_alias, dst, sym
111 mov_q \dst, TRAMP_VALIAS
112 add \dst, \dst, #(\sym - .entry.tramp.text)
116 * This macro corrupts x0-x3. It is the caller's duty to save/restore
119 .macro apply_ssbd, state, tmp1, tmp2
120 alternative_cb spectre_v4_patch_fw_mitigation_enable
121 b .L__asm_ssbd_skip\@ // Patched to NOP
123 ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1
124 cbz \tmp2, .L__asm_ssbd_skip\@
125 ldr \tmp2, [tsk, #TSK_TI_FLAGS]
126 tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@
127 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2
129 alternative_cb spectre_v4_patch_fw_mitigation_conduit
130 nop // Patched to SMC/HVC #0
135 /* Check for MTE asynchronous tag check faults */
136 .macro check_mte_async_tcf, tmp, ti_flags, thread_sctlr
137 #ifdef CONFIG_ARM64_MTE
139 alternative_if_not ARM64_MTE
141 alternative_else_nop_endif
143 * Asynchronous tag check faults are only possible in ASYNC (2) or
144 * ASYM (3) modes. In each of these modes bit 1 of SCTLR_EL1.TCF0 is
145 * set, so skip the check if it is unset.
147 tbz \thread_sctlr, #(SCTLR_EL1_TCF0_SHIFT + 1), 1f
148 mrs_s \tmp, SYS_TFSRE0_EL1
149 tbz \tmp, #SYS_TFSR_EL1_TF0_SHIFT, 1f
150 /* Asynchronous TCF occurred for TTBR0 access, set the TI flag */
151 mov \tmp, #_TIF_MTE_ASYNC_FAULT
152 add \ti_flags, tsk, #TSK_TI_FLAGS
153 stset \tmp, [\ti_flags]
158 /* Clear the MTE asynchronous tag check faults */
159 .macro clear_mte_async_tcf thread_sctlr
160 #ifdef CONFIG_ARM64_MTE
161 alternative_if ARM64_MTE
162 /* See comment in check_mte_async_tcf above. */
163 tbz \thread_sctlr, #(SCTLR_EL1_TCF0_SHIFT + 1), 1f
165 msr_s SYS_TFSRE0_EL1, xzr
167 alternative_else_nop_endif
171 .macro mte_set_gcr, mte_ctrl, tmp
172 #ifdef CONFIG_ARM64_MTE
173 ubfx \tmp, \mte_ctrl, #MTE_CTRL_GCR_USER_EXCL_SHIFT, #16
174 orr \tmp, \tmp, #SYS_GCR_EL1_RRND
175 msr_s SYS_GCR_EL1, \tmp
179 .macro mte_set_kernel_gcr, tmp, tmp2
180 #ifdef CONFIG_KASAN_HW_TAGS
181 alternative_if_not ARM64_MTE
183 alternative_else_nop_endif
184 ldr_l \tmp, gcr_kernel_excl
186 mte_set_gcr \tmp, \tmp2
192 .macro mte_set_user_gcr, tsk, tmp, tmp2
193 #ifdef CONFIG_ARM64_MTE
194 alternative_if_not ARM64_MTE
196 alternative_else_nop_endif
197 ldr \tmp, [\tsk, #THREAD_MTE_CTRL]
199 mte_set_gcr \tmp, \tmp2
204 .macro kernel_entry, el, regsize = 64
206 mov w0, w0 // zero upper 32 bits of x0
208 stp x0, x1, [sp, #16 * 0]
209 stp x2, x3, [sp, #16 * 1]
210 stp x4, x5, [sp, #16 * 2]
211 stp x6, x7, [sp, #16 * 3]
212 stp x8, x9, [sp, #16 * 4]
213 stp x10, x11, [sp, #16 * 5]
214 stp x12, x13, [sp, #16 * 6]
215 stp x14, x15, [sp, #16 * 7]
216 stp x16, x17, [sp, #16 * 8]
217 stp x18, x19, [sp, #16 * 9]
218 stp x20, x21, [sp, #16 * 10]
219 stp x22, x23, [sp, #16 * 11]
220 stp x24, x25, [sp, #16 * 12]
221 stp x26, x27, [sp, #16 * 13]
222 stp x28, x29, [sp, #16 * 14]
227 ldr_this_cpu tsk, __entry_task, x20
231 * Ensure MDSCR_EL1.SS is clear, since we can unmask debug exceptions
234 ldr x19, [tsk, #TSK_TI_FLAGS]
235 disable_step_tsk x19, x20
237 /* Check for asynchronous tag check faults in user space */
238 ldr x0, [tsk, THREAD_SCTLR_USER]
239 check_mte_async_tcf x22, x23, x0
241 #ifdef CONFIG_ARM64_PTR_AUTH
242 alternative_if ARM64_HAS_ADDRESS_AUTH
244 * Enable IA for in-kernel PAC if the task had it disabled. Although
245 * this could be implemented with an unconditional MRS which would avoid
246 * a load, this was measured to be slower on Cortex-A75 and Cortex-A76.
248 * Install the kernel IA key only if IA was enabled in the task. If IA
249 * was disabled on kernel exit then we would have left the kernel IA
250 * installed so there is no need to install it again.
252 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f
253 __ptrauth_keys_install_kernel_nosync tsk, x20, x22, x23
257 orr x0, x0, SCTLR_ELx_ENIA
261 alternative_else_nop_endif
264 apply_ssbd 1, x22, x23
266 mte_set_kernel_gcr x22, x23
270 add x21, sp, #PT_REGS_SIZE
272 .endif /* \el == 0 */
275 stp lr, x21, [sp, #S_LR]
278 * For exceptions from EL0, create a final frame record.
279 * For exceptions from EL1, create a synthetic frame record so the
280 * interrupted code shows up in the backtrace.
283 stp xzr, xzr, [sp, #S_STACKFRAME]
285 stp x29, x22, [sp, #S_STACKFRAME]
287 add x29, sp, #S_STACKFRAME
289 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
290 alternative_if_not ARM64_HAS_PAN
291 bl __swpan_entry_el\el
292 alternative_else_nop_endif
295 stp x22, x23, [sp, #S_PC]
297 /* Not in a syscall by default (el0_svc overwrites for real syscall) */
300 str w21, [sp, #S_SYSCALLNO]
304 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
305 mrs_s x20, SYS_ICC_PMR_EL1
306 str x20, [sp, #S_PMR_SAVE]
307 mov x20, #GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET
308 msr_s SYS_ICC_PMR_EL1, x20
309 alternative_else_nop_endif
311 /* Re-enable tag checking (TCO set on exception entry) */
312 #ifdef CONFIG_ARM64_MTE
313 alternative_if ARM64_MTE
315 alternative_else_nop_endif
319 * Registers that may be useful after this macro is invoked:
324 * x23 - aborted PSTATE
328 .macro kernel_exit, el
334 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
335 ldr x20, [sp, #S_PMR_SAVE]
336 msr_s SYS_ICC_PMR_EL1, x20
337 mrs_s x21, SYS_ICC_CTLR_EL1
338 tbz x21, #6, .L__skip_pmr_sync\@ // Check for ICC_CTLR_EL1.PMHE
339 dsb sy // Ensure priority change is seen by redistributor
341 alternative_else_nop_endif
343 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
345 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
346 alternative_if_not ARM64_HAS_PAN
347 bl __swpan_exit_el\el
348 alternative_else_nop_endif
352 ldr x23, [sp, #S_SP] // load return stack pointer
354 tst x22, #PSR_MODE32_BIT // native task?
357 #ifdef CONFIG_ARM64_ERRATUM_845719
358 alternative_if ARM64_WORKAROUND_845719
359 #ifdef CONFIG_PID_IN_CONTEXTIDR
360 mrs x29, contextidr_el1
361 msr contextidr_el1, x29
363 msr contextidr_el1, xzr
365 alternative_else_nop_endif
370 /* Ignore asynchronous tag check faults in the uaccess routines */
371 ldr x0, [tsk, THREAD_SCTLR_USER]
372 clear_mte_async_tcf x0
374 #ifdef CONFIG_ARM64_PTR_AUTH
375 alternative_if ARM64_HAS_ADDRESS_AUTH
377 * IA was enabled for in-kernel PAC. Disable it now if needed, or
378 * alternatively install the user's IA. All other per-task keys and
379 * SCTLR bits were updated on task switch.
381 * No kernel C function calls after this.
383 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f
384 __ptrauth_keys_install_user tsk, x0, x1, x2
388 bic x0, x0, SCTLR_ELx_ENIA
391 alternative_else_nop_endif
394 mte_set_user_gcr tsk, x0, x1
399 msr elr_el1, x21 // set up the return data
401 ldp x0, x1, [sp, #16 * 0]
402 ldp x2, x3, [sp, #16 * 1]
403 ldp x4, x5, [sp, #16 * 2]
404 ldp x6, x7, [sp, #16 * 3]
405 ldp x8, x9, [sp, #16 * 4]
406 ldp x10, x11, [sp, #16 * 5]
407 ldp x12, x13, [sp, #16 * 6]
408 ldp x14, x15, [sp, #16 * 7]
409 ldp x16, x17, [sp, #16 * 8]
410 ldp x18, x19, [sp, #16 * 9]
411 ldp x20, x21, [sp, #16 * 10]
412 ldp x22, x23, [sp, #16 * 11]
413 ldp x24, x25, [sp, #16 * 12]
414 ldp x26, x27, [sp, #16 * 13]
415 ldp x28, x29, [sp, #16 * 14]
417 add sp, sp, #PT_REGS_SIZE // restore sp
420 alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0
421 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
424 tramp_alias x30, tramp_exit_native
427 tramp_alias x30, tramp_exit_compat
431 /* Ensure any device/NC reads complete */
432 alternative_insn nop, "dmb sy", ARM64_WORKAROUND_1508412
439 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
441 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from
442 * EL0, there is no need to check the state of TTBR0_EL1 since
443 * accesses are always enabled.
444 * Note that the meaning of this bit differs from the ARMv8.1 PAN
445 * feature as all TTBR0_EL1 accesses are disabled, not just those to
448 SYM_CODE_START_LOCAL(__swpan_entry_el1)
450 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID
451 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR
452 b.eq 1f // TTBR0 access already disabled
453 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR
454 SYM_INNER_LABEL(__swpan_entry_el0, SYM_L_LOCAL)
455 __uaccess_ttbr0_disable x21
457 SYM_CODE_END(__swpan_entry_el1)
460 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR
463 SYM_CODE_START_LOCAL(__swpan_exit_el1)
464 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set
465 __uaccess_ttbr0_enable x0, x1
466 1: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
468 SYM_CODE_END(__swpan_exit_el1)
470 SYM_CODE_START_LOCAL(__swpan_exit_el0)
471 __uaccess_ttbr0_enable x0, x1
473 * Enable errata workarounds only if returning to user. The only
474 * workaround currently required for TTBR0_EL1 changes are for the
475 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
478 b post_ttbr_update_workaround
479 SYM_CODE_END(__swpan_exit_el0)
482 /* GPRs used by entry code */
483 tsk .req x28 // current thread_info
486 * Interrupt handling.
488 .macro gic_prio_kentry_setup, tmp:req
489 #ifdef CONFIG_ARM64_PSEUDO_NMI
490 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
491 mov \tmp, #(GIC_PRIO_PSR_I_SET | GIC_PRIO_IRQON)
492 msr_s SYS_ICC_PMR_EL1, \tmp
493 alternative_else_nop_endif
502 .pushsection ".entry.text", "ax"
505 SYM_CODE_START(vectors)
506 kernel_ventry 1, t, 64, sync // Synchronous EL1t
507 kernel_ventry 1, t, 64, irq // IRQ EL1t
508 kernel_ventry 1, t, 64, fiq // FIQ EL1h
509 kernel_ventry 1, t, 64, error // Error EL1t
511 kernel_ventry 1, h, 64, sync // Synchronous EL1h
512 kernel_ventry 1, h, 64, irq // IRQ EL1h
513 kernel_ventry 1, h, 64, fiq // FIQ EL1h
514 kernel_ventry 1, h, 64, error // Error EL1h
516 kernel_ventry 0, t, 64, sync // Synchronous 64-bit EL0
517 kernel_ventry 0, t, 64, irq // IRQ 64-bit EL0
518 kernel_ventry 0, t, 64, fiq // FIQ 64-bit EL0
519 kernel_ventry 0, t, 64, error // Error 64-bit EL0
521 kernel_ventry 0, t, 32, sync // Synchronous 32-bit EL0
522 kernel_ventry 0, t, 32, irq // IRQ 32-bit EL0
523 kernel_ventry 0, t, 32, fiq // FIQ 32-bit EL0
524 kernel_ventry 0, t, 32, error // Error 32-bit EL0
525 SYM_CODE_END(vectors)
527 #ifdef CONFIG_VMAP_STACK
529 * We detected an overflow in kernel_ventry, which switched to the
530 * overflow stack. Stash the exception regs, and head to our overflow
534 /* Restore the original x0 value */
538 * Store the original GPRs to the new stack. The orginal SP (minus
539 * PT_REGS_SIZE) was stashed in tpidr_el0 by kernel_ventry.
541 sub sp, sp, #PT_REGS_SIZE
544 add x0, x0, #PT_REGS_SIZE
547 /* Stash the regs for handle_bad_stack */
553 #endif /* CONFIG_VMAP_STACK */
556 .macro entry_handler el:req, ht:req, regsize:req, label:req
557 SYM_CODE_START_LOCAL(el\el\ht\()_\regsize\()_\label)
558 kernel_entry \el, \regsize
560 bl el\el\ht\()_\regsize\()_\label\()_handler
566 SYM_CODE_END(el\el\ht\()_\regsize\()_\label)
570 * Early exception handlers
572 entry_handler 1, t, 64, sync
573 entry_handler 1, t, 64, irq
574 entry_handler 1, t, 64, fiq
575 entry_handler 1, t, 64, error
577 entry_handler 1, h, 64, sync
578 entry_handler 1, h, 64, irq
579 entry_handler 1, h, 64, fiq
580 entry_handler 1, h, 64, error
582 entry_handler 0, t, 64, sync
583 entry_handler 0, t, 64, irq
584 entry_handler 0, t, 64, fiq
585 entry_handler 0, t, 64, error
587 entry_handler 0, t, 32, sync
588 entry_handler 0, t, 32, irq
589 entry_handler 0, t, 32, fiq
590 entry_handler 0, t, 32, error
592 SYM_CODE_START_LOCAL(ret_to_kernel)
594 SYM_CODE_END(ret_to_kernel)
597 * "slow" syscall return path.
599 SYM_CODE_START_LOCAL(ret_to_user)
601 gic_prio_kentry_setup tmp=x3
602 #ifdef CONFIG_TRACE_IRQFLAGS
603 bl trace_hardirqs_off
605 ldr x19, [tsk, #TSK_TI_FLAGS]
606 and x2, x19, #_TIF_WORK_MASK
607 cbnz x2, work_pending
610 enable_step_tsk x19, x2
611 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK
617 * Ok, we need to do extra processing, enter the slow path.
623 ldr x19, [tsk, #TSK_TI_FLAGS] // re-check for single-step
625 SYM_CODE_END(ret_to_user)
627 .popsection // .entry.text
629 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
631 * Exception vectors trampoline.
633 .pushsection ".entry.tramp.text", "ax"
635 // Move from tramp_pg_dir to swapper_pg_dir
636 .macro tramp_map_kernel, tmp
638 add \tmp, \tmp, #TRAMP_SWAPPER_OFFSET
639 bic \tmp, \tmp, #USER_ASID_FLAG
641 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
642 alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003
643 /* ASID already in \tmp[63:48] */
644 movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12)
645 movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12)
646 /* 2MB boundary containing the vectors, so we nobble the walk cache */
647 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12)
651 alternative_else_nop_endif
652 #endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */
655 // Move from swapper_pg_dir to tramp_pg_dir
656 .macro tramp_unmap_kernel, tmp
658 sub \tmp, \tmp, #TRAMP_SWAPPER_OFFSET
659 orr \tmp, \tmp, #USER_ASID_FLAG
662 * We avoid running the post_ttbr_update_workaround here because
663 * it's only needed by Cavium ThunderX, which requires KPTI to be
668 .macro tramp_ventry, regsize = 64
672 msr tpidrro_el0, x30 // Restored in kernel_ventry
675 * Defend against branch aliasing attacks by pushing a dummy
676 * entry onto the return stack and using a RET instruction to
677 * enter the full-fat kernel vectors.
683 #ifdef CONFIG_RANDOMIZE_BASE
684 adr x30, tramp_vectors + PAGE_SIZE
685 alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003
690 alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM
691 prfm plil1strm, [x30, #(1b - tramp_vectors)]
692 alternative_else_nop_endif
694 add x30, x30, #(1b - tramp_vectors)
699 .macro tramp_exit, regsize = 64
700 adr x30, tramp_vectors
702 tramp_unmap_kernel x30
711 SYM_CODE_START_NOALIGN(tramp_vectors)
723 SYM_CODE_END(tramp_vectors)
725 SYM_CODE_START(tramp_exit_native)
727 SYM_CODE_END(tramp_exit_native)
729 SYM_CODE_START(tramp_exit_compat)
731 SYM_CODE_END(tramp_exit_compat)
734 .popsection // .entry.tramp.text
735 #ifdef CONFIG_RANDOMIZE_BASE
736 .pushsection ".rodata", "a"
738 SYM_DATA_START(__entry_tramp_data_start)
740 SYM_DATA_END(__entry_tramp_data_start)
741 .popsection // .rodata
742 #endif /* CONFIG_RANDOMIZE_BASE */
743 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
746 * Register switch for AArch64. The callee-saved registers need to be saved
747 * and restored. On entry:
748 * x0 = previous task_struct (must be preserved across the switch)
749 * x1 = next task_struct
750 * Previous and next are guaranteed not to be the same.
753 SYM_FUNC_START(cpu_switch_to)
754 mov x10, #THREAD_CPU_CONTEXT
757 stp x19, x20, [x8], #16 // store callee-saved registers
758 stp x21, x22, [x8], #16
759 stp x23, x24, [x8], #16
760 stp x25, x26, [x8], #16
761 stp x27, x28, [x8], #16
762 stp x29, x9, [x8], #16
765 ldp x19, x20, [x8], #16 // restore callee-saved registers
766 ldp x21, x22, [x8], #16
767 ldp x23, x24, [x8], #16
768 ldp x25, x26, [x8], #16
769 ldp x27, x28, [x8], #16
770 ldp x29, x9, [x8], #16
774 ptrauth_keys_install_kernel x1, x8, x9, x10
778 SYM_FUNC_END(cpu_switch_to)
779 NOKPROBE(cpu_switch_to)
782 * This is how we return from a fork.
784 SYM_CODE_START(ret_from_fork)
786 cbz x19, 1f // not a kernel thread
789 1: get_current_task tsk
791 SYM_CODE_END(ret_from_fork)
792 NOKPROBE(ret_from_fork)
795 * void call_on_irq_stack(struct pt_regs *regs,
796 * void (*func)(struct pt_regs *));
798 * Calls func(regs) using this CPU's irq stack and shadow irq stack.
800 SYM_FUNC_START(call_on_irq_stack)
801 #ifdef CONFIG_SHADOW_CALL_STACK
802 stp scs_sp, xzr, [sp, #-16]!
803 ldr_this_cpu scs_sp, irq_shadow_call_stack_ptr, x17
805 /* Create a frame record to save our LR and SP (implicit in FP) */
806 stp x29, x30, [sp, #-16]!
809 ldr_this_cpu x16, irq_stack_ptr, x17
810 mov x15, #IRQ_STACK_SIZE
813 /* Move to the new stack and call the function there */
818 * Restore the SP from the FP, and restore the FP and LR from the frame
822 ldp x29, x30, [sp], #16
823 #ifdef CONFIG_SHADOW_CALL_STACK
824 ldp scs_sp, xzr, [sp], #16
827 SYM_FUNC_END(call_on_irq_stack)
828 NOKPROBE(call_on_irq_stack)
830 #ifdef CONFIG_ARM_SDE_INTERFACE
832 #include <asm/sdei.h>
833 #include <uapi/linux/arm_sdei.h>
835 .macro sdei_handler_exit exit_mode
836 /* On success, this call never returns... */
837 cmp \exit_mode, #SDEI_EXIT_SMC
845 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
847 * The regular SDEI entry point may have been unmapped along with the rest of
848 * the kernel. This trampoline restores the kernel mapping to make the x1 memory
849 * argument accessible.
851 * This clobbers x4, __sdei_handler() will restore this from firmware's
855 .pushsection ".entry.tramp.text", "ax"
856 SYM_CODE_START(__sdei_asm_entry_trampoline)
858 tbz x4, #USER_ASID_BIT, 1f
860 tramp_map_kernel tmp=x4
865 * Remember whether to unmap the kernel on exit.
867 1: str x4, [x1, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)]
869 #ifdef CONFIG_RANDOMIZE_BASE
870 adr x4, tramp_vectors + PAGE_SIZE
871 add x4, x4, #:lo12:__sdei_asm_trampoline_next_handler
874 ldr x4, =__sdei_asm_handler
877 SYM_CODE_END(__sdei_asm_entry_trampoline)
878 NOKPROBE(__sdei_asm_entry_trampoline)
881 * Make the exit call and restore the original ttbr1_el1
883 * x0 & x1: setup for the exit API call
885 * x4: struct sdei_registered_event argument from registration time.
887 SYM_CODE_START(__sdei_asm_exit_trampoline)
888 ldr x4, [x4, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)]
891 tramp_unmap_kernel tmp=x4
893 1: sdei_handler_exit exit_mode=x2
894 SYM_CODE_END(__sdei_asm_exit_trampoline)
895 NOKPROBE(__sdei_asm_exit_trampoline)
897 .popsection // .entry.tramp.text
898 #ifdef CONFIG_RANDOMIZE_BASE
899 .pushsection ".rodata", "a"
900 SYM_DATA_START(__sdei_asm_trampoline_next_handler)
901 .quad __sdei_asm_handler
902 SYM_DATA_END(__sdei_asm_trampoline_next_handler)
903 .popsection // .rodata
904 #endif /* CONFIG_RANDOMIZE_BASE */
905 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
908 * Software Delegated Exception entry point.
911 * x1: struct sdei_registered_event argument from registration time.
913 * x3: interrupted PSTATE
914 * x4: maybe clobbered by the trampoline
916 * Firmware has preserved x0->x17 for us, we must save/restore the rest to
917 * follow SMC-CC. We save (or retrieve) all the registers as the handler may
920 SYM_CODE_START(__sdei_asm_handler)
921 stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC]
922 stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2]
923 stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3]
924 stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4]
925 stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5]
926 stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6]
927 stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7]
928 stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8]
929 stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9]
930 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10]
931 stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11]
932 stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12]
933 stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13]
934 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14]
936 stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR]
940 #if defined(CONFIG_VMAP_STACK) || defined(CONFIG_SHADOW_CALL_STACK)
941 ldrb w4, [x19, #SDEI_EVENT_PRIORITY]
944 #ifdef CONFIG_VMAP_STACK
946 * entry.S may have been using sp as a scratch register, find whether
947 * this is a normal or critical event and switch to the appropriate
948 * stack for this CPU.
951 ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6
953 1: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6
954 2: mov x6, #SDEI_STACK_SIZE
959 #ifdef CONFIG_SHADOW_CALL_STACK
960 /* Use a separate shadow call stack for normal and critical events */
962 ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_normal_ptr, tmp=x6
964 3: ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_critical_ptr, tmp=x6
969 * We may have interrupted userspace, or a guest, or exit-from or
970 * return-to either of these. We can't trust sp_el0, restore it.
973 ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1
976 /* If we interrupted the kernel point to the previous stack/frame. */
980 csel x29, x29, xzr, eq // fp, or zero
981 csel x4, x2, xzr, eq // elr, or zero
983 stp x29, x4, [sp, #-16]!
986 add x0, x19, #SDEI_EVENT_INTREGS
991 /* restore regs >x17 that we clobbered */
992 mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline
993 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14]
994 ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9]
995 ldp lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR]
998 mov x1, x0 // address to complete_and_resume
999 /* x0 = (x0 <= 1) ? EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME */
1001 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE
1002 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME
1005 ldr_l x2, sdei_exit_mode
1007 alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0
1008 sdei_handler_exit exit_mode=x2
1009 alternative_else_nop_endif
1011 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1012 tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline
1015 SYM_CODE_END(__sdei_asm_handler)
1016 NOKPROBE(__sdei_asm_handler)
1017 #endif /* CONFIG_ARM_SDE_INTERFACE */