1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Low-level exception handling code
5 * Copyright (C) 2012 ARM Ltd.
6 * Authors: Catalin Marinas <catalin.marinas@arm.com>
7 * Will Deacon <will.deacon@arm.com>
10 #include <linux/arm-smccc.h>
11 #include <linux/init.h>
12 #include <linux/linkage.h>
14 #include <asm/alternative.h>
15 #include <asm/assembler.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/asm_pointer_auth.h>
19 #include <asm/cpufeature.h>
20 #include <asm/errno.h>
23 #include <asm/memory.h>
25 #include <asm/processor.h>
26 #include <asm/ptrace.h>
28 #include <asm/thread_info.h>
29 #include <asm/asm-uaccess.h>
30 #include <asm/unistd.h>
33 * Context tracking subsystem. Used to instrument transitions
34 * between user and kernel mode.
36 .macro ct_user_exit_irqoff
37 #ifdef CONFIG_CONTEXT_TRACKING
38 bl enter_from_user_mode
43 #ifdef CONFIG_CONTEXT_TRACKING
44 bl context_tracking_user_enter
49 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
63 .macro kernel_ventry, el, label, regsize = 64
65 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
67 alternative_if ARM64_UNMAP_KERNEL_AT_EL0
74 alternative_else_nop_endif
78 sub sp, sp, #S_FRAME_SIZE
79 #ifdef CONFIG_VMAP_STACK
81 * Test whether the SP has overflowed, without corrupting a GPR.
82 * Task and IRQ stacks are aligned so that SP & (1 << THREAD_SHIFT)
83 * should always be zero.
85 add sp, sp, x0 // sp' = sp + x0
86 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp
87 tbnz x0, #THREAD_SHIFT, 0f
88 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0
89 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp
94 * Either we've just detected an overflow, or we've taken an exception
95 * while on the overflow stack. Either way, we won't return to
96 * userspace, and can clobber EL0 registers to free up GPRs.
99 /* Stash the original SP (minus S_FRAME_SIZE) in tpidr_el0. */
102 /* Recover the original x0 value and stash it in tpidrro_el0 */
106 /* Switch to the overflow stack */
107 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0
110 * Check whether we were already on the overflow stack. This may happen
111 * after panic() re-enables interrupts.
113 mrs x0, tpidr_el0 // sp of interrupted context
114 sub x0, sp, x0 // delta with top of overflow stack
115 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range?
116 b.ne __bad_stack // no? -> bad stack pointer
118 /* We were already on the overflow stack. Restore sp/x0 and carry on. */
125 .macro tramp_alias, dst, sym
126 mov_q \dst, TRAMP_VALIAS
127 add \dst, \dst, #(\sym - .entry.tramp.text)
131 * This macro corrupts x0-x3. It is the caller's duty to save/restore
134 .macro apply_ssbd, state, tmp1, tmp2
135 #ifdef CONFIG_ARM64_SSBD
136 alternative_cb arm64_enable_wa2_handling
137 b .L__asm_ssbd_skip\@
139 ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1
140 cbz \tmp2, .L__asm_ssbd_skip\@
141 ldr \tmp2, [tsk, #TSK_TI_FLAGS]
142 tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@
143 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2
145 alternative_cb arm64_update_smccc_conduit
146 nop // Patched to SMC/HVC #0
152 .macro kernel_entry, el, regsize = 64
154 mov w0, w0 // zero upper 32 bits of x0
156 stp x0, x1, [sp, #16 * 0]
157 stp x2, x3, [sp, #16 * 1]
158 stp x4, x5, [sp, #16 * 2]
159 stp x6, x7, [sp, #16 * 3]
160 stp x8, x9, [sp, #16 * 4]
161 stp x10, x11, [sp, #16 * 5]
162 stp x12, x13, [sp, #16 * 6]
163 stp x14, x15, [sp, #16 * 7]
164 stp x16, x17, [sp, #16 * 8]
165 stp x18, x19, [sp, #16 * 9]
166 stp x20, x21, [sp, #16 * 10]
167 stp x22, x23, [sp, #16 * 11]
168 stp x24, x25, [sp, #16 * 12]
169 stp x26, x27, [sp, #16 * 13]
170 stp x28, x29, [sp, #16 * 14]
175 ldr_this_cpu tsk, __entry_task, x20
179 * Ensure MDSCR_EL1.SS is clear, since we can unmask debug exceptions
182 ldr x19, [tsk, #TSK_TI_FLAGS]
183 disable_step_tsk x19, x20
185 apply_ssbd 1, x22, x23
187 ptrauth_keys_install_kernel tsk, x20, x22, x23
191 add x21, sp, #S_FRAME_SIZE
193 /* Save the task's original addr_limit and set USER_DS */
194 ldr x20, [tsk, #TSK_TI_ADDR_LIMIT]
195 str x20, [sp, #S_ORIG_ADDR_LIMIT]
197 str x20, [tsk, #TSK_TI_ADDR_LIMIT]
198 /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */
199 .endif /* \el == 0 */
202 stp lr, x21, [sp, #S_LR]
205 * In order to be able to dump the contents of struct pt_regs at the
206 * time the exception was taken (in case we attempt to walk the call
207 * stack later), chain it together with the stack frames.
210 stp xzr, xzr, [sp, #S_STACKFRAME]
212 stp x29, x22, [sp, #S_STACKFRAME]
214 add x29, sp, #S_STACKFRAME
216 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
217 alternative_if_not ARM64_HAS_PAN
218 bl __swpan_entry_el\el
219 alternative_else_nop_endif
222 stp x22, x23, [sp, #S_PC]
224 /* Not in a syscall by default (el0_svc overwrites for real syscall) */
227 str w21, [sp, #S_SYSCALLNO]
231 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
232 mrs_s x20, SYS_ICC_PMR_EL1
233 str x20, [sp, #S_PMR_SAVE]
234 alternative_else_nop_endif
237 * Registers that may be useful after this macro is invoked:
242 * x23 - aborted PSTATE
246 .macro kernel_exit, el
250 /* Restore the task's original addr_limit. */
251 ldr x20, [sp, #S_ORIG_ADDR_LIMIT]
252 str x20, [tsk, #TSK_TI_ADDR_LIMIT]
254 /* No need to restore UAO, it will be restored from SPSR_EL1 */
258 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
259 ldr x20, [sp, #S_PMR_SAVE]
260 msr_s SYS_ICC_PMR_EL1, x20
261 mrs_s x21, SYS_ICC_CTLR_EL1
262 tbz x21, #6, .L__skip_pmr_sync\@ // Check for ICC_CTLR_EL1.PMHE
263 dsb sy // Ensure priority change is seen by redistributor
265 alternative_else_nop_endif
267 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
272 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
273 alternative_if_not ARM64_HAS_PAN
274 bl __swpan_exit_el\el
275 alternative_else_nop_endif
279 ldr x23, [sp, #S_SP] // load return stack pointer
281 tst x22, #PSR_MODE32_BIT // native task?
284 #ifdef CONFIG_ARM64_ERRATUM_845719
285 alternative_if ARM64_WORKAROUND_845719
286 #ifdef CONFIG_PID_IN_CONTEXTIDR
287 mrs x29, contextidr_el1
288 msr contextidr_el1, x29
290 msr contextidr_el1, xzr
292 alternative_else_nop_endif
297 /* No kernel C function calls after this as user keys are set. */
298 ptrauth_keys_install_user tsk, x0, x1, x2
303 msr elr_el1, x21 // set up the return data
305 ldp x0, x1, [sp, #16 * 0]
306 ldp x2, x3, [sp, #16 * 1]
307 ldp x4, x5, [sp, #16 * 2]
308 ldp x6, x7, [sp, #16 * 3]
309 ldp x8, x9, [sp, #16 * 4]
310 ldp x10, x11, [sp, #16 * 5]
311 ldp x12, x13, [sp, #16 * 6]
312 ldp x14, x15, [sp, #16 * 7]
313 ldp x16, x17, [sp, #16 * 8]
314 ldp x18, x19, [sp, #16 * 9]
315 ldp x20, x21, [sp, #16 * 10]
316 ldp x22, x23, [sp, #16 * 11]
317 ldp x24, x25, [sp, #16 * 12]
318 ldp x26, x27, [sp, #16 * 13]
319 ldp x28, x29, [sp, #16 * 14]
321 add sp, sp, #S_FRAME_SIZE // restore sp
324 alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0
325 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
328 tramp_alias x30, tramp_exit_native
331 tramp_alias x30, tramp_exit_compat
340 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
342 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from
343 * EL0, there is no need to check the state of TTBR0_EL1 since
344 * accesses are always enabled.
345 * Note that the meaning of this bit differs from the ARMv8.1 PAN
346 * feature as all TTBR0_EL1 accesses are disabled, not just those to
349 SYM_CODE_START_LOCAL(__swpan_entry_el1)
351 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID
352 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR
353 b.eq 1f // TTBR0 access already disabled
354 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR
355 SYM_INNER_LABEL(__swpan_entry_el0, SYM_L_LOCAL)
356 __uaccess_ttbr0_disable x21
358 SYM_CODE_END(__swpan_entry_el1)
361 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR
364 SYM_CODE_START_LOCAL(__swpan_exit_el1)
365 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set
366 __uaccess_ttbr0_enable x0, x1
367 1: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
369 SYM_CODE_END(__swpan_exit_el1)
371 SYM_CODE_START_LOCAL(__swpan_exit_el0)
372 __uaccess_ttbr0_enable x0, x1
374 * Enable errata workarounds only if returning to user. The only
375 * workaround currently required for TTBR0_EL1 changes are for the
376 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
379 b post_ttbr_update_workaround
380 SYM_CODE_END(__swpan_exit_el0)
383 .macro irq_stack_entry
384 mov x19, sp // preserve the original sp
385 #ifdef CONFIG_SHADOW_CALL_STACK
386 mov x24, scs_sp // preserve the original shadow stack
390 * Compare sp with the base of the task stack.
391 * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack,
392 * and should switch to the irq stack.
394 ldr x25, [tsk, TSK_STACK]
396 and x25, x25, #~(THREAD_SIZE - 1)
399 ldr_this_cpu x25, irq_stack_ptr, x26
400 mov x26, #IRQ_STACK_SIZE
403 /* switch to the irq stack */
406 #ifdef CONFIG_SHADOW_CALL_STACK
407 /* also switch to the irq shadow stack */
408 adr_this_cpu scs_sp, irq_shadow_call_stack, x26
415 * The callee-saved regs (x19-x29) should be preserved between
416 * irq_stack_entry and irq_stack_exit, but note that kernel_entry
417 * uses x20-x23 to store data for later use.
419 .macro irq_stack_exit
421 #ifdef CONFIG_SHADOW_CALL_STACK
426 /* GPRs used by entry code */
427 tsk .req x28 // current thread_info
430 * Interrupt handling.
433 ldr_l x1, handle_arch_irq
440 #ifdef CONFIG_ARM64_PSEUDO_NMI
442 * Set res to 0 if irqs were unmasked in interrupted context.
443 * Otherwise set res to non-0 value.
445 .macro test_irqs_unmasked res:req, pmr:req
446 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
447 sub \res, \pmr, #GIC_PRIO_IRQON
454 .macro gic_prio_kentry_setup, tmp:req
455 #ifdef CONFIG_ARM64_PSEUDO_NMI
456 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
457 mov \tmp, #(GIC_PRIO_PSR_I_SET | GIC_PRIO_IRQON)
458 msr_s SYS_ICC_PMR_EL1, \tmp
459 alternative_else_nop_endif
463 .macro gic_prio_irq_setup, pmr:req, tmp:req
464 #ifdef CONFIG_ARM64_PSEUDO_NMI
465 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
466 orr \tmp, \pmr, #GIC_PRIO_PSR_I_SET
467 msr_s SYS_ICC_PMR_EL1, \tmp
468 alternative_else_nop_endif
477 .pushsection ".entry.text", "ax"
480 SYM_CODE_START(vectors)
481 kernel_ventry 1, sync_invalid // Synchronous EL1t
482 kernel_ventry 1, irq_invalid // IRQ EL1t
483 kernel_ventry 1, fiq_invalid // FIQ EL1t
484 kernel_ventry 1, error_invalid // Error EL1t
486 kernel_ventry 1, sync // Synchronous EL1h
487 kernel_ventry 1, irq // IRQ EL1h
488 kernel_ventry 1, fiq_invalid // FIQ EL1h
489 kernel_ventry 1, error // Error EL1h
491 kernel_ventry 0, sync // Synchronous 64-bit EL0
492 kernel_ventry 0, irq // IRQ 64-bit EL0
493 kernel_ventry 0, fiq_invalid // FIQ 64-bit EL0
494 kernel_ventry 0, error // Error 64-bit EL0
497 kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0
498 kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0
499 kernel_ventry 0, fiq_invalid_compat, 32 // FIQ 32-bit EL0
500 kernel_ventry 0, error_compat, 32 // Error 32-bit EL0
502 kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0
503 kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0
504 kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0
505 kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0
507 SYM_CODE_END(vectors)
509 #ifdef CONFIG_VMAP_STACK
511 * We detected an overflow in kernel_ventry, which switched to the
512 * overflow stack. Stash the exception regs, and head to our overflow
516 /* Restore the original x0 value */
520 * Store the original GPRs to the new stack. The orginal SP (minus
521 * S_FRAME_SIZE) was stashed in tpidr_el0 by kernel_ventry.
523 sub sp, sp, #S_FRAME_SIZE
526 add x0, x0, #S_FRAME_SIZE
529 /* Stash the regs for handle_bad_stack */
535 #endif /* CONFIG_VMAP_STACK */
538 * Invalid mode handlers
540 .macro inv_entry, el, reason, regsize = 64
541 kernel_entry \el, \regsize
549 SYM_CODE_START_LOCAL(el0_sync_invalid)
550 inv_entry 0, BAD_SYNC
551 SYM_CODE_END(el0_sync_invalid)
553 SYM_CODE_START_LOCAL(el0_irq_invalid)
555 SYM_CODE_END(el0_irq_invalid)
557 SYM_CODE_START_LOCAL(el0_fiq_invalid)
559 SYM_CODE_END(el0_fiq_invalid)
561 SYM_CODE_START_LOCAL(el0_error_invalid)
562 inv_entry 0, BAD_ERROR
563 SYM_CODE_END(el0_error_invalid)
566 SYM_CODE_START_LOCAL(el0_fiq_invalid_compat)
567 inv_entry 0, BAD_FIQ, 32
568 SYM_CODE_END(el0_fiq_invalid_compat)
571 SYM_CODE_START_LOCAL(el1_sync_invalid)
572 inv_entry 1, BAD_SYNC
573 SYM_CODE_END(el1_sync_invalid)
575 SYM_CODE_START_LOCAL(el1_irq_invalid)
577 SYM_CODE_END(el1_irq_invalid)
579 SYM_CODE_START_LOCAL(el1_fiq_invalid)
581 SYM_CODE_END(el1_fiq_invalid)
583 SYM_CODE_START_LOCAL(el1_error_invalid)
584 inv_entry 1, BAD_ERROR
585 SYM_CODE_END(el1_error_invalid)
591 SYM_CODE_START_LOCAL_NOALIGN(el1_sync)
596 SYM_CODE_END(el1_sync)
599 SYM_CODE_START_LOCAL_NOALIGN(el1_irq)
601 gic_prio_irq_setup pmr=x20, tmp=x1
604 #ifdef CONFIG_ARM64_PSEUDO_NMI
605 test_irqs_unmasked res=x0, pmr=x20
611 #ifdef CONFIG_TRACE_IRQFLAGS
612 bl trace_hardirqs_off
617 #ifdef CONFIG_PREEMPTION
618 ldr x24, [tsk, #TSK_TI_PREEMPT] // get preempt count
619 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
621 * DA_F were cleared at start of handling. If anything is set in DAIF,
622 * we come back from an NMI, so skip preemption
626 alternative_else_nop_endif
627 cbnz x24, 1f // preempt count != 0 || NMI return path
628 bl arm64_preempt_schedule_irq // irq en/disable is done inside
632 #ifdef CONFIG_ARM64_PSEUDO_NMI
634 * When using IRQ priority masking, we can get spurious interrupts while
635 * PMR is set to GIC_PRIO_IRQOFF. An NMI might also have occurred in a
636 * section with interrupts disabled. Skip tracing in those cases.
638 test_irqs_unmasked res=x0, pmr=x20
644 #ifdef CONFIG_TRACE_IRQFLAGS
645 #ifdef CONFIG_ARM64_PSEUDO_NMI
646 test_irqs_unmasked res=x0, pmr=x20
654 SYM_CODE_END(el1_irq)
660 SYM_CODE_START_LOCAL_NOALIGN(el0_sync)
665 SYM_CODE_END(el0_sync)
669 SYM_CODE_START_LOCAL_NOALIGN(el0_sync_compat)
672 bl el0_sync_compat_handler
674 SYM_CODE_END(el0_sync_compat)
677 SYM_CODE_START_LOCAL_NOALIGN(el0_irq_compat)
680 SYM_CODE_END(el0_irq_compat)
682 SYM_CODE_START_LOCAL_NOALIGN(el0_error_compat)
685 SYM_CODE_END(el0_error_compat)
689 SYM_CODE_START_LOCAL_NOALIGN(el0_irq)
692 gic_prio_irq_setup pmr=x20, tmp=x0
696 #ifdef CONFIG_TRACE_IRQFLAGS
697 bl trace_hardirqs_off
700 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
702 bl do_el0_irq_bp_hardening
707 #ifdef CONFIG_TRACE_IRQFLAGS
711 SYM_CODE_END(el0_irq)
713 SYM_CODE_START_LOCAL(el1_error)
716 gic_prio_kentry_setup tmp=x2
721 SYM_CODE_END(el1_error)
723 SYM_CODE_START_LOCAL(el0_error)
727 gic_prio_kentry_setup tmp=x2
735 SYM_CODE_END(el0_error)
738 * "slow" syscall return path.
740 SYM_CODE_START_LOCAL(ret_to_user)
742 gic_prio_kentry_setup tmp=x3
743 ldr x1, [tsk, #TSK_TI_FLAGS]
744 and x2, x1, #_TIF_WORK_MASK
745 cbnz x2, work_pending
747 enable_step_tsk x1, x2
748 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK
754 * Ok, we need to do extra processing, enter the slow path.
759 #ifdef CONFIG_TRACE_IRQFLAGS
760 bl trace_hardirqs_on // enabled while in userspace
762 ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for single-step
764 SYM_CODE_END(ret_to_user)
766 .popsection // .entry.text
768 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
770 * Exception vectors trampoline.
772 .pushsection ".entry.tramp.text", "ax"
774 .macro tramp_map_kernel, tmp
776 add \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE)
777 bic \tmp, \tmp, #USER_ASID_FLAG
779 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
780 alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003
781 /* ASID already in \tmp[63:48] */
782 movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12)
783 movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12)
784 /* 2MB boundary containing the vectors, so we nobble the walk cache */
785 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12)
789 alternative_else_nop_endif
790 #endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */
793 .macro tramp_unmap_kernel, tmp
795 sub \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE)
796 orr \tmp, \tmp, #USER_ASID_FLAG
799 * We avoid running the post_ttbr_update_workaround here because
800 * it's only needed by Cavium ThunderX, which requires KPTI to be
805 .macro tramp_ventry, regsize = 64
809 msr tpidrro_el0, x30 // Restored in kernel_ventry
812 * Defend against branch aliasing attacks by pushing a dummy
813 * entry onto the return stack and using a RET instruction to
814 * enter the full-fat kernel vectors.
820 #ifdef CONFIG_RANDOMIZE_BASE
821 adr x30, tramp_vectors + PAGE_SIZE
822 alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003
827 alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM
828 prfm plil1strm, [x30, #(1b - tramp_vectors)]
829 alternative_else_nop_endif
831 add x30, x30, #(1b - tramp_vectors)
836 .macro tramp_exit, regsize = 64
837 adr x30, tramp_vectors
839 tramp_unmap_kernel x30
848 SYM_CODE_START_NOALIGN(tramp_vectors)
860 SYM_CODE_END(tramp_vectors)
862 SYM_CODE_START(tramp_exit_native)
864 SYM_CODE_END(tramp_exit_native)
866 SYM_CODE_START(tramp_exit_compat)
868 SYM_CODE_END(tramp_exit_compat)
871 .popsection // .entry.tramp.text
872 #ifdef CONFIG_RANDOMIZE_BASE
873 .pushsection ".rodata", "a"
875 SYM_DATA_START(__entry_tramp_data_start)
877 SYM_DATA_END(__entry_tramp_data_start)
878 .popsection // .rodata
879 #endif /* CONFIG_RANDOMIZE_BASE */
880 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
883 * Register switch for AArch64. The callee-saved registers need to be saved
884 * and restored. On entry:
885 * x0 = previous task_struct (must be preserved across the switch)
886 * x1 = next task_struct
887 * Previous and next are guaranteed not to be the same.
890 SYM_FUNC_START(cpu_switch_to)
891 mov x10, #THREAD_CPU_CONTEXT
894 stp x19, x20, [x8], #16 // store callee-saved registers
895 stp x21, x22, [x8], #16
896 stp x23, x24, [x8], #16
897 stp x25, x26, [x8], #16
898 stp x27, x28, [x8], #16
899 stp x29, x9, [x8], #16
902 ldp x19, x20, [x8], #16 // restore callee-saved registers
903 ldp x21, x22, [x8], #16
904 ldp x23, x24, [x8], #16
905 ldp x25, x26, [x8], #16
906 ldp x27, x28, [x8], #16
907 ldp x29, x9, [x8], #16
911 ptrauth_keys_install_kernel x1, x8, x9, x10
915 SYM_FUNC_END(cpu_switch_to)
916 NOKPROBE(cpu_switch_to)
919 * This is how we return from a fork.
921 SYM_CODE_START(ret_from_fork)
923 cbz x19, 1f // not a kernel thread
926 1: get_current_task tsk
928 SYM_CODE_END(ret_from_fork)
929 NOKPROBE(ret_from_fork)
931 #ifdef CONFIG_ARM_SDE_INTERFACE
933 #include <asm/sdei.h>
934 #include <uapi/linux/arm_sdei.h>
936 .macro sdei_handler_exit exit_mode
937 /* On success, this call never returns... */
938 cmp \exit_mode, #SDEI_EXIT_SMC
946 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
948 * The regular SDEI entry point may have been unmapped along with the rest of
949 * the kernel. This trampoline restores the kernel mapping to make the x1 memory
950 * argument accessible.
952 * This clobbers x4, __sdei_handler() will restore this from firmware's
956 .pushsection ".entry.tramp.text", "ax"
957 SYM_CODE_START(__sdei_asm_entry_trampoline)
959 tbz x4, #USER_ASID_BIT, 1f
961 tramp_map_kernel tmp=x4
966 * Use reg->interrupted_regs.addr_limit to remember whether to unmap
967 * the kernel on exit.
969 1: str x4, [x1, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)]
971 #ifdef CONFIG_RANDOMIZE_BASE
972 adr x4, tramp_vectors + PAGE_SIZE
973 add x4, x4, #:lo12:__sdei_asm_trampoline_next_handler
976 ldr x4, =__sdei_asm_handler
979 SYM_CODE_END(__sdei_asm_entry_trampoline)
980 NOKPROBE(__sdei_asm_entry_trampoline)
983 * Make the exit call and restore the original ttbr1_el1
985 * x0 & x1: setup for the exit API call
987 * x4: struct sdei_registered_event argument from registration time.
989 SYM_CODE_START(__sdei_asm_exit_trampoline)
990 ldr x4, [x4, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)]
993 tramp_unmap_kernel tmp=x4
995 1: sdei_handler_exit exit_mode=x2
996 SYM_CODE_END(__sdei_asm_exit_trampoline)
997 NOKPROBE(__sdei_asm_exit_trampoline)
999 .popsection // .entry.tramp.text
1000 #ifdef CONFIG_RANDOMIZE_BASE
1001 .pushsection ".rodata", "a"
1002 SYM_DATA_START(__sdei_asm_trampoline_next_handler)
1003 .quad __sdei_asm_handler
1004 SYM_DATA_END(__sdei_asm_trampoline_next_handler)
1005 .popsection // .rodata
1006 #endif /* CONFIG_RANDOMIZE_BASE */
1007 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1010 * Software Delegated Exception entry point.
1013 * x1: struct sdei_registered_event argument from registration time.
1014 * x2: interrupted PC
1015 * x3: interrupted PSTATE
1016 * x4: maybe clobbered by the trampoline
1018 * Firmware has preserved x0->x17 for us, we must save/restore the rest to
1019 * follow SMC-CC. We save (or retrieve) all the registers as the handler may
1022 SYM_CODE_START(__sdei_asm_handler)
1023 stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC]
1024 stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2]
1025 stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3]
1026 stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4]
1027 stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5]
1028 stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6]
1029 stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7]
1030 stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8]
1031 stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9]
1032 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10]
1033 stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11]
1034 stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12]
1035 stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13]
1036 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14]
1038 stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR]
1042 #if defined(CONFIG_VMAP_STACK) || defined(CONFIG_SHADOW_CALL_STACK)
1043 ldrb w4, [x19, #SDEI_EVENT_PRIORITY]
1046 #ifdef CONFIG_VMAP_STACK
1048 * entry.S may have been using sp as a scratch register, find whether
1049 * this is a normal or critical event and switch to the appropriate
1050 * stack for this CPU.
1053 ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6
1055 1: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6
1056 2: mov x6, #SDEI_STACK_SIZE
1061 #ifdef CONFIG_SHADOW_CALL_STACK
1062 /* Use a separate shadow call stack for normal and critical events */
1064 adr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_normal, tmp=x6
1066 3: adr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_critical, tmp=x6
1071 * We may have interrupted userspace, or a guest, or exit-from or
1072 * return-to either of these. We can't trust sp_el0, restore it.
1075 ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1
1078 /* If we interrupted the kernel point to the previous stack/frame. */
1082 csel x29, x29, xzr, eq // fp, or zero
1083 csel x4, x2, xzr, eq // elr, or zero
1085 stp x29, x4, [sp, #-16]!
1088 add x0, x19, #SDEI_EVENT_INTREGS
1093 /* restore regs >x17 that we clobbered */
1094 mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline
1095 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14]
1096 ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9]
1097 ldp lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR]
1100 mov x1, x0 // address to complete_and_resume
1101 /* x0 = (x0 <= 1) ? EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME */
1103 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE
1104 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME
1107 ldr_l x2, sdei_exit_mode
1109 alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0
1110 sdei_handler_exit exit_mode=x2
1111 alternative_else_nop_endif
1113 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1114 tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline
1117 SYM_CODE_END(__sdei_asm_handler)
1118 NOKPROBE(__sdei_asm_handler)
1119 #endif /* CONFIG_ARM_SDE_INTERFACE */