2 * Low-level exception handling code
4 * Copyright (C) 2012 ARM Ltd.
5 * Authors: Catalin Marinas <catalin.marinas@arm.com>
6 * Will Deacon <will.deacon@arm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/init.h>
22 #include <linux/linkage.h>
24 #include <asm/assembler.h>
25 #include <asm/asm-offsets.h>
26 #include <asm/errno.h>
28 #include <asm/thread_info.h>
29 #include <asm/unistd.h>
30 #include <asm/unistd32.h>
41 .macro kernel_entry, el, regsize = 64
42 sub sp, sp, #S_FRAME_SIZE - S_LR // room for LR, SP, SPSR, ELR
44 mov w0, w0 // zero upper 32 bits of x0
64 add x21, sp, #S_FRAME_SIZE
68 stp lr, x21, [sp, #S_LR]
69 stp x22, x23, [sp, #S_PC]
72 * Set syscallno to -1 by default (overridden later if real syscall).
76 str x21, [sp, #S_SYSCALLNO]
80 * Registers that may be useful after this macro is invoked:
84 * x23 - aborted PSTATE
88 .macro kernel_exit, el, ret = 0
89 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
91 ldr x23, [sp, #S_SP] // load return stack pointer
94 ldr x1, [sp, #S_X1] // preserve x0 (syscall return)
99 pop x2, x3 // load the rest of the registers
103 msr elr_el1, x21 // set up the return data
118 ldr lr, [sp], #S_FRAME_SIZE - S_LR // load LR and restore SP
119 eret // return to kernel
122 .macro get_thread_info, rd
124 and \rd, \rd, #~(THREAD_SIZE - 1) // top of stack
128 * These are the registers used in the syscall handler, and allow us to
129 * have in theory up to 7 arguments to a function - x0 to x6.
131 * x7 is reserved for the system call number in 32-bit mode.
133 sc_nr .req x25 // number of system calls
134 scno .req x26 // syscall number
135 stbl .req x27 // syscall table pointer
136 tsk .req x28 // current thread_info
139 * Interrupt handling.
142 ldr x1, handle_arch_irq
155 ventry el1_sync_invalid // Synchronous EL1t
156 ventry el1_irq_invalid // IRQ EL1t
157 ventry el1_fiq_invalid // FIQ EL1t
158 ventry el1_error_invalid // Error EL1t
160 ventry el1_sync // Synchronous EL1h
161 ventry el1_irq // IRQ EL1h
162 ventry el1_fiq_invalid // FIQ EL1h
163 ventry el1_error_invalid // Error EL1h
165 ventry el0_sync // Synchronous 64-bit EL0
166 ventry el0_irq // IRQ 64-bit EL0
167 ventry el0_fiq_invalid // FIQ 64-bit EL0
168 ventry el0_error_invalid // Error 64-bit EL0
171 ventry el0_sync_compat // Synchronous 32-bit EL0
172 ventry el0_irq_compat // IRQ 32-bit EL0
173 ventry el0_fiq_invalid_compat // FIQ 32-bit EL0
174 ventry el0_error_invalid_compat // Error 32-bit EL0
176 ventry el0_sync_invalid // Synchronous 32-bit EL0
177 ventry el0_irq_invalid // IRQ 32-bit EL0
178 ventry el0_fiq_invalid // FIQ 32-bit EL0
179 ventry el0_error_invalid // Error 32-bit EL0
184 * Invalid mode handlers
186 .macro inv_entry, el, reason, regsize = 64
187 kernel_entry el, \regsize
195 inv_entry 0, BAD_SYNC
196 ENDPROC(el0_sync_invalid)
200 ENDPROC(el0_irq_invalid)
204 ENDPROC(el0_fiq_invalid)
207 inv_entry 0, BAD_ERROR
208 ENDPROC(el0_error_invalid)
211 el0_fiq_invalid_compat:
212 inv_entry 0, BAD_FIQ, 32
213 ENDPROC(el0_fiq_invalid_compat)
215 el0_error_invalid_compat:
216 inv_entry 0, BAD_ERROR, 32
217 ENDPROC(el0_error_invalid_compat)
221 inv_entry 1, BAD_SYNC
222 ENDPROC(el1_sync_invalid)
226 ENDPROC(el1_irq_invalid)
230 ENDPROC(el1_fiq_invalid)
233 inv_entry 1, BAD_ERROR
234 ENDPROC(el1_error_invalid)
242 mrs x1, esr_el1 // read the syndrome register
243 lsr x24, x1, #ESR_EL1_EC_SHIFT // exception class
244 cmp x24, #ESR_EL1_EC_DABT_EL1 // data abort in EL1
246 cmp x24, #ESR_EL1_EC_SYS64 // configurable trap
248 cmp x24, #ESR_EL1_EC_SP_ALIGN // stack alignment exception
250 cmp x24, #ESR_EL1_EC_PC_ALIGN // pc alignment exception
252 cmp x24, #ESR_EL1_EC_UNKNOWN // unknown exception in EL1
254 cmp x24, #ESR_EL1_EC_BREAKPT_EL1 // debug exception in EL1
259 * Data abort handling
262 enable_dbg_if_not_stepping x2
263 // re-enable interrupts if they were enabled in the aborted context
264 tbnz x23, #7, 1f // PSR_I_BIT
267 mov x2, sp // struct pt_regs
270 // disable interrupts before pulling preserved data off the stack
275 * Stack or PC alignment exception handling
283 * Undefined instruction
289 * Debug exception handling
291 tbz x24, #0, el1_inv // EL1 only
293 mov x2, sp // struct pt_regs
294 bl do_debug_exception
298 // TODO: add support for undefined instructions in kernel mode
308 enable_dbg_if_not_stepping x0
309 #ifdef CONFIG_TRACE_IRQFLAGS
310 bl trace_hardirqs_off
315 #ifdef CONFIG_PREEMPT
317 ldr w24, [tsk, #TI_PREEMPT] // restore preempt count
318 cbnz w24, 1f // preempt count != 0
319 ldr x0, [tsk, #TI_FLAGS] // get flags
320 tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling?
324 #ifdef CONFIG_TRACE_IRQFLAGS
330 #ifdef CONFIG_PREEMPT
334 bl preempt_schedule_irq // irq en/disable is done inside
335 ldr x0, [tsk, #TI_FLAGS] // get new tasks TI_FLAGS
336 tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling?
346 mrs x25, esr_el1 // read the syndrome register
347 lsr x24, x25, #ESR_EL1_EC_SHIFT // exception class
348 cmp x24, #ESR_EL1_EC_SVC64 // SVC in 64-bit state
350 adr lr, ret_from_exception
351 cmp x24, #ESR_EL1_EC_DABT_EL0 // data abort in EL0
353 cmp x24, #ESR_EL1_EC_IABT_EL0 // instruction abort in EL0
355 cmp x24, #ESR_EL1_EC_FP_ASIMD // FP/ASIMD access
357 cmp x24, #ESR_EL1_EC_FP_EXC64 // FP/ASIMD exception
359 cmp x24, #ESR_EL1_EC_SYS64 // configurable trap
361 cmp x24, #ESR_EL1_EC_SP_ALIGN // stack alignment exception
363 cmp x24, #ESR_EL1_EC_PC_ALIGN // pc alignment exception
365 cmp x24, #ESR_EL1_EC_UNKNOWN // unknown exception in EL0
367 cmp x24, #ESR_EL1_EC_BREAKPT_EL0 // debug exception in EL0
375 mrs x25, esr_el1 // read the syndrome register
376 lsr x24, x25, #ESR_EL1_EC_SHIFT // exception class
377 cmp x24, #ESR_EL1_EC_SVC32 // SVC in 32-bit state
379 adr lr, ret_from_exception
380 cmp x24, #ESR_EL1_EC_DABT_EL0 // data abort in EL0
382 cmp x24, #ESR_EL1_EC_IABT_EL0 // instruction abort in EL0
384 cmp x24, #ESR_EL1_EC_FP_ASIMD // FP/ASIMD access
386 cmp x24, #ESR_EL1_EC_FP_EXC32 // FP/ASIMD exception
388 cmp x24, #ESR_EL1_EC_UNKNOWN // unknown exception in EL0
390 cmp x24, #ESR_EL1_EC_CP15_32 // CP15 MRC/MCR trap
392 cmp x24, #ESR_EL1_EC_CP15_64 // CP15 MRRC/MCRR trap
394 cmp x24, #ESR_EL1_EC_CP14_MR // CP14 MRC/MCR trap
396 cmp x24, #ESR_EL1_EC_CP14_LS // CP14 LDC/STC trap
398 cmp x24, #ESR_EL1_EC_CP14_64 // CP14 MRRC/MCRR trap
400 cmp x24, #ESR_EL1_EC_BREAKPT_EL0 // debug exception in EL0
405 * AArch32 syscall handling
407 adr stbl, compat_sys_call_table // load compat syscall table pointer
408 uxtw scno, w7 // syscall number in w7 (r7)
409 mov sc_nr, #__NR_compat_syscalls
420 * Data abort handling
423 bic x0, x0, #(0xff << 56)
427 // enable interrupts before calling the main handler
434 * Instruction abort handling
440 // enable interrupts before calling the main handler
442 orr x1, x25, #1 << 24 // use reserved ISS bit for instruction aborts
447 * Floating Point or Advanced SIMD access
454 * Floating Point or Advanced SIMD exception
461 * Stack or PC alignment exception handling
467 // enable interrupts before calling the main handler
474 * Undefined instruction
477 // enable interrupts before calling the main handler
482 * Debug exception handling
484 tbnz x24, #0, el0_inv // EL0 only
504 #ifdef CONFIG_TRACE_IRQFLAGS
505 bl trace_hardirqs_off
511 #ifdef CONFIG_TRACE_IRQFLAGS
518 * This is the return code to user mode for abort handlers
523 ENDPROC(ret_from_exception)
526 * Register switch for AArch64. The callee-saved registers need to be saved
527 * and restored. On entry:
528 * x0 = previous task_struct (must be preserved across the switch)
529 * x1 = next task_struct
530 * Previous and next are guaranteed not to be the same.
534 add x8, x0, #THREAD_CPU_CONTEXT
536 stp x19, x20, [x8], #16 // store callee-saved registers
537 stp x21, x22, [x8], #16
538 stp x23, x24, [x8], #16
539 stp x25, x26, [x8], #16
540 stp x27, x28, [x8], #16
541 stp x29, x9, [x8], #16
543 add x8, x1, #THREAD_CPU_CONTEXT
544 ldp x19, x20, [x8], #16 // restore callee-saved registers
545 ldp x21, x22, [x8], #16
546 ldp x23, x24, [x8], #16
547 ldp x25, x26, [x8], #16
548 ldp x27, x28, [x8], #16
549 ldp x29, x9, [x8], #16
553 ENDPROC(cpu_switch_to)
556 * This is the fast syscall return path. We do as little as possible here,
557 * and this includes saving x0 back into the kernel stack.
560 disable_irq // disable interrupts
561 ldr x1, [tsk, #TI_FLAGS]
562 and x2, x1, #_TIF_WORK_MASK
563 cbnz x2, fast_work_pending
564 tbz x1, #TIF_SINGLESTEP, fast_exit
568 kernel_exit 0, ret = 1
571 * Ok, we need to do extra processing, enter the slow path.
574 str x0, [sp, #S_X0] // returned x0
576 tbnz x1, #TIF_NEED_RESCHED, work_resched
577 /* TIF_SIGPENDING or TIF_NOTIFY_RESUME case */
578 ldr x2, [sp, #S_PSTATE]
580 tst x2, #PSR_MODE_MASK // user mode regs?
581 b.ne no_work_pending // returning to kernel
582 enable_irq // enable interrupts for do_notify_resume()
590 * "slow" syscall return path.
593 disable_irq // disable interrupts
594 ldr x1, [tsk, #TI_FLAGS]
595 and x2, x1, #_TIF_WORK_MASK
596 cbnz x2, work_pending
597 tbz x1, #TIF_SINGLESTEP, no_work_pending
601 kernel_exit 0, ret = 0
605 * This is how we return from a fork.
609 cbz x19, 1f // not a kernel thread
612 1: get_thread_info tsk
614 ENDPROC(ret_from_fork)
621 adrp stbl, sys_call_table // load syscall table pointer
622 uxtw scno, w8 // syscall number in w8
623 mov sc_nr, #__NR_syscalls
624 el0_svc_naked: // compat entry point
625 stp x0, scno, [sp, #S_ORIG_X0] // save the original x0 and syscall number
632 ldr x16, [tsk, #TI_FLAGS] // check for syscall tracing
633 tbnz x16, #TIF_SYSCALL_TRACE, __sys_trace // are we tracing syscalls?
634 adr lr, ret_fast_syscall // return address
635 cmp scno, sc_nr // check upper syscall limit
637 ldr x16, [stbl, scno, lsl #3] // address in the syscall table
638 br x16 // call sys_* routine
645 * This is the really slow path. We're going to be doing context
646 * switches, and waiting for our parent to respond.
650 mov w0, #0 // trace entry
652 adr lr, __sys_trace_return // return address
653 uxtw scno, w0 // syscall number (possibly new)
654 mov x1, sp // pointer to regs
655 cmp scno, sc_nr // check upper syscall limit
657 ldp x0, x1, [sp] // restore the syscall args
658 ldp x2, x3, [sp, #S_X2]
659 ldp x4, x5, [sp, #S_X4]
660 ldp x6, x7, [sp, #S_X6]
661 ldr x16, [stbl, scno, lsl #3] // address in the syscall table
662 br x16 // call sys_* routine
665 str x0, [sp] // save returned x0
667 mov w0, #1 // trace exit
672 * Special system call wrappers.
674 ENTRY(sys_rt_sigreturn_wrapper)
677 ENDPROC(sys_rt_sigreturn_wrapper)
679 ENTRY(handle_arch_irq)