1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Low-level exception handling code
5 * Copyright (C) 2012 ARM Ltd.
6 * Authors: Catalin Marinas <catalin.marinas@arm.com>
7 * Will Deacon <will.deacon@arm.com>
10 #include <linux/arm-smccc.h>
11 #include <linux/init.h>
12 #include <linux/linkage.h>
14 #include <asm/alternative.h>
15 #include <asm/assembler.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/asm_pointer_auth.h>
19 #include <asm/cpufeature.h>
20 #include <asm/errno.h>
23 #include <asm/memory.h>
25 #include <asm/processor.h>
26 #include <asm/ptrace.h>
28 #include <asm/thread_info.h>
29 #include <asm/asm-uaccess.h>
30 #include <asm/unistd.h>
33 * Context tracking and irqflag tracing need to instrument transitions between
34 * user and kernel mode.
36 .macro user_exit_irqoff
37 #if defined(CONFIG_CONTEXT_TRACKING) || defined(CONFIG_TRACE_IRQFLAGS)
38 bl enter_from_user_mode
42 .macro user_enter_irqoff
43 #if defined(CONFIG_CONTEXT_TRACKING) || defined(CONFIG_TRACE_IRQFLAGS)
49 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
63 .macro kernel_ventry, el, label, regsize = 64
65 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
67 alternative_if ARM64_UNMAP_KERNEL_AT_EL0
74 alternative_else_nop_endif
78 sub sp, sp, #PT_REGS_SIZE
79 #ifdef CONFIG_VMAP_STACK
81 * Test whether the SP has overflowed, without corrupting a GPR.
82 * Task and IRQ stacks are aligned so that SP & (1 << THREAD_SHIFT)
83 * should always be zero.
85 add sp, sp, x0 // sp' = sp + x0
86 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp
87 tbnz x0, #THREAD_SHIFT, 0f
88 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0
89 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp
94 * Either we've just detected an overflow, or we've taken an exception
95 * while on the overflow stack. Either way, we won't return to
96 * userspace, and can clobber EL0 registers to free up GPRs.
99 /* Stash the original SP (minus PT_REGS_SIZE) in tpidr_el0. */
102 /* Recover the original x0 value and stash it in tpidrro_el0 */
106 /* Switch to the overflow stack */
107 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0
110 * Check whether we were already on the overflow stack. This may happen
111 * after panic() re-enables interrupts.
113 mrs x0, tpidr_el0 // sp of interrupted context
114 sub x0, sp, x0 // delta with top of overflow stack
115 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range?
116 b.ne __bad_stack // no? -> bad stack pointer
118 /* We were already on the overflow stack. Restore sp/x0 and carry on. */
125 .macro tramp_alias, dst, sym
126 mov_q \dst, TRAMP_VALIAS
127 add \dst, \dst, #(\sym - .entry.tramp.text)
131 * This macro corrupts x0-x3. It is the caller's duty to save/restore
134 .macro apply_ssbd, state, tmp1, tmp2
135 alternative_cb spectre_v4_patch_fw_mitigation_enable
136 b .L__asm_ssbd_skip\@ // Patched to NOP
138 ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1
139 cbz \tmp2, .L__asm_ssbd_skip\@
140 ldr \tmp2, [tsk, #TSK_TI_FLAGS]
141 tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@
142 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2
144 alternative_cb spectre_v4_patch_fw_mitigation_conduit
145 nop // Patched to SMC/HVC #0
150 /* Check for MTE asynchronous tag check faults */
151 .macro check_mte_async_tcf, tmp, ti_flags
152 #ifdef CONFIG_ARM64_MTE
154 alternative_if_not ARM64_MTE
156 alternative_else_nop_endif
157 mrs_s \tmp, SYS_TFSRE0_EL1
158 tbz \tmp, #SYS_TFSR_EL1_TF0_SHIFT, 1f
159 /* Asynchronous TCF occurred for TTBR0 access, set the TI flag */
160 mov \tmp, #_TIF_MTE_ASYNC_FAULT
161 add \ti_flags, tsk, #TSK_TI_FLAGS
162 stset \tmp, [\ti_flags]
163 msr_s SYS_TFSRE0_EL1, xzr
168 /* Clear the MTE asynchronous tag check faults */
169 .macro clear_mte_async_tcf
170 #ifdef CONFIG_ARM64_MTE
171 alternative_if ARM64_MTE
173 msr_s SYS_TFSRE0_EL1, xzr
174 alternative_else_nop_endif
178 .macro mte_set_gcr, tmp, tmp2
179 #ifdef CONFIG_ARM64_MTE
181 * Calculate and set the exclude mask preserving
182 * the RRND (bit[16]) setting.
184 mrs_s \tmp2, SYS_GCR_EL1
185 bfi \tmp2, \tmp, #0, #16
186 msr_s SYS_GCR_EL1, \tmp2
190 .macro mte_set_kernel_gcr, tmp, tmp2
191 #ifdef CONFIG_KASAN_HW_TAGS
192 alternative_if_not ARM64_MTE
194 alternative_else_nop_endif
195 ldr_l \tmp, gcr_kernel_excl
197 mte_set_gcr \tmp, \tmp2
203 .macro mte_set_user_gcr, tsk, tmp, tmp2
204 #ifdef CONFIG_ARM64_MTE
205 alternative_if_not ARM64_MTE
207 alternative_else_nop_endif
208 ldr \tmp, [\tsk, #THREAD_GCR_EL1_USER]
210 mte_set_gcr \tmp, \tmp2
215 .macro kernel_entry, el, regsize = 64
217 mov w0, w0 // zero upper 32 bits of x0
219 stp x0, x1, [sp, #16 * 0]
220 stp x2, x3, [sp, #16 * 1]
221 stp x4, x5, [sp, #16 * 2]
222 stp x6, x7, [sp, #16 * 3]
223 stp x8, x9, [sp, #16 * 4]
224 stp x10, x11, [sp, #16 * 5]
225 stp x12, x13, [sp, #16 * 6]
226 stp x14, x15, [sp, #16 * 7]
227 stp x16, x17, [sp, #16 * 8]
228 stp x18, x19, [sp, #16 * 9]
229 stp x20, x21, [sp, #16 * 10]
230 stp x22, x23, [sp, #16 * 11]
231 stp x24, x25, [sp, #16 * 12]
232 stp x26, x27, [sp, #16 * 13]
233 stp x28, x29, [sp, #16 * 14]
238 ldr_this_cpu tsk, __entry_task, x20
242 * Ensure MDSCR_EL1.SS is clear, since we can unmask debug exceptions
245 ldr x19, [tsk, #TSK_TI_FLAGS]
246 disable_step_tsk x19, x20
248 /* Check for asynchronous tag check faults in user space */
249 check_mte_async_tcf x22, x23
250 apply_ssbd 1, x22, x23
252 #ifdef CONFIG_ARM64_PTR_AUTH
253 alternative_if ARM64_HAS_ADDRESS_AUTH
255 * Enable IA for in-kernel PAC if the task had it disabled. Although
256 * this could be implemented with an unconditional MRS which would avoid
257 * a load, this was measured to be slower on Cortex-A75 and Cortex-A76.
259 * Install the kernel IA key only if IA was enabled in the task. If IA
260 * was disabled on kernel exit then we would have left the kernel IA
261 * installed so there is no need to install it again.
263 ldr x0, [tsk, THREAD_SCTLR_USER]
264 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f
265 __ptrauth_keys_install_kernel_nosync tsk, x20, x22, x23
269 orr x0, x0, SCTLR_ELx_ENIA
273 alternative_else_nop_endif
276 mte_set_kernel_gcr x22, x23
280 add x21, sp, #PT_REGS_SIZE
282 .endif /* \el == 0 */
285 stp lr, x21, [sp, #S_LR]
288 * For exceptions from EL0, create a final frame record.
289 * For exceptions from EL1, create a synthetic frame record so the
290 * interrupted code shows up in the backtrace.
293 stp xzr, xzr, [sp, #S_STACKFRAME]
295 stp x29, x22, [sp, #S_STACKFRAME]
297 add x29, sp, #S_STACKFRAME
299 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
300 alternative_if_not ARM64_HAS_PAN
301 bl __swpan_entry_el\el
302 alternative_else_nop_endif
305 stp x22, x23, [sp, #S_PC]
307 /* Not in a syscall by default (el0_svc overwrites for real syscall) */
310 str w21, [sp, #S_SYSCALLNO]
314 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
315 mrs_s x20, SYS_ICC_PMR_EL1
316 str x20, [sp, #S_PMR_SAVE]
317 mov x20, #GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET
318 msr_s SYS_ICC_PMR_EL1, x20
319 alternative_else_nop_endif
321 /* Re-enable tag checking (TCO set on exception entry) */
322 #ifdef CONFIG_ARM64_MTE
323 alternative_if ARM64_MTE
325 alternative_else_nop_endif
329 * Registers that may be useful after this macro is invoked:
334 * x23 - aborted PSTATE
338 .macro kernel_exit, el
344 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
345 ldr x20, [sp, #S_PMR_SAVE]
346 msr_s SYS_ICC_PMR_EL1, x20
347 mrs_s x21, SYS_ICC_CTLR_EL1
348 tbz x21, #6, .L__skip_pmr_sync\@ // Check for ICC_CTLR_EL1.PMHE
349 dsb sy // Ensure priority change is seen by redistributor
351 alternative_else_nop_endif
353 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
355 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
356 alternative_if_not ARM64_HAS_PAN
357 bl __swpan_exit_el\el
358 alternative_else_nop_endif
362 ldr x23, [sp, #S_SP] // load return stack pointer
364 tst x22, #PSR_MODE32_BIT // native task?
367 #ifdef CONFIG_ARM64_ERRATUM_845719
368 alternative_if ARM64_WORKAROUND_845719
369 #ifdef CONFIG_PID_IN_CONTEXTIDR
370 mrs x29, contextidr_el1
371 msr contextidr_el1, x29
373 msr contextidr_el1, xzr
375 alternative_else_nop_endif
380 #ifdef CONFIG_ARM64_PTR_AUTH
381 alternative_if ARM64_HAS_ADDRESS_AUTH
383 * IA was enabled for in-kernel PAC. Disable it now if needed, or
384 * alternatively install the user's IA. All other per-task keys and
385 * SCTLR bits were updated on task switch.
387 * No kernel C function calls after this.
389 ldr x0, [tsk, THREAD_SCTLR_USER]
390 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f
391 __ptrauth_keys_install_user tsk, x0, x1, x2
395 bic x0, x0, SCTLR_ELx_ENIA
398 alternative_else_nop_endif
401 mte_set_user_gcr tsk, x0, x1
406 msr elr_el1, x21 // set up the return data
408 ldp x0, x1, [sp, #16 * 0]
409 ldp x2, x3, [sp, #16 * 1]
410 ldp x4, x5, [sp, #16 * 2]
411 ldp x6, x7, [sp, #16 * 3]
412 ldp x8, x9, [sp, #16 * 4]
413 ldp x10, x11, [sp, #16 * 5]
414 ldp x12, x13, [sp, #16 * 6]
415 ldp x14, x15, [sp, #16 * 7]
416 ldp x16, x17, [sp, #16 * 8]
417 ldp x18, x19, [sp, #16 * 9]
418 ldp x20, x21, [sp, #16 * 10]
419 ldp x22, x23, [sp, #16 * 11]
420 ldp x24, x25, [sp, #16 * 12]
421 ldp x26, x27, [sp, #16 * 13]
422 ldp x28, x29, [sp, #16 * 14]
424 add sp, sp, #PT_REGS_SIZE // restore sp
427 alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0
428 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
431 tramp_alias x30, tramp_exit_native
434 tramp_alias x30, tramp_exit_compat
438 /* Ensure any device/NC reads complete */
439 alternative_insn nop, "dmb sy", ARM64_WORKAROUND_1508412
446 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
448 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from
449 * EL0, there is no need to check the state of TTBR0_EL1 since
450 * accesses are always enabled.
451 * Note that the meaning of this bit differs from the ARMv8.1 PAN
452 * feature as all TTBR0_EL1 accesses are disabled, not just those to
455 SYM_CODE_START_LOCAL(__swpan_entry_el1)
457 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID
458 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR
459 b.eq 1f // TTBR0 access already disabled
460 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR
461 SYM_INNER_LABEL(__swpan_entry_el0, SYM_L_LOCAL)
462 __uaccess_ttbr0_disable x21
464 SYM_CODE_END(__swpan_entry_el1)
467 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR
470 SYM_CODE_START_LOCAL(__swpan_exit_el1)
471 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set
472 __uaccess_ttbr0_enable x0, x1
473 1: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
475 SYM_CODE_END(__swpan_exit_el1)
477 SYM_CODE_START_LOCAL(__swpan_exit_el0)
478 __uaccess_ttbr0_enable x0, x1
480 * Enable errata workarounds only if returning to user. The only
481 * workaround currently required for TTBR0_EL1 changes are for the
482 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
485 b post_ttbr_update_workaround
486 SYM_CODE_END(__swpan_exit_el0)
489 .macro irq_stack_entry
490 mov x19, sp // preserve the original sp
491 #ifdef CONFIG_SHADOW_CALL_STACK
492 mov x24, scs_sp // preserve the original shadow stack
496 * Compare sp with the base of the task stack.
497 * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack,
498 * and should switch to the irq stack.
500 ldr x25, [tsk, TSK_STACK]
502 and x25, x25, #~(THREAD_SIZE - 1)
505 ldr_this_cpu x25, irq_stack_ptr, x26
506 mov x26, #IRQ_STACK_SIZE
509 /* switch to the irq stack */
512 #ifdef CONFIG_SHADOW_CALL_STACK
513 /* also switch to the irq shadow stack */
514 ldr_this_cpu scs_sp, irq_shadow_call_stack_ptr, x26
521 * The callee-saved regs (x19-x29) should be preserved between
522 * irq_stack_entry and irq_stack_exit, but note that kernel_entry
523 * uses x20-x23 to store data for later use.
525 .macro irq_stack_exit
527 #ifdef CONFIG_SHADOW_CALL_STACK
532 /* GPRs used by entry code */
533 tsk .req x28 // current thread_info
536 * Interrupt handling.
538 .macro irq_handler, handler:req
546 .macro gic_prio_kentry_setup, tmp:req
547 #ifdef CONFIG_ARM64_PSEUDO_NMI
548 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
549 mov \tmp, #(GIC_PRIO_PSR_I_SET | GIC_PRIO_IRQON)
550 msr_s SYS_ICC_PMR_EL1, \tmp
551 alternative_else_nop_endif
555 .macro el1_interrupt_handler, handler:req
559 bl enter_el1_irq_or_nmi
563 #ifdef CONFIG_PREEMPTION
564 ldr x24, [tsk, #TSK_TI_PREEMPT] // get preempt count
565 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
567 * DA were cleared at start of handling, and IF are cleared by
568 * the GIC irqchip driver using gic_arch_enable_irqs() for
569 * normal IRQs. If anything is set, it means we come back from
570 * an NMI instead of a normal IRQ, so skip preemption
574 alternative_else_nop_endif
575 cbnz x24, 1f // preempt count != 0 || NMI return path
576 bl arm64_preempt_schedule_irq // irq en/disable is done inside
581 bl exit_el1_irq_or_nmi
584 .macro el0_interrupt_handler, handler:req
589 bl do_el0_irq_bp_hardening
599 .pushsection ".entry.text", "ax"
602 SYM_CODE_START(vectors)
603 kernel_ventry 1, sync_invalid // Synchronous EL1t
604 kernel_ventry 1, irq_invalid // IRQ EL1t
605 kernel_ventry 1, fiq_invalid // FIQ EL1t
606 kernel_ventry 1, error_invalid // Error EL1t
608 kernel_ventry 1, sync // Synchronous EL1h
609 kernel_ventry 1, irq // IRQ EL1h
610 kernel_ventry 1, fiq // FIQ EL1h
611 kernel_ventry 1, error // Error EL1h
613 kernel_ventry 0, sync // Synchronous 64-bit EL0
614 kernel_ventry 0, irq // IRQ 64-bit EL0
615 kernel_ventry 0, fiq // FIQ 64-bit EL0
616 kernel_ventry 0, error // Error 64-bit EL0
619 kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0
620 kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0
621 kernel_ventry 0, fiq_compat, 32 // FIQ 32-bit EL0
622 kernel_ventry 0, error_compat, 32 // Error 32-bit EL0
624 kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0
625 kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0
626 kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0
627 kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0
629 SYM_CODE_END(vectors)
631 #ifdef CONFIG_VMAP_STACK
633 * We detected an overflow in kernel_ventry, which switched to the
634 * overflow stack. Stash the exception regs, and head to our overflow
638 /* Restore the original x0 value */
642 * Store the original GPRs to the new stack. The orginal SP (minus
643 * PT_REGS_SIZE) was stashed in tpidr_el0 by kernel_ventry.
645 sub sp, sp, #PT_REGS_SIZE
648 add x0, x0, #PT_REGS_SIZE
651 /* Stash the regs for handle_bad_stack */
657 #endif /* CONFIG_VMAP_STACK */
660 * Invalid mode handlers
662 .macro inv_entry, el, reason, regsize = 64
663 kernel_entry \el, \regsize
671 SYM_CODE_START_LOCAL(el0_sync_invalid)
672 inv_entry 0, BAD_SYNC
673 SYM_CODE_END(el0_sync_invalid)
675 SYM_CODE_START_LOCAL(el0_irq_invalid)
677 SYM_CODE_END(el0_irq_invalid)
679 SYM_CODE_START_LOCAL(el0_fiq_invalid)
681 SYM_CODE_END(el0_fiq_invalid)
683 SYM_CODE_START_LOCAL(el0_error_invalid)
684 inv_entry 0, BAD_ERROR
685 SYM_CODE_END(el0_error_invalid)
687 SYM_CODE_START_LOCAL(el1_sync_invalid)
688 inv_entry 1, BAD_SYNC
689 SYM_CODE_END(el1_sync_invalid)
691 SYM_CODE_START_LOCAL(el1_irq_invalid)
693 SYM_CODE_END(el1_irq_invalid)
695 SYM_CODE_START_LOCAL(el1_fiq_invalid)
697 SYM_CODE_END(el1_fiq_invalid)
699 SYM_CODE_START_LOCAL(el1_error_invalid)
700 inv_entry 1, BAD_ERROR
701 SYM_CODE_END(el1_error_invalid)
707 SYM_CODE_START_LOCAL_NOALIGN(el1_sync)
712 SYM_CODE_END(el1_sync)
715 SYM_CODE_START_LOCAL_NOALIGN(el1_irq)
717 el1_interrupt_handler handle_arch_irq
719 SYM_CODE_END(el1_irq)
721 SYM_CODE_START_LOCAL_NOALIGN(el1_fiq)
723 el1_interrupt_handler handle_arch_fiq
725 SYM_CODE_END(el1_fiq)
731 SYM_CODE_START_LOCAL_NOALIGN(el0_sync)
736 SYM_CODE_END(el0_sync)
740 SYM_CODE_START_LOCAL_NOALIGN(el0_sync_compat)
743 bl el0_sync_compat_handler
745 SYM_CODE_END(el0_sync_compat)
748 SYM_CODE_START_LOCAL_NOALIGN(el0_irq_compat)
751 SYM_CODE_END(el0_irq_compat)
753 SYM_CODE_START_LOCAL_NOALIGN(el0_fiq_compat)
756 SYM_CODE_END(el0_fiq_compat)
758 SYM_CODE_START_LOCAL_NOALIGN(el0_error_compat)
761 SYM_CODE_END(el0_error_compat)
765 SYM_CODE_START_LOCAL_NOALIGN(el0_irq)
768 el0_interrupt_handler handle_arch_irq
770 SYM_CODE_END(el0_irq)
772 SYM_CODE_START_LOCAL_NOALIGN(el0_fiq)
775 el0_interrupt_handler handle_arch_fiq
777 SYM_CODE_END(el0_fiq)
779 SYM_CODE_START_LOCAL(el1_error)
786 SYM_CODE_END(el1_error)
788 SYM_CODE_START_LOCAL(el0_error)
799 SYM_CODE_END(el0_error)
802 * "slow" syscall return path.
804 SYM_CODE_START_LOCAL(ret_to_user)
806 gic_prio_kentry_setup tmp=x3
807 #ifdef CONFIG_TRACE_IRQFLAGS
808 bl trace_hardirqs_off
810 ldr x19, [tsk, #TSK_TI_FLAGS]
811 and x2, x19, #_TIF_WORK_MASK
812 cbnz x2, work_pending
815 /* Ignore asynchronous tag check faults in the uaccess routines */
817 enable_step_tsk x19, x2
818 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK
824 * Ok, we need to do extra processing, enter the slow path.
830 ldr x19, [tsk, #TSK_TI_FLAGS] // re-check for single-step
832 SYM_CODE_END(ret_to_user)
834 .popsection // .entry.text
836 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
838 * Exception vectors trampoline.
840 .pushsection ".entry.tramp.text", "ax"
842 // Move from tramp_pg_dir to swapper_pg_dir
843 .macro tramp_map_kernel, tmp
845 add \tmp, \tmp, #TRAMP_SWAPPER_OFFSET
846 bic \tmp, \tmp, #USER_ASID_FLAG
848 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
849 alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003
850 /* ASID already in \tmp[63:48] */
851 movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12)
852 movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12)
853 /* 2MB boundary containing the vectors, so we nobble the walk cache */
854 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12)
858 alternative_else_nop_endif
859 #endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */
862 // Move from swapper_pg_dir to tramp_pg_dir
863 .macro tramp_unmap_kernel, tmp
865 sub \tmp, \tmp, #TRAMP_SWAPPER_OFFSET
866 orr \tmp, \tmp, #USER_ASID_FLAG
869 * We avoid running the post_ttbr_update_workaround here because
870 * it's only needed by Cavium ThunderX, which requires KPTI to be
875 .macro tramp_ventry, regsize = 64
879 msr tpidrro_el0, x30 // Restored in kernel_ventry
882 * Defend against branch aliasing attacks by pushing a dummy
883 * entry onto the return stack and using a RET instruction to
884 * enter the full-fat kernel vectors.
890 #ifdef CONFIG_RANDOMIZE_BASE
891 adr x30, tramp_vectors + PAGE_SIZE
892 alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003
897 alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM
898 prfm plil1strm, [x30, #(1b - tramp_vectors)]
899 alternative_else_nop_endif
901 add x30, x30, #(1b - tramp_vectors)
906 .macro tramp_exit, regsize = 64
907 adr x30, tramp_vectors
909 tramp_unmap_kernel x30
918 SYM_CODE_START_NOALIGN(tramp_vectors)
930 SYM_CODE_END(tramp_vectors)
932 SYM_CODE_START(tramp_exit_native)
934 SYM_CODE_END(tramp_exit_native)
936 SYM_CODE_START(tramp_exit_compat)
938 SYM_CODE_END(tramp_exit_compat)
941 .popsection // .entry.tramp.text
942 #ifdef CONFIG_RANDOMIZE_BASE
943 .pushsection ".rodata", "a"
945 SYM_DATA_START(__entry_tramp_data_start)
947 SYM_DATA_END(__entry_tramp_data_start)
948 .popsection // .rodata
949 #endif /* CONFIG_RANDOMIZE_BASE */
950 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
953 * Register switch for AArch64. The callee-saved registers need to be saved
954 * and restored. On entry:
955 * x0 = previous task_struct (must be preserved across the switch)
956 * x1 = next task_struct
957 * Previous and next are guaranteed not to be the same.
960 SYM_FUNC_START(cpu_switch_to)
961 mov x10, #THREAD_CPU_CONTEXT
964 stp x19, x20, [x8], #16 // store callee-saved registers
965 stp x21, x22, [x8], #16
966 stp x23, x24, [x8], #16
967 stp x25, x26, [x8], #16
968 stp x27, x28, [x8], #16
969 stp x29, x9, [x8], #16
972 ldp x19, x20, [x8], #16 // restore callee-saved registers
973 ldp x21, x22, [x8], #16
974 ldp x23, x24, [x8], #16
975 ldp x25, x26, [x8], #16
976 ldp x27, x28, [x8], #16
977 ldp x29, x9, [x8], #16
981 ptrauth_keys_install_kernel x1, x8, x9, x10
985 SYM_FUNC_END(cpu_switch_to)
986 NOKPROBE(cpu_switch_to)
989 * This is how we return from a fork.
991 SYM_CODE_START(ret_from_fork)
993 cbz x19, 1f // not a kernel thread
996 1: get_current_task tsk
998 SYM_CODE_END(ret_from_fork)
999 NOKPROBE(ret_from_fork)
1001 #ifdef CONFIG_ARM_SDE_INTERFACE
1003 #include <asm/sdei.h>
1004 #include <uapi/linux/arm_sdei.h>
1006 .macro sdei_handler_exit exit_mode
1007 /* On success, this call never returns... */
1008 cmp \exit_mode, #SDEI_EXIT_SMC
1016 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1018 * The regular SDEI entry point may have been unmapped along with the rest of
1019 * the kernel. This trampoline restores the kernel mapping to make the x1 memory
1020 * argument accessible.
1022 * This clobbers x4, __sdei_handler() will restore this from firmware's
1026 .pushsection ".entry.tramp.text", "ax"
1027 SYM_CODE_START(__sdei_asm_entry_trampoline)
1029 tbz x4, #USER_ASID_BIT, 1f
1031 tramp_map_kernel tmp=x4
1036 * Remember whether to unmap the kernel on exit.
1038 1: str x4, [x1, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)]
1040 #ifdef CONFIG_RANDOMIZE_BASE
1041 adr x4, tramp_vectors + PAGE_SIZE
1042 add x4, x4, #:lo12:__sdei_asm_trampoline_next_handler
1045 ldr x4, =__sdei_asm_handler
1048 SYM_CODE_END(__sdei_asm_entry_trampoline)
1049 NOKPROBE(__sdei_asm_entry_trampoline)
1052 * Make the exit call and restore the original ttbr1_el1
1054 * x0 & x1: setup for the exit API call
1056 * x4: struct sdei_registered_event argument from registration time.
1058 SYM_CODE_START(__sdei_asm_exit_trampoline)
1059 ldr x4, [x4, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)]
1062 tramp_unmap_kernel tmp=x4
1064 1: sdei_handler_exit exit_mode=x2
1065 SYM_CODE_END(__sdei_asm_exit_trampoline)
1066 NOKPROBE(__sdei_asm_exit_trampoline)
1068 .popsection // .entry.tramp.text
1069 #ifdef CONFIG_RANDOMIZE_BASE
1070 .pushsection ".rodata", "a"
1071 SYM_DATA_START(__sdei_asm_trampoline_next_handler)
1072 .quad __sdei_asm_handler
1073 SYM_DATA_END(__sdei_asm_trampoline_next_handler)
1074 .popsection // .rodata
1075 #endif /* CONFIG_RANDOMIZE_BASE */
1076 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1079 * Software Delegated Exception entry point.
1082 * x1: struct sdei_registered_event argument from registration time.
1083 * x2: interrupted PC
1084 * x3: interrupted PSTATE
1085 * x4: maybe clobbered by the trampoline
1087 * Firmware has preserved x0->x17 for us, we must save/restore the rest to
1088 * follow SMC-CC. We save (or retrieve) all the registers as the handler may
1091 SYM_CODE_START(__sdei_asm_handler)
1092 stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC]
1093 stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2]
1094 stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3]
1095 stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4]
1096 stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5]
1097 stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6]
1098 stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7]
1099 stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8]
1100 stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9]
1101 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10]
1102 stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11]
1103 stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12]
1104 stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13]
1105 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14]
1107 stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR]
1111 #if defined(CONFIG_VMAP_STACK) || defined(CONFIG_SHADOW_CALL_STACK)
1112 ldrb w4, [x19, #SDEI_EVENT_PRIORITY]
1115 #ifdef CONFIG_VMAP_STACK
1117 * entry.S may have been using sp as a scratch register, find whether
1118 * this is a normal or critical event and switch to the appropriate
1119 * stack for this CPU.
1122 ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6
1124 1: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6
1125 2: mov x6, #SDEI_STACK_SIZE
1130 #ifdef CONFIG_SHADOW_CALL_STACK
1131 /* Use a separate shadow call stack for normal and critical events */
1133 ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_normal_ptr, tmp=x6
1135 3: ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_critical_ptr, tmp=x6
1140 * We may have interrupted userspace, or a guest, or exit-from or
1141 * return-to either of these. We can't trust sp_el0, restore it.
1144 ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1
1147 /* If we interrupted the kernel point to the previous stack/frame. */
1151 csel x29, x29, xzr, eq // fp, or zero
1152 csel x4, x2, xzr, eq // elr, or zero
1154 stp x29, x4, [sp, #-16]!
1157 add x0, x19, #SDEI_EVENT_INTREGS
1162 /* restore regs >x17 that we clobbered */
1163 mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline
1164 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14]
1165 ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9]
1166 ldp lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR]
1169 mov x1, x0 // address to complete_and_resume
1170 /* x0 = (x0 <= 1) ? EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME */
1172 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE
1173 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME
1176 ldr_l x2, sdei_exit_mode
1178 alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0
1179 sdei_handler_exit exit_mode=x2
1180 alternative_else_nop_endif
1182 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1183 tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline
1186 SYM_CODE_END(__sdei_asm_handler)
1187 NOKPROBE(__sdei_asm_handler)
1188 #endif /* CONFIG_ARM_SDE_INTERFACE */