1 // SPDX-License-Identifier: GPL-2.0
3 * Exception handling code
5 * Copyright (C) 2019 ARM Ltd.
8 #include <linux/context_tracking.h>
9 #include <linux/linkage.h>
10 #include <linux/lockdep.h>
11 #include <linux/ptrace.h>
12 #include <linux/sched.h>
13 #include <linux/sched/debug.h>
14 #include <linux/thread_info.h>
16 #include <asm/cpufeature.h>
17 #include <asm/daifflags.h>
19 #include <asm/exception.h>
20 #include <asm/kprobes.h>
22 #include <asm/processor.h>
24 #include <asm/stacktrace.h>
25 #include <asm/sysreg.h>
26 #include <asm/system_misc.h>
29 * Handle IRQ/context state management when entering from kernel mode.
30 * Before this function is called it is not safe to call regular kernel code,
31 * intrumentable code, or any code which may trigger an exception.
33 * This is intended to match the logic in irqentry_enter(), handling the kernel
34 * mode transitions only.
36 static __always_inline void __enter_from_kernel_mode(struct pt_regs *regs)
38 regs->exit_rcu = false;
40 if (!IS_ENABLED(CONFIG_TINY_RCU) && is_idle_task(current)) {
41 lockdep_hardirqs_off(CALLER_ADDR0);
43 trace_hardirqs_off_finish();
45 regs->exit_rcu = true;
49 lockdep_hardirqs_off(CALLER_ADDR0);
50 rcu_irq_enter_check_tick();
51 trace_hardirqs_off_finish();
54 static void noinstr enter_from_kernel_mode(struct pt_regs *regs)
56 __enter_from_kernel_mode(regs);
57 mte_check_tfsr_entry();
61 * Handle IRQ/context state management when exiting to kernel mode.
62 * After this function returns it is not safe to call regular kernel code,
63 * intrumentable code, or any code which may trigger an exception.
65 * This is intended to match the logic in irqentry_exit(), handling the kernel
66 * mode transitions only, and with preemption handled elsewhere.
68 static __always_inline void __exit_to_kernel_mode(struct pt_regs *regs)
70 lockdep_assert_irqs_disabled();
72 if (interrupts_enabled(regs)) {
74 trace_hardirqs_on_prepare();
75 lockdep_hardirqs_on_prepare(CALLER_ADDR0);
77 lockdep_hardirqs_on(CALLER_ADDR0);
88 static void noinstr exit_to_kernel_mode(struct pt_regs *regs)
90 mte_check_tfsr_exit();
91 __exit_to_kernel_mode(regs);
95 * Handle IRQ/context state management when entering from user mode.
96 * Before this function is called it is not safe to call regular kernel code,
97 * intrumentable code, or any code which may trigger an exception.
99 static __always_inline void __enter_from_user_mode(void)
101 lockdep_hardirqs_off(CALLER_ADDR0);
102 CT_WARN_ON(ct_state() != CONTEXT_USER);
104 trace_hardirqs_off_finish();
107 asmlinkage void noinstr enter_from_user_mode(void)
109 __enter_from_user_mode();
113 * Handle IRQ/context state management when exiting to user mode.
114 * After this function returns it is not safe to call regular kernel code,
115 * intrumentable code, or any code which may trigger an exception.
117 static __always_inline void __exit_to_user_mode(void)
120 trace_hardirqs_on_prepare();
121 lockdep_hardirqs_on_prepare(CALLER_ADDR0);
123 lockdep_hardirqs_on(CALLER_ADDR0);
126 asmlinkage void noinstr exit_to_user_mode(void)
128 mte_check_tfsr_exit();
129 __exit_to_user_mode();
133 * Handle IRQ/context state management when entering an NMI from user/kernel
134 * mode. Before this function is called it is not safe to call regular kernel
135 * code, intrumentable code, or any code which may trigger an exception.
137 static void noinstr arm64_enter_nmi(struct pt_regs *regs)
139 regs->lockdep_hardirqs = lockdep_hardirqs_enabled();
142 lockdep_hardirqs_off(CALLER_ADDR0);
143 lockdep_hardirq_enter();
146 trace_hardirqs_off_finish();
151 * Handle IRQ/context state management when exiting an NMI from user/kernel
152 * mode. After this function returns it is not safe to call regular kernel
153 * code, intrumentable code, or any code which may trigger an exception.
155 static void noinstr arm64_exit_nmi(struct pt_regs *regs)
157 bool restore = regs->lockdep_hardirqs;
161 trace_hardirqs_on_prepare();
162 lockdep_hardirqs_on_prepare(CALLER_ADDR0);
166 lockdep_hardirq_exit();
168 lockdep_hardirqs_on(CALLER_ADDR0);
173 * Handle IRQ/context state management when entering a debug exception from
174 * kernel mode. Before this function is called it is not safe to call regular
175 * kernel code, intrumentable code, or any code which may trigger an exception.
177 static void noinstr arm64_enter_el1_dbg(struct pt_regs *regs)
179 regs->lockdep_hardirqs = lockdep_hardirqs_enabled();
181 lockdep_hardirqs_off(CALLER_ADDR0);
184 trace_hardirqs_off_finish();
188 * Handle IRQ/context state management when exiting a debug exception from
189 * kernel mode. After this function returns it is not safe to call regular
190 * kernel code, intrumentable code, or any code which may trigger an exception.
192 static void noinstr arm64_exit_el1_dbg(struct pt_regs *regs)
194 bool restore = regs->lockdep_hardirqs;
197 trace_hardirqs_on_prepare();
198 lockdep_hardirqs_on_prepare(CALLER_ADDR0);
203 lockdep_hardirqs_on(CALLER_ADDR0);
206 static void noinstr enter_el1_irq_or_nmi(struct pt_regs *regs)
208 if (IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && !interrupts_enabled(regs))
209 arm64_enter_nmi(regs);
211 enter_from_kernel_mode(regs);
214 static void noinstr exit_el1_irq_or_nmi(struct pt_regs *regs)
216 if (IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && !interrupts_enabled(regs))
217 arm64_exit_nmi(regs);
219 exit_to_kernel_mode(regs);
222 static void __sched arm64_preempt_schedule_irq(void)
224 lockdep_assert_irqs_disabled();
227 * DAIF.DA are cleared at the start of IRQ/FIQ handling, and when GIC
228 * priority masking is used the GIC irqchip driver will clear DAIF.IF
229 * using gic_arch_enable_irqs() for normal IRQs. If anything is set in
230 * DAIF we must have handled an NMI, so skip preemption.
232 if (system_uses_irq_prio_masking() && read_sysreg(daif))
236 * Preempting a task from an IRQ means we leave copies of PSTATE
237 * on the stack. cpufeature's enable calls may modify PSTATE, but
238 * resuming one of these preempted tasks would undo those changes.
240 * Only allow a task to be preempted once cpufeatures have been
243 if (system_capabilities_finalized())
244 preempt_schedule_irq();
247 static void do_interrupt_handler(struct pt_regs *regs,
248 void (*handler)(struct pt_regs *))
250 if (on_thread_stack())
251 call_on_irq_stack(regs, handler);
256 extern void (*handle_arch_irq)(struct pt_regs *);
257 extern void (*handle_arch_fiq)(struct pt_regs *);
259 static void noinstr __panic_unhandled(struct pt_regs *regs, const char *vector,
262 arm64_enter_nmi(regs);
266 pr_crit("Unhandled %s exception on CPU%d, ESR 0x%08x -- %s\n",
267 vector, smp_processor_id(), esr,
268 esr_get_class_string(esr));
271 panic("Unhandled exception");
274 #define UNHANDLED(el, regsize, vector) \
275 asmlinkage void noinstr el##_##regsize##_##vector##_handler(struct pt_regs *regs) \
277 const char *desc = #regsize "-bit " #el " " #vector; \
278 __panic_unhandled(regs, desc, read_sysreg(esr_el1)); \
281 #ifdef CONFIG_ARM64_ERRATUM_1463225
282 static DEFINE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa);
284 static void cortex_a76_erratum_1463225_svc_handler(void)
288 if (!unlikely(test_thread_flag(TIF_SINGLESTEP)))
291 if (!unlikely(this_cpu_has_cap(ARM64_WORKAROUND_1463225)))
294 __this_cpu_write(__in_cortex_a76_erratum_1463225_wa, 1);
295 reg = read_sysreg(mdscr_el1);
296 val = reg | DBG_MDSCR_SS | DBG_MDSCR_KDE;
297 write_sysreg(val, mdscr_el1);
298 asm volatile("msr daifclr, #8");
301 /* We will have taken a single-step exception by this point */
303 write_sysreg(reg, mdscr_el1);
304 __this_cpu_write(__in_cortex_a76_erratum_1463225_wa, 0);
307 static bool cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs)
309 if (!__this_cpu_read(__in_cortex_a76_erratum_1463225_wa))
313 * We've taken a dummy step exception from the kernel to ensure
314 * that interrupts are re-enabled on the syscall path. Return back
315 * to cortex_a76_erratum_1463225_svc_handler() with debug exceptions
316 * masked so that we can safely restore the mdscr and get on with
317 * handling the syscall.
319 regs->pstate |= PSR_D_BIT;
322 #else /* CONFIG_ARM64_ERRATUM_1463225 */
323 static void cortex_a76_erratum_1463225_svc_handler(void) { }
324 static bool cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs)
328 #endif /* CONFIG_ARM64_ERRATUM_1463225 */
330 UNHANDLED(el1t, 64, sync)
331 UNHANDLED(el1t, 64, irq)
332 UNHANDLED(el1t, 64, fiq)
333 UNHANDLED(el1t, 64, error)
335 static void noinstr el1_abort(struct pt_regs *regs, unsigned long esr)
337 unsigned long far = read_sysreg(far_el1);
339 enter_from_kernel_mode(regs);
340 local_daif_inherit(regs);
341 do_mem_abort(far, esr, regs);
343 exit_to_kernel_mode(regs);
346 static void noinstr el1_pc(struct pt_regs *regs, unsigned long esr)
348 unsigned long far = read_sysreg(far_el1);
350 enter_from_kernel_mode(regs);
351 local_daif_inherit(regs);
352 do_sp_pc_abort(far, esr, regs);
354 exit_to_kernel_mode(regs);
357 static void noinstr el1_undef(struct pt_regs *regs)
359 enter_from_kernel_mode(regs);
360 local_daif_inherit(regs);
363 exit_to_kernel_mode(regs);
366 static void noinstr el1_dbg(struct pt_regs *regs, unsigned long esr)
368 unsigned long far = read_sysreg(far_el1);
370 arm64_enter_el1_dbg(regs);
371 if (!cortex_a76_erratum_1463225_debug_handler(regs))
372 do_debug_exception(far, esr, regs);
373 arm64_exit_el1_dbg(regs);
376 static void noinstr el1_fpac(struct pt_regs *regs, unsigned long esr)
378 enter_from_kernel_mode(regs);
379 local_daif_inherit(regs);
380 do_ptrauth_fault(regs, esr);
382 exit_to_kernel_mode(regs);
385 asmlinkage void noinstr el1h_64_sync_handler(struct pt_regs *regs)
387 unsigned long esr = read_sysreg(esr_el1);
389 switch (ESR_ELx_EC(esr)) {
390 case ESR_ELx_EC_DABT_CUR:
391 case ESR_ELx_EC_IABT_CUR:
392 el1_abort(regs, esr);
395 * We don't handle ESR_ELx_EC_SP_ALIGN, since we will have hit a
396 * recursive exception when trying to push the initial pt_regs.
398 case ESR_ELx_EC_PC_ALIGN:
401 case ESR_ELx_EC_SYS64:
402 case ESR_ELx_EC_UNKNOWN:
405 case ESR_ELx_EC_BREAKPT_CUR:
406 case ESR_ELx_EC_SOFTSTP_CUR:
407 case ESR_ELx_EC_WATCHPT_CUR:
408 case ESR_ELx_EC_BRK64:
411 case ESR_ELx_EC_FPAC:
415 __panic_unhandled(regs, "64-bit el1h sync", esr);
419 static void noinstr el1_interrupt(struct pt_regs *regs,
420 void (*handler)(struct pt_regs *))
422 write_sysreg(DAIF_PROCCTX_NOIRQ, daif);
424 enter_el1_irq_or_nmi(regs);
425 do_interrupt_handler(regs, handler);
428 * Note: thread_info::preempt_count includes both thread_info::count
429 * and thread_info::need_resched, and is not equivalent to
432 if (IS_ENABLED(CONFIG_PREEMPTION) &&
433 READ_ONCE(current_thread_info()->preempt_count) == 0)
434 arm64_preempt_schedule_irq();
436 exit_el1_irq_or_nmi(regs);
439 asmlinkage void noinstr el1h_64_irq_handler(struct pt_regs *regs)
441 el1_interrupt(regs, handle_arch_irq);
444 asmlinkage void noinstr el1h_64_fiq_handler(struct pt_regs *regs)
446 el1_interrupt(regs, handle_arch_fiq);
449 asmlinkage void noinstr el1h_64_error_handler(struct pt_regs *regs)
451 unsigned long esr = read_sysreg(esr_el1);
453 local_daif_restore(DAIF_ERRCTX);
454 arm64_enter_nmi(regs);
455 do_serror(regs, esr);
456 arm64_exit_nmi(regs);
459 static void noinstr el0_da(struct pt_regs *regs, unsigned long esr)
461 unsigned long far = read_sysreg(far_el1);
463 enter_from_user_mode();
464 local_daif_restore(DAIF_PROCCTX);
465 do_mem_abort(far, esr, regs);
468 static void noinstr el0_ia(struct pt_regs *regs, unsigned long esr)
470 unsigned long far = read_sysreg(far_el1);
473 * We've taken an instruction abort from userspace and not yet
474 * re-enabled IRQs. If the address is a kernel address, apply
475 * BP hardening prior to enabling IRQs and pre-emption.
477 if (!is_ttbr0_addr(far))
478 arm64_apply_bp_hardening();
480 enter_from_user_mode();
481 local_daif_restore(DAIF_PROCCTX);
482 do_mem_abort(far, esr, regs);
485 static void noinstr el0_fpsimd_acc(struct pt_regs *regs, unsigned long esr)
487 enter_from_user_mode();
488 local_daif_restore(DAIF_PROCCTX);
489 do_fpsimd_acc(esr, regs);
492 static void noinstr el0_sve_acc(struct pt_regs *regs, unsigned long esr)
494 enter_from_user_mode();
495 local_daif_restore(DAIF_PROCCTX);
496 do_sve_acc(esr, regs);
499 static void noinstr el0_fpsimd_exc(struct pt_regs *regs, unsigned long esr)
501 enter_from_user_mode();
502 local_daif_restore(DAIF_PROCCTX);
503 do_fpsimd_exc(esr, regs);
506 static void noinstr el0_sys(struct pt_regs *regs, unsigned long esr)
508 enter_from_user_mode();
509 local_daif_restore(DAIF_PROCCTX);
510 do_sysinstr(esr, regs);
513 static void noinstr el0_pc(struct pt_regs *regs, unsigned long esr)
515 unsigned long far = read_sysreg(far_el1);
517 if (!is_ttbr0_addr(instruction_pointer(regs)))
518 arm64_apply_bp_hardening();
520 enter_from_user_mode();
521 local_daif_restore(DAIF_PROCCTX);
522 do_sp_pc_abort(far, esr, regs);
525 static void noinstr el0_sp(struct pt_regs *regs, unsigned long esr)
527 enter_from_user_mode();
528 local_daif_restore(DAIF_PROCCTX);
529 do_sp_pc_abort(regs->sp, esr, regs);
532 static void noinstr el0_undef(struct pt_regs *regs)
534 enter_from_user_mode();
535 local_daif_restore(DAIF_PROCCTX);
539 static void noinstr el0_bti(struct pt_regs *regs)
541 enter_from_user_mode();
542 local_daif_restore(DAIF_PROCCTX);
546 static void noinstr el0_inv(struct pt_regs *regs, unsigned long esr)
548 enter_from_user_mode();
549 local_daif_restore(DAIF_PROCCTX);
550 bad_el0_sync(regs, 0, esr);
553 static void noinstr el0_dbg(struct pt_regs *regs, unsigned long esr)
555 /* Only watchpoints write FAR_EL1, otherwise its UNKNOWN */
556 unsigned long far = read_sysreg(far_el1);
558 enter_from_user_mode();
559 do_debug_exception(far, esr, regs);
560 local_daif_restore(DAIF_PROCCTX);
563 static void noinstr el0_svc(struct pt_regs *regs)
565 enter_from_user_mode();
566 cortex_a76_erratum_1463225_svc_handler();
570 static void noinstr el0_fpac(struct pt_regs *regs, unsigned long esr)
572 enter_from_user_mode();
573 local_daif_restore(DAIF_PROCCTX);
574 do_ptrauth_fault(regs, esr);
577 asmlinkage void noinstr el0t_64_sync_handler(struct pt_regs *regs)
579 unsigned long esr = read_sysreg(esr_el1);
581 switch (ESR_ELx_EC(esr)) {
582 case ESR_ELx_EC_SVC64:
585 case ESR_ELx_EC_DABT_LOW:
588 case ESR_ELx_EC_IABT_LOW:
591 case ESR_ELx_EC_FP_ASIMD:
592 el0_fpsimd_acc(regs, esr);
595 el0_sve_acc(regs, esr);
597 case ESR_ELx_EC_FP_EXC64:
598 el0_fpsimd_exc(regs, esr);
600 case ESR_ELx_EC_SYS64:
604 case ESR_ELx_EC_SP_ALIGN:
607 case ESR_ELx_EC_PC_ALIGN:
610 case ESR_ELx_EC_UNKNOWN:
616 case ESR_ELx_EC_BREAKPT_LOW:
617 case ESR_ELx_EC_SOFTSTP_LOW:
618 case ESR_ELx_EC_WATCHPT_LOW:
619 case ESR_ELx_EC_BRK64:
622 case ESR_ELx_EC_FPAC:
630 static void noinstr el0_interrupt(struct pt_regs *regs,
631 void (*handler)(struct pt_regs *))
633 enter_from_user_mode();
635 write_sysreg(DAIF_PROCCTX_NOIRQ, daif);
637 if (regs->pc & BIT(55))
638 arm64_apply_bp_hardening();
640 do_interrupt_handler(regs, handler);
643 static void noinstr __el0_irq_handler_common(struct pt_regs *regs)
645 el0_interrupt(regs, handle_arch_irq);
648 asmlinkage void noinstr el0t_64_irq_handler(struct pt_regs *regs)
650 __el0_irq_handler_common(regs);
653 static void noinstr __el0_fiq_handler_common(struct pt_regs *regs)
655 el0_interrupt(regs, handle_arch_fiq);
658 asmlinkage void noinstr el0t_64_fiq_handler(struct pt_regs *regs)
660 __el0_fiq_handler_common(regs);
663 static void noinstr __el0_error_handler_common(struct pt_regs *regs)
665 unsigned long esr = read_sysreg(esr_el1);
667 enter_from_user_mode();
668 local_daif_restore(DAIF_ERRCTX);
669 arm64_enter_nmi(regs);
670 do_serror(regs, esr);
671 arm64_exit_nmi(regs);
672 local_daif_restore(DAIF_PROCCTX);
675 asmlinkage void noinstr el0t_64_error_handler(struct pt_regs *regs)
677 __el0_error_handler_common(regs);
681 static void noinstr el0_cp15(struct pt_regs *regs, unsigned long esr)
683 enter_from_user_mode();
684 local_daif_restore(DAIF_PROCCTX);
685 do_cp15instr(esr, regs);
688 static void noinstr el0_svc_compat(struct pt_regs *regs)
690 enter_from_user_mode();
691 cortex_a76_erratum_1463225_svc_handler();
692 do_el0_svc_compat(regs);
695 asmlinkage void noinstr el0t_32_sync_handler(struct pt_regs *regs)
697 unsigned long esr = read_sysreg(esr_el1);
699 switch (ESR_ELx_EC(esr)) {
700 case ESR_ELx_EC_SVC32:
701 el0_svc_compat(regs);
703 case ESR_ELx_EC_DABT_LOW:
706 case ESR_ELx_EC_IABT_LOW:
709 case ESR_ELx_EC_FP_ASIMD:
710 el0_fpsimd_acc(regs, esr);
712 case ESR_ELx_EC_FP_EXC32:
713 el0_fpsimd_exc(regs, esr);
715 case ESR_ELx_EC_PC_ALIGN:
718 case ESR_ELx_EC_UNKNOWN:
719 case ESR_ELx_EC_CP14_MR:
720 case ESR_ELx_EC_CP14_LS:
721 case ESR_ELx_EC_CP14_64:
724 case ESR_ELx_EC_CP15_32:
725 case ESR_ELx_EC_CP15_64:
728 case ESR_ELx_EC_BREAKPT_LOW:
729 case ESR_ELx_EC_SOFTSTP_LOW:
730 case ESR_ELx_EC_WATCHPT_LOW:
731 case ESR_ELx_EC_BKPT32:
739 asmlinkage void noinstr el0t_32_irq_handler(struct pt_regs *regs)
741 __el0_irq_handler_common(regs);
744 asmlinkage void noinstr el0t_32_fiq_handler(struct pt_regs *regs)
746 __el0_fiq_handler_common(regs);
749 asmlinkage void noinstr el0t_32_error_handler(struct pt_regs *regs)
751 __el0_error_handler_common(regs);
753 #else /* CONFIG_COMPAT */
754 UNHANDLED(el0t, 32, sync)
755 UNHANDLED(el0t, 32, irq)
756 UNHANDLED(el0t, 32, fiq)
757 UNHANDLED(el0t, 32, error)
758 #endif /* CONFIG_COMPAT */
760 #ifdef CONFIG_VMAP_STACK
761 asmlinkage void noinstr handle_bad_stack(struct pt_regs *regs)
763 unsigned int esr = read_sysreg(esr_el1);
764 unsigned long far = read_sysreg(far_el1);
766 arm64_enter_nmi(regs);
767 panic_bad_stack(regs, esr, far);
769 #endif /* CONFIG_VMAP_STACK */
771 #ifdef CONFIG_ARM_SDE_INTERFACE
772 asmlinkage noinstr unsigned long
773 __sdei_handler(struct pt_regs *regs, struct sdei_registered_event *arg)
778 * We didn't take an exception to get here, so the HW hasn't
779 * set/cleared bits in PSTATE that we may rely on.
781 * The original SDEI spec (ARM DEN 0054A) can be read ambiguously as to
782 * whether PSTATE bits are inherited unchanged or generated from
783 * scratch, and the TF-A implementation always clears PAN and always
784 * clears UAO. There are no other known implementations.
786 * Subsequent revisions (ARM DEN 0054B) follow the usual rules for how
787 * PSTATE is modified upon architectural exceptions, and so PAN is
788 * either inherited or set per SCTLR_ELx.SPAN, and UAO is always
791 * We must explicitly reset PAN to the expected state, including
792 * clearing it when the host isn't using it, in case a VM had it set.
794 if (system_uses_hw_pan())
796 else if (cpu_has_pan())
799 arm64_enter_nmi(regs);
800 ret = do_sdei_event(regs, arg);
801 arm64_exit_nmi(regs);
805 #endif /* CONFIG_ARM_SDE_INTERFACE */