1 // SPDX-License-Identifier: GPL-2.0
3 * Exception handling code
5 * Copyright (C) 2019 ARM Ltd.
8 #include <linux/context_tracking.h>
9 #include <linux/linkage.h>
10 #include <linux/lockdep.h>
11 #include <linux/ptrace.h>
12 #include <linux/sched.h>
13 #include <linux/sched/debug.h>
14 #include <linux/thread_info.h>
16 #include <asm/cpufeature.h>
17 #include <asm/daifflags.h>
19 #include <asm/exception.h>
20 #include <asm/kprobes.h>
22 #include <asm/processor.h>
24 #include <asm/stacktrace.h>
25 #include <asm/sysreg.h>
26 #include <asm/system_misc.h>
29 * This is intended to match the logic in irqentry_enter(), handling the kernel
30 * mode transitions only.
32 static void noinstr enter_from_kernel_mode(struct pt_regs *regs)
34 regs->exit_rcu = false;
36 if (!IS_ENABLED(CONFIG_TINY_RCU) && is_idle_task(current)) {
37 lockdep_hardirqs_off(CALLER_ADDR0);
39 trace_hardirqs_off_finish();
41 regs->exit_rcu = true;
45 lockdep_hardirqs_off(CALLER_ADDR0);
46 rcu_irq_enter_check_tick();
47 trace_hardirqs_off_finish();
49 mte_check_tfsr_entry();
53 * This is intended to match the logic in irqentry_exit(), handling the kernel
54 * mode transitions only, and with preemption handled elsewhere.
56 static void noinstr exit_to_kernel_mode(struct pt_regs *regs)
58 lockdep_assert_irqs_disabled();
60 mte_check_tfsr_exit();
62 if (interrupts_enabled(regs)) {
64 trace_hardirqs_on_prepare();
65 lockdep_hardirqs_on_prepare(CALLER_ADDR0);
67 lockdep_hardirqs_on(CALLER_ADDR0);
78 asmlinkage void noinstr enter_from_user_mode(void)
80 lockdep_hardirqs_off(CALLER_ADDR0);
81 CT_WARN_ON(ct_state() != CONTEXT_USER);
83 trace_hardirqs_off_finish();
86 asmlinkage void noinstr exit_to_user_mode(void)
88 mte_check_tfsr_exit();
90 trace_hardirqs_on_prepare();
91 lockdep_hardirqs_on_prepare(CALLER_ADDR0);
93 lockdep_hardirqs_on(CALLER_ADDR0);
96 static void noinstr arm64_enter_nmi(struct pt_regs *regs)
98 regs->lockdep_hardirqs = lockdep_hardirqs_enabled();
101 lockdep_hardirqs_off(CALLER_ADDR0);
102 lockdep_hardirq_enter();
105 trace_hardirqs_off_finish();
109 static void noinstr arm64_exit_nmi(struct pt_regs *regs)
111 bool restore = regs->lockdep_hardirqs;
115 trace_hardirqs_on_prepare();
116 lockdep_hardirqs_on_prepare(CALLER_ADDR0);
120 lockdep_hardirq_exit();
122 lockdep_hardirqs_on(CALLER_ADDR0);
126 static void noinstr arm64_enter_el1_dbg(struct pt_regs *regs)
128 regs->lockdep_hardirqs = lockdep_hardirqs_enabled();
130 lockdep_hardirqs_off(CALLER_ADDR0);
133 trace_hardirqs_off_finish();
136 static void noinstr arm64_exit_el1_dbg(struct pt_regs *regs)
138 bool restore = regs->lockdep_hardirqs;
141 trace_hardirqs_on_prepare();
142 lockdep_hardirqs_on_prepare(CALLER_ADDR0);
147 lockdep_hardirqs_on(CALLER_ADDR0);
150 static void noinstr enter_el1_irq_or_nmi(struct pt_regs *regs)
152 if (IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && !interrupts_enabled(regs))
153 arm64_enter_nmi(regs);
155 enter_from_kernel_mode(regs);
158 static void noinstr exit_el1_irq_or_nmi(struct pt_regs *regs)
160 if (IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && !interrupts_enabled(regs))
161 arm64_exit_nmi(regs);
163 exit_to_kernel_mode(regs);
166 static void __sched arm64_preempt_schedule_irq(void)
168 lockdep_assert_irqs_disabled();
171 * DAIF.DA are cleared at the start of IRQ/FIQ handling, and when GIC
172 * priority masking is used the GIC irqchip driver will clear DAIF.IF
173 * using gic_arch_enable_irqs() for normal IRQs. If anything is set in
174 * DAIF we must have handled an NMI, so skip preemption.
176 if (system_uses_irq_prio_masking() && read_sysreg(daif))
180 * Preempting a task from an IRQ means we leave copies of PSTATE
181 * on the stack. cpufeature's enable calls may modify PSTATE, but
182 * resuming one of these preempted tasks would undo those changes.
184 * Only allow a task to be preempted once cpufeatures have been
187 if (system_capabilities_finalized())
188 preempt_schedule_irq();
191 static void do_interrupt_handler(struct pt_regs *regs,
192 void (*handler)(struct pt_regs *))
194 if (on_thread_stack())
195 call_on_irq_stack(regs, handler);
200 extern void (*handle_arch_irq)(struct pt_regs *);
201 extern void (*handle_arch_fiq)(struct pt_regs *);
203 static void noinstr __panic_unhandled(struct pt_regs *regs, const char *vector,
206 arm64_enter_nmi(regs);
210 pr_crit("Unhandled %s exception on CPU%d, ESR 0x%08x -- %s\n",
211 vector, smp_processor_id(), esr,
212 esr_get_class_string(esr));
215 panic("Unhandled exception");
218 #define UNHANDLED(el, regsize, vector) \
219 asmlinkage void noinstr el##_##regsize##_##vector##_handler(struct pt_regs *regs) \
221 const char *desc = #regsize "-bit " #el " " #vector; \
222 __panic_unhandled(regs, desc, read_sysreg(esr_el1)); \
225 #ifdef CONFIG_ARM64_ERRATUM_1463225
226 static DEFINE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa);
228 static void cortex_a76_erratum_1463225_svc_handler(void)
232 if (!unlikely(test_thread_flag(TIF_SINGLESTEP)))
235 if (!unlikely(this_cpu_has_cap(ARM64_WORKAROUND_1463225)))
238 __this_cpu_write(__in_cortex_a76_erratum_1463225_wa, 1);
239 reg = read_sysreg(mdscr_el1);
240 val = reg | DBG_MDSCR_SS | DBG_MDSCR_KDE;
241 write_sysreg(val, mdscr_el1);
242 asm volatile("msr daifclr, #8");
245 /* We will have taken a single-step exception by this point */
247 write_sysreg(reg, mdscr_el1);
248 __this_cpu_write(__in_cortex_a76_erratum_1463225_wa, 0);
251 static bool cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs)
253 if (!__this_cpu_read(__in_cortex_a76_erratum_1463225_wa))
257 * We've taken a dummy step exception from the kernel to ensure
258 * that interrupts are re-enabled on the syscall path. Return back
259 * to cortex_a76_erratum_1463225_svc_handler() with debug exceptions
260 * masked so that we can safely restore the mdscr and get on with
261 * handling the syscall.
263 regs->pstate |= PSR_D_BIT;
266 #else /* CONFIG_ARM64_ERRATUM_1463225 */
267 static void cortex_a76_erratum_1463225_svc_handler(void) { }
268 static bool cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs)
272 #endif /* CONFIG_ARM64_ERRATUM_1463225 */
274 UNHANDLED(el1t, 64, sync)
275 UNHANDLED(el1t, 64, irq)
276 UNHANDLED(el1t, 64, fiq)
277 UNHANDLED(el1t, 64, error)
279 static void noinstr el1_abort(struct pt_regs *regs, unsigned long esr)
281 unsigned long far = read_sysreg(far_el1);
283 enter_from_kernel_mode(regs);
284 local_daif_inherit(regs);
285 do_mem_abort(far, esr, regs);
287 exit_to_kernel_mode(regs);
290 static void noinstr el1_pc(struct pt_regs *regs, unsigned long esr)
292 unsigned long far = read_sysreg(far_el1);
294 enter_from_kernel_mode(regs);
295 local_daif_inherit(regs);
296 do_sp_pc_abort(far, esr, regs);
298 exit_to_kernel_mode(regs);
301 static void noinstr el1_undef(struct pt_regs *regs)
303 enter_from_kernel_mode(regs);
304 local_daif_inherit(regs);
307 exit_to_kernel_mode(regs);
310 static void noinstr el1_dbg(struct pt_regs *regs, unsigned long esr)
312 unsigned long far = read_sysreg(far_el1);
314 arm64_enter_el1_dbg(regs);
315 if (!cortex_a76_erratum_1463225_debug_handler(regs))
316 do_debug_exception(far, esr, regs);
317 arm64_exit_el1_dbg(regs);
320 static void noinstr el1_fpac(struct pt_regs *regs, unsigned long esr)
322 enter_from_kernel_mode(regs);
323 local_daif_inherit(regs);
324 do_ptrauth_fault(regs, esr);
326 exit_to_kernel_mode(regs);
329 asmlinkage void noinstr el1h_64_sync_handler(struct pt_regs *regs)
331 unsigned long esr = read_sysreg(esr_el1);
333 switch (ESR_ELx_EC(esr)) {
334 case ESR_ELx_EC_DABT_CUR:
335 case ESR_ELx_EC_IABT_CUR:
336 el1_abort(regs, esr);
339 * We don't handle ESR_ELx_EC_SP_ALIGN, since we will have hit a
340 * recursive exception when trying to push the initial pt_regs.
342 case ESR_ELx_EC_PC_ALIGN:
345 case ESR_ELx_EC_SYS64:
346 case ESR_ELx_EC_UNKNOWN:
349 case ESR_ELx_EC_BREAKPT_CUR:
350 case ESR_ELx_EC_SOFTSTP_CUR:
351 case ESR_ELx_EC_WATCHPT_CUR:
352 case ESR_ELx_EC_BRK64:
355 case ESR_ELx_EC_FPAC:
359 __panic_unhandled(regs, "64-bit el1h sync", esr);
363 static void noinstr el1_interrupt(struct pt_regs *regs,
364 void (*handler)(struct pt_regs *))
366 write_sysreg(DAIF_PROCCTX_NOIRQ, daif);
368 enter_el1_irq_or_nmi(regs);
369 do_interrupt_handler(regs, handler);
372 * Note: thread_info::preempt_count includes both thread_info::count
373 * and thread_info::need_resched, and is not equivalent to
376 if (IS_ENABLED(CONFIG_PREEMPTION) &&
377 READ_ONCE(current_thread_info()->preempt_count) == 0)
378 arm64_preempt_schedule_irq();
380 exit_el1_irq_or_nmi(regs);
383 asmlinkage void noinstr el1h_64_irq_handler(struct pt_regs *regs)
385 el1_interrupt(regs, handle_arch_irq);
388 asmlinkage void noinstr el1h_64_fiq_handler(struct pt_regs *regs)
390 el1_interrupt(regs, handle_arch_fiq);
393 asmlinkage void noinstr el1h_64_error_handler(struct pt_regs *regs)
395 unsigned long esr = read_sysreg(esr_el1);
397 local_daif_restore(DAIF_ERRCTX);
398 arm64_enter_nmi(regs);
399 do_serror(regs, esr);
400 arm64_exit_nmi(regs);
403 static void noinstr el0_da(struct pt_regs *regs, unsigned long esr)
405 unsigned long far = read_sysreg(far_el1);
407 enter_from_user_mode();
408 local_daif_restore(DAIF_PROCCTX);
409 do_mem_abort(far, esr, regs);
412 static void noinstr el0_ia(struct pt_regs *regs, unsigned long esr)
414 unsigned long far = read_sysreg(far_el1);
417 * We've taken an instruction abort from userspace and not yet
418 * re-enabled IRQs. If the address is a kernel address, apply
419 * BP hardening prior to enabling IRQs and pre-emption.
421 if (!is_ttbr0_addr(far))
422 arm64_apply_bp_hardening();
424 enter_from_user_mode();
425 local_daif_restore(DAIF_PROCCTX);
426 do_mem_abort(far, esr, regs);
429 static void noinstr el0_fpsimd_acc(struct pt_regs *regs, unsigned long esr)
431 enter_from_user_mode();
432 local_daif_restore(DAIF_PROCCTX);
433 do_fpsimd_acc(esr, regs);
436 static void noinstr el0_sve_acc(struct pt_regs *regs, unsigned long esr)
438 enter_from_user_mode();
439 local_daif_restore(DAIF_PROCCTX);
440 do_sve_acc(esr, regs);
443 static void noinstr el0_fpsimd_exc(struct pt_regs *regs, unsigned long esr)
445 enter_from_user_mode();
446 local_daif_restore(DAIF_PROCCTX);
447 do_fpsimd_exc(esr, regs);
450 static void noinstr el0_sys(struct pt_regs *regs, unsigned long esr)
452 enter_from_user_mode();
453 local_daif_restore(DAIF_PROCCTX);
454 do_sysinstr(esr, regs);
457 static void noinstr el0_pc(struct pt_regs *regs, unsigned long esr)
459 unsigned long far = read_sysreg(far_el1);
461 if (!is_ttbr0_addr(instruction_pointer(regs)))
462 arm64_apply_bp_hardening();
464 enter_from_user_mode();
465 local_daif_restore(DAIF_PROCCTX);
466 do_sp_pc_abort(far, esr, regs);
469 static void noinstr el0_sp(struct pt_regs *regs, unsigned long esr)
471 enter_from_user_mode();
472 local_daif_restore(DAIF_PROCCTX);
473 do_sp_pc_abort(regs->sp, esr, regs);
476 static void noinstr el0_undef(struct pt_regs *regs)
478 enter_from_user_mode();
479 local_daif_restore(DAIF_PROCCTX);
483 static void noinstr el0_bti(struct pt_regs *regs)
485 enter_from_user_mode();
486 local_daif_restore(DAIF_PROCCTX);
490 static void noinstr el0_inv(struct pt_regs *regs, unsigned long esr)
492 enter_from_user_mode();
493 local_daif_restore(DAIF_PROCCTX);
494 bad_el0_sync(regs, 0, esr);
497 static void noinstr el0_dbg(struct pt_regs *regs, unsigned long esr)
499 /* Only watchpoints write FAR_EL1, otherwise its UNKNOWN */
500 unsigned long far = read_sysreg(far_el1);
502 enter_from_user_mode();
503 do_debug_exception(far, esr, regs);
504 local_daif_restore(DAIF_PROCCTX);
507 static void noinstr el0_svc(struct pt_regs *regs)
509 enter_from_user_mode();
510 cortex_a76_erratum_1463225_svc_handler();
514 static void noinstr el0_fpac(struct pt_regs *regs, unsigned long esr)
516 enter_from_user_mode();
517 local_daif_restore(DAIF_PROCCTX);
518 do_ptrauth_fault(regs, esr);
521 asmlinkage void noinstr el0t_64_sync_handler(struct pt_regs *regs)
523 unsigned long esr = read_sysreg(esr_el1);
525 switch (ESR_ELx_EC(esr)) {
526 case ESR_ELx_EC_SVC64:
529 case ESR_ELx_EC_DABT_LOW:
532 case ESR_ELx_EC_IABT_LOW:
535 case ESR_ELx_EC_FP_ASIMD:
536 el0_fpsimd_acc(regs, esr);
539 el0_sve_acc(regs, esr);
541 case ESR_ELx_EC_FP_EXC64:
542 el0_fpsimd_exc(regs, esr);
544 case ESR_ELx_EC_SYS64:
548 case ESR_ELx_EC_SP_ALIGN:
551 case ESR_ELx_EC_PC_ALIGN:
554 case ESR_ELx_EC_UNKNOWN:
560 case ESR_ELx_EC_BREAKPT_LOW:
561 case ESR_ELx_EC_SOFTSTP_LOW:
562 case ESR_ELx_EC_WATCHPT_LOW:
563 case ESR_ELx_EC_BRK64:
566 case ESR_ELx_EC_FPAC:
574 static void noinstr el0_interrupt(struct pt_regs *regs,
575 void (*handler)(struct pt_regs *))
577 enter_from_user_mode();
579 write_sysreg(DAIF_PROCCTX_NOIRQ, daif);
581 if (regs->pc & BIT(55))
582 arm64_apply_bp_hardening();
584 do_interrupt_handler(regs, handler);
587 static void noinstr __el0_irq_handler_common(struct pt_regs *regs)
589 el0_interrupt(regs, handle_arch_irq);
592 asmlinkage void noinstr el0t_64_irq_handler(struct pt_regs *regs)
594 __el0_irq_handler_common(regs);
597 static void noinstr __el0_fiq_handler_common(struct pt_regs *regs)
599 el0_interrupt(regs, handle_arch_fiq);
602 asmlinkage void noinstr el0t_64_fiq_handler(struct pt_regs *regs)
604 __el0_fiq_handler_common(regs);
607 static void noinstr __el0_error_handler_common(struct pt_regs *regs)
609 unsigned long esr = read_sysreg(esr_el1);
611 enter_from_user_mode();
612 local_daif_restore(DAIF_ERRCTX);
613 arm64_enter_nmi(regs);
614 do_serror(regs, esr);
615 arm64_exit_nmi(regs);
616 local_daif_restore(DAIF_PROCCTX);
619 asmlinkage void noinstr el0t_64_error_handler(struct pt_regs *regs)
621 __el0_error_handler_common(regs);
625 static void noinstr el0_cp15(struct pt_regs *regs, unsigned long esr)
627 enter_from_user_mode();
628 local_daif_restore(DAIF_PROCCTX);
629 do_cp15instr(esr, regs);
632 static void noinstr el0_svc_compat(struct pt_regs *regs)
634 enter_from_user_mode();
635 cortex_a76_erratum_1463225_svc_handler();
636 do_el0_svc_compat(regs);
639 asmlinkage void noinstr el0t_32_sync_handler(struct pt_regs *regs)
641 unsigned long esr = read_sysreg(esr_el1);
643 switch (ESR_ELx_EC(esr)) {
644 case ESR_ELx_EC_SVC32:
645 el0_svc_compat(regs);
647 case ESR_ELx_EC_DABT_LOW:
650 case ESR_ELx_EC_IABT_LOW:
653 case ESR_ELx_EC_FP_ASIMD:
654 el0_fpsimd_acc(regs, esr);
656 case ESR_ELx_EC_FP_EXC32:
657 el0_fpsimd_exc(regs, esr);
659 case ESR_ELx_EC_PC_ALIGN:
662 case ESR_ELx_EC_UNKNOWN:
663 case ESR_ELx_EC_CP14_MR:
664 case ESR_ELx_EC_CP14_LS:
665 case ESR_ELx_EC_CP14_64:
668 case ESR_ELx_EC_CP15_32:
669 case ESR_ELx_EC_CP15_64:
672 case ESR_ELx_EC_BREAKPT_LOW:
673 case ESR_ELx_EC_SOFTSTP_LOW:
674 case ESR_ELx_EC_WATCHPT_LOW:
675 case ESR_ELx_EC_BKPT32:
683 asmlinkage void noinstr el0t_32_irq_handler(struct pt_regs *regs)
685 __el0_irq_handler_common(regs);
688 asmlinkage void noinstr el0t_32_fiq_handler(struct pt_regs *regs)
690 __el0_fiq_handler_common(regs);
693 asmlinkage void noinstr el0t_32_error_handler(struct pt_regs *regs)
695 __el0_error_handler_common(regs);
697 #else /* CONFIG_COMPAT */
698 UNHANDLED(el0t, 32, sync)
699 UNHANDLED(el0t, 32, irq)
700 UNHANDLED(el0t, 32, fiq)
701 UNHANDLED(el0t, 32, error)
702 #endif /* CONFIG_COMPAT */
704 #ifdef CONFIG_VMAP_STACK
705 asmlinkage void noinstr handle_bad_stack(struct pt_regs *regs)
707 unsigned int esr = read_sysreg(esr_el1);
708 unsigned long far = read_sysreg(far_el1);
710 arm64_enter_nmi(regs);
711 panic_bad_stack(regs, esr, far);
713 #endif /* CONFIG_VMAP_STACK */
715 #ifdef CONFIG_ARM_SDE_INTERFACE
716 asmlinkage noinstr unsigned long
717 __sdei_handler(struct pt_regs *regs, struct sdei_registered_event *arg)
722 * We didn't take an exception to get here, so the HW hasn't
723 * set/cleared bits in PSTATE that we may rely on.
725 * The original SDEI spec (ARM DEN 0054A) can be read ambiguously as to
726 * whether PSTATE bits are inherited unchanged or generated from
727 * scratch, and the TF-A implementation always clears PAN and always
728 * clears UAO. There are no other known implementations.
730 * Subsequent revisions (ARM DEN 0054B) follow the usual rules for how
731 * PSTATE is modified upon architectural exceptions, and so PAN is
732 * either inherited or set per SCTLR_ELx.SPAN, and UAO is always
735 * We must explicitly reset PAN to the expected state, including
736 * clearing it when the host isn't using it, in case a VM had it set.
738 if (system_uses_hw_pan())
740 else if (cpu_has_pan())
743 arm64_enter_nmi(regs);
744 ret = do_sdei_event(regs, arg);
745 arm64_exit_nmi(regs);
749 #endif /* CONFIG_ARM_SDE_INTERFACE */