1 // SPDX-License-Identifier: GPL-2.0
3 * Exception handling code
5 * Copyright (C) 2019 ARM Ltd.
8 #include <linux/context_tracking.h>
9 #include <linux/kasan.h>
10 #include <linux/linkage.h>
11 #include <linux/lockdep.h>
12 #include <linux/ptrace.h>
13 #include <linux/sched.h>
14 #include <linux/sched/debug.h>
15 #include <linux/thread_info.h>
17 #include <asm/cpufeature.h>
18 #include <asm/daifflags.h>
20 #include <asm/exception.h>
21 #include <asm/irq_regs.h>
22 #include <asm/kprobes.h>
24 #include <asm/processor.h>
26 #include <asm/stacktrace.h>
27 #include <asm/sysreg.h>
28 #include <asm/system_misc.h>
31 * Handle IRQ/context state management when entering from kernel mode.
32 * Before this function is called it is not safe to call regular kernel code,
33 * instrumentable code, or any code which may trigger an exception.
35 * This is intended to match the logic in irqentry_enter(), handling the kernel
36 * mode transitions only.
38 static __always_inline void __enter_from_kernel_mode(struct pt_regs *regs)
40 regs->exit_rcu = false;
42 if (!IS_ENABLED(CONFIG_TINY_RCU) && is_idle_task(current)) {
43 lockdep_hardirqs_off(CALLER_ADDR0);
45 trace_hardirqs_off_finish();
47 regs->exit_rcu = true;
51 lockdep_hardirqs_off(CALLER_ADDR0);
52 rcu_irq_enter_check_tick();
53 trace_hardirqs_off_finish();
56 static void noinstr enter_from_kernel_mode(struct pt_regs *regs)
58 __enter_from_kernel_mode(regs);
59 mte_check_tfsr_entry();
60 mte_disable_tco_entry(current);
64 * Handle IRQ/context state management when exiting to kernel mode.
65 * After this function returns it is not safe to call regular kernel code,
66 * instrumentable code, or any code which may trigger an exception.
68 * This is intended to match the logic in irqentry_exit(), handling the kernel
69 * mode transitions only, and with preemption handled elsewhere.
71 static __always_inline void __exit_to_kernel_mode(struct pt_regs *regs)
73 lockdep_assert_irqs_disabled();
75 if (interrupts_enabled(regs)) {
77 trace_hardirqs_on_prepare();
78 lockdep_hardirqs_on_prepare();
80 lockdep_hardirqs_on(CALLER_ADDR0);
91 static void noinstr exit_to_kernel_mode(struct pt_regs *regs)
93 mte_check_tfsr_exit();
94 __exit_to_kernel_mode(regs);
98 * Handle IRQ/context state management when entering from user mode.
99 * Before this function is called it is not safe to call regular kernel code,
100 * instrumentable code, or any code which may trigger an exception.
102 static __always_inline void __enter_from_user_mode(void)
104 lockdep_hardirqs_off(CALLER_ADDR0);
105 CT_WARN_ON(ct_state() != CONTEXT_USER);
107 trace_hardirqs_off_finish();
108 mte_disable_tco_entry(current);
111 static __always_inline void enter_from_user_mode(struct pt_regs *regs)
113 __enter_from_user_mode();
117 * Handle IRQ/context state management when exiting to user mode.
118 * After this function returns it is not safe to call regular kernel code,
119 * instrumentable code, or any code which may trigger an exception.
121 static __always_inline void __exit_to_user_mode(void)
123 trace_hardirqs_on_prepare();
124 lockdep_hardirqs_on_prepare();
126 lockdep_hardirqs_on(CALLER_ADDR0);
129 static __always_inline void exit_to_user_mode_prepare(struct pt_regs *regs)
135 flags = read_thread_flags();
136 if (unlikely(flags & _TIF_WORK_MASK))
137 do_notify_resume(regs, flags);
142 static __always_inline void exit_to_user_mode(struct pt_regs *regs)
144 exit_to_user_mode_prepare(regs);
145 mte_check_tfsr_exit();
146 __exit_to_user_mode();
149 asmlinkage void noinstr asm_exit_to_user_mode(struct pt_regs *regs)
151 exit_to_user_mode(regs);
155 * Handle IRQ/context state management when entering an NMI from user/kernel
156 * mode. Before this function is called it is not safe to call regular kernel
157 * code, instrumentable code, or any code which may trigger an exception.
159 static void noinstr arm64_enter_nmi(struct pt_regs *regs)
161 regs->lockdep_hardirqs = lockdep_hardirqs_enabled();
164 lockdep_hardirqs_off(CALLER_ADDR0);
165 lockdep_hardirq_enter();
168 trace_hardirqs_off_finish();
173 * Handle IRQ/context state management when exiting an NMI from user/kernel
174 * mode. After this function returns it is not safe to call regular kernel
175 * code, instrumentable code, or any code which may trigger an exception.
177 static void noinstr arm64_exit_nmi(struct pt_regs *regs)
179 bool restore = regs->lockdep_hardirqs;
183 trace_hardirqs_on_prepare();
184 lockdep_hardirqs_on_prepare();
188 lockdep_hardirq_exit();
190 lockdep_hardirqs_on(CALLER_ADDR0);
195 * Handle IRQ/context state management when entering a debug exception from
196 * kernel mode. Before this function is called it is not safe to call regular
197 * kernel code, instrumentable code, or any code which may trigger an exception.
199 static void noinstr arm64_enter_el1_dbg(struct pt_regs *regs)
201 regs->lockdep_hardirqs = lockdep_hardirqs_enabled();
203 lockdep_hardirqs_off(CALLER_ADDR0);
206 trace_hardirqs_off_finish();
210 * Handle IRQ/context state management when exiting a debug exception from
211 * kernel mode. After this function returns it is not safe to call regular
212 * kernel code, instrumentable code, or any code which may trigger an exception.
214 static void noinstr arm64_exit_el1_dbg(struct pt_regs *regs)
216 bool restore = regs->lockdep_hardirqs;
219 trace_hardirqs_on_prepare();
220 lockdep_hardirqs_on_prepare();
225 lockdep_hardirqs_on(CALLER_ADDR0);
228 #ifdef CONFIG_PREEMPT_DYNAMIC
229 DEFINE_STATIC_KEY_TRUE(sk_dynamic_irqentry_exit_cond_resched);
230 #define need_irq_preemption() \
231 (static_branch_unlikely(&sk_dynamic_irqentry_exit_cond_resched))
233 #define need_irq_preemption() (IS_ENABLED(CONFIG_PREEMPTION))
236 static void __sched arm64_preempt_schedule_irq(void)
238 if (!need_irq_preemption())
242 * Note: thread_info::preempt_count includes both thread_info::count
243 * and thread_info::need_resched, and is not equivalent to
246 if (READ_ONCE(current_thread_info()->preempt_count) != 0)
250 * DAIF.DA are cleared at the start of IRQ/FIQ handling, and when GIC
251 * priority masking is used the GIC irqchip driver will clear DAIF.IF
252 * using gic_arch_enable_irqs() for normal IRQs. If anything is set in
253 * DAIF we must have handled an NMI, so skip preemption.
255 if (system_uses_irq_prio_masking() && read_sysreg(daif))
259 * Preempting a task from an IRQ means we leave copies of PSTATE
260 * on the stack. cpufeature's enable calls may modify PSTATE, but
261 * resuming one of these preempted tasks would undo those changes.
263 * Only allow a task to be preempted once cpufeatures have been
266 if (system_capabilities_finalized())
267 preempt_schedule_irq();
270 static void do_interrupt_handler(struct pt_regs *regs,
271 void (*handler)(struct pt_regs *))
273 struct pt_regs *old_regs = set_irq_regs(regs);
275 if (on_thread_stack())
276 call_on_irq_stack(regs, handler);
280 set_irq_regs(old_regs);
283 extern void (*handle_arch_irq)(struct pt_regs *);
284 extern void (*handle_arch_fiq)(struct pt_regs *);
286 static void noinstr __panic_unhandled(struct pt_regs *regs, const char *vector,
289 arm64_enter_nmi(regs);
293 pr_crit("Unhandled %s exception on CPU%d, ESR 0x%016lx -- %s\n",
294 vector, smp_processor_id(), esr,
295 esr_get_class_string(esr));
298 panic("Unhandled exception");
301 #define UNHANDLED(el, regsize, vector) \
302 asmlinkage void noinstr el##_##regsize##_##vector##_handler(struct pt_regs *regs) \
304 const char *desc = #regsize "-bit " #el " " #vector; \
305 __panic_unhandled(regs, desc, read_sysreg(esr_el1)); \
308 #ifdef CONFIG_ARM64_ERRATUM_1463225
309 static DEFINE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa);
311 static void cortex_a76_erratum_1463225_svc_handler(void)
315 if (!unlikely(test_thread_flag(TIF_SINGLESTEP)))
318 if (!unlikely(this_cpu_has_cap(ARM64_WORKAROUND_1463225)))
321 __this_cpu_write(__in_cortex_a76_erratum_1463225_wa, 1);
322 reg = read_sysreg(mdscr_el1);
323 val = reg | DBG_MDSCR_SS | DBG_MDSCR_KDE;
324 write_sysreg(val, mdscr_el1);
325 asm volatile("msr daifclr, #8");
328 /* We will have taken a single-step exception by this point */
330 write_sysreg(reg, mdscr_el1);
331 __this_cpu_write(__in_cortex_a76_erratum_1463225_wa, 0);
334 static __always_inline bool
335 cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs)
337 if (!__this_cpu_read(__in_cortex_a76_erratum_1463225_wa))
341 * We've taken a dummy step exception from the kernel to ensure
342 * that interrupts are re-enabled on the syscall path. Return back
343 * to cortex_a76_erratum_1463225_svc_handler() with debug exceptions
344 * masked so that we can safely restore the mdscr and get on with
345 * handling the syscall.
347 regs->pstate |= PSR_D_BIT;
350 #else /* CONFIG_ARM64_ERRATUM_1463225 */
351 static void cortex_a76_erratum_1463225_svc_handler(void) { }
352 static bool cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs)
356 #endif /* CONFIG_ARM64_ERRATUM_1463225 */
358 UNHANDLED(el1t, 64, sync)
359 UNHANDLED(el1t, 64, irq)
360 UNHANDLED(el1t, 64, fiq)
361 UNHANDLED(el1t, 64, error)
363 static void noinstr el1_abort(struct pt_regs *regs, unsigned long esr)
365 unsigned long far = read_sysreg(far_el1);
367 enter_from_kernel_mode(regs);
368 local_daif_inherit(regs);
369 do_mem_abort(far, esr, regs);
371 exit_to_kernel_mode(regs);
374 static void noinstr el1_pc(struct pt_regs *regs, unsigned long esr)
376 unsigned long far = read_sysreg(far_el1);
378 enter_from_kernel_mode(regs);
379 local_daif_inherit(regs);
380 do_sp_pc_abort(far, esr, regs);
382 exit_to_kernel_mode(regs);
385 static void noinstr el1_undef(struct pt_regs *regs, unsigned long esr)
387 enter_from_kernel_mode(regs);
388 local_daif_inherit(regs);
389 do_el1_undef(regs, esr);
391 exit_to_kernel_mode(regs);
394 static void noinstr el1_bti(struct pt_regs *regs, unsigned long esr)
396 enter_from_kernel_mode(regs);
397 local_daif_inherit(regs);
398 do_el1_bti(regs, esr);
400 exit_to_kernel_mode(regs);
403 static void noinstr el1_dbg(struct pt_regs *regs, unsigned long esr)
405 unsigned long far = read_sysreg(far_el1);
407 arm64_enter_el1_dbg(regs);
408 if (!cortex_a76_erratum_1463225_debug_handler(regs))
409 do_debug_exception(far, esr, regs);
410 arm64_exit_el1_dbg(regs);
413 static void noinstr el1_fpac(struct pt_regs *regs, unsigned long esr)
415 enter_from_kernel_mode(regs);
416 local_daif_inherit(regs);
417 do_el1_fpac(regs, esr);
419 exit_to_kernel_mode(regs);
422 asmlinkage void noinstr el1h_64_sync_handler(struct pt_regs *regs)
424 unsigned long esr = read_sysreg(esr_el1);
426 switch (ESR_ELx_EC(esr)) {
427 case ESR_ELx_EC_DABT_CUR:
428 case ESR_ELx_EC_IABT_CUR:
429 el1_abort(regs, esr);
432 * We don't handle ESR_ELx_EC_SP_ALIGN, since we will have hit a
433 * recursive exception when trying to push the initial pt_regs.
435 case ESR_ELx_EC_PC_ALIGN:
438 case ESR_ELx_EC_SYS64:
439 case ESR_ELx_EC_UNKNOWN:
440 el1_undef(regs, esr);
445 case ESR_ELx_EC_BREAKPT_CUR:
446 case ESR_ELx_EC_SOFTSTP_CUR:
447 case ESR_ELx_EC_WATCHPT_CUR:
448 case ESR_ELx_EC_BRK64:
451 case ESR_ELx_EC_FPAC:
455 __panic_unhandled(regs, "64-bit el1h sync", esr);
459 static __always_inline void __el1_pnmi(struct pt_regs *regs,
460 void (*handler)(struct pt_regs *))
462 arm64_enter_nmi(regs);
463 do_interrupt_handler(regs, handler);
464 arm64_exit_nmi(regs);
467 static __always_inline void __el1_irq(struct pt_regs *regs,
468 void (*handler)(struct pt_regs *))
470 enter_from_kernel_mode(regs);
473 do_interrupt_handler(regs, handler);
476 arm64_preempt_schedule_irq();
478 exit_to_kernel_mode(regs);
480 static void noinstr el1_interrupt(struct pt_regs *regs,
481 void (*handler)(struct pt_regs *))
483 write_sysreg(DAIF_PROCCTX_NOIRQ, daif);
485 if (IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && !interrupts_enabled(regs))
486 __el1_pnmi(regs, handler);
488 __el1_irq(regs, handler);
491 asmlinkage void noinstr el1h_64_irq_handler(struct pt_regs *regs)
493 el1_interrupt(regs, handle_arch_irq);
496 asmlinkage void noinstr el1h_64_fiq_handler(struct pt_regs *regs)
498 el1_interrupt(regs, handle_arch_fiq);
501 asmlinkage void noinstr el1h_64_error_handler(struct pt_regs *regs)
503 unsigned long esr = read_sysreg(esr_el1);
505 local_daif_restore(DAIF_ERRCTX);
506 arm64_enter_nmi(regs);
507 do_serror(regs, esr);
508 arm64_exit_nmi(regs);
511 static void noinstr el0_da(struct pt_regs *regs, unsigned long esr)
513 unsigned long far = read_sysreg(far_el1);
515 enter_from_user_mode(regs);
516 local_daif_restore(DAIF_PROCCTX);
517 do_mem_abort(far, esr, regs);
518 exit_to_user_mode(regs);
521 static void noinstr el0_ia(struct pt_regs *regs, unsigned long esr)
523 unsigned long far = read_sysreg(far_el1);
526 * We've taken an instruction abort from userspace and not yet
527 * re-enabled IRQs. If the address is a kernel address, apply
528 * BP hardening prior to enabling IRQs and pre-emption.
530 if (!is_ttbr0_addr(far))
531 arm64_apply_bp_hardening();
533 enter_from_user_mode(regs);
534 local_daif_restore(DAIF_PROCCTX);
535 do_mem_abort(far, esr, regs);
536 exit_to_user_mode(regs);
539 static void noinstr el0_fpsimd_acc(struct pt_regs *regs, unsigned long esr)
541 enter_from_user_mode(regs);
542 local_daif_restore(DAIF_PROCCTX);
543 do_fpsimd_acc(esr, regs);
544 exit_to_user_mode(regs);
547 static void noinstr el0_sve_acc(struct pt_regs *regs, unsigned long esr)
549 enter_from_user_mode(regs);
550 local_daif_restore(DAIF_PROCCTX);
551 do_sve_acc(esr, regs);
552 exit_to_user_mode(regs);
555 static void noinstr el0_sme_acc(struct pt_regs *regs, unsigned long esr)
557 enter_from_user_mode(regs);
558 local_daif_restore(DAIF_PROCCTX);
559 do_sme_acc(esr, regs);
560 exit_to_user_mode(regs);
563 static void noinstr el0_fpsimd_exc(struct pt_regs *regs, unsigned long esr)
565 enter_from_user_mode(regs);
566 local_daif_restore(DAIF_PROCCTX);
567 do_fpsimd_exc(esr, regs);
568 exit_to_user_mode(regs);
571 static void noinstr el0_sys(struct pt_regs *regs, unsigned long esr)
573 enter_from_user_mode(regs);
574 local_daif_restore(DAIF_PROCCTX);
575 do_el0_sys(esr, regs);
576 exit_to_user_mode(regs);
579 static void noinstr el0_pc(struct pt_regs *regs, unsigned long esr)
581 unsigned long far = read_sysreg(far_el1);
583 if (!is_ttbr0_addr(instruction_pointer(regs)))
584 arm64_apply_bp_hardening();
586 enter_from_user_mode(regs);
587 local_daif_restore(DAIF_PROCCTX);
588 do_sp_pc_abort(far, esr, regs);
589 exit_to_user_mode(regs);
592 static void noinstr el0_sp(struct pt_regs *regs, unsigned long esr)
594 enter_from_user_mode(regs);
595 local_daif_restore(DAIF_PROCCTX);
596 do_sp_pc_abort(regs->sp, esr, regs);
597 exit_to_user_mode(regs);
600 static void noinstr el0_undef(struct pt_regs *regs, unsigned long esr)
602 enter_from_user_mode(regs);
603 local_daif_restore(DAIF_PROCCTX);
604 do_el0_undef(regs, esr);
605 exit_to_user_mode(regs);
608 static void noinstr el0_bti(struct pt_regs *regs)
610 enter_from_user_mode(regs);
611 local_daif_restore(DAIF_PROCCTX);
613 exit_to_user_mode(regs);
616 static void noinstr el0_mops(struct pt_regs *regs, unsigned long esr)
618 enter_from_user_mode(regs);
619 local_daif_restore(DAIF_PROCCTX);
620 do_el0_mops(regs, esr);
621 exit_to_user_mode(regs);
624 static void noinstr el0_inv(struct pt_regs *regs, unsigned long esr)
626 enter_from_user_mode(regs);
627 local_daif_restore(DAIF_PROCCTX);
628 bad_el0_sync(regs, 0, esr);
629 exit_to_user_mode(regs);
632 static void noinstr el0_dbg(struct pt_regs *regs, unsigned long esr)
634 /* Only watchpoints write FAR_EL1, otherwise its UNKNOWN */
635 unsigned long far = read_sysreg(far_el1);
637 enter_from_user_mode(regs);
638 do_debug_exception(far, esr, regs);
639 local_daif_restore(DAIF_PROCCTX);
640 exit_to_user_mode(regs);
643 static void noinstr el0_svc(struct pt_regs *regs)
645 enter_from_user_mode(regs);
646 cortex_a76_erratum_1463225_svc_handler();
648 exit_to_user_mode(regs);
651 static void noinstr el0_fpac(struct pt_regs *regs, unsigned long esr)
653 enter_from_user_mode(regs);
654 local_daif_restore(DAIF_PROCCTX);
655 do_el0_fpac(regs, esr);
656 exit_to_user_mode(regs);
659 asmlinkage void noinstr el0t_64_sync_handler(struct pt_regs *regs)
661 unsigned long esr = read_sysreg(esr_el1);
663 switch (ESR_ELx_EC(esr)) {
664 case ESR_ELx_EC_SVC64:
667 case ESR_ELx_EC_DABT_LOW:
670 case ESR_ELx_EC_IABT_LOW:
673 case ESR_ELx_EC_FP_ASIMD:
674 el0_fpsimd_acc(regs, esr);
677 el0_sve_acc(regs, esr);
680 el0_sme_acc(regs, esr);
682 case ESR_ELx_EC_FP_EXC64:
683 el0_fpsimd_exc(regs, esr);
685 case ESR_ELx_EC_SYS64:
689 case ESR_ELx_EC_SP_ALIGN:
692 case ESR_ELx_EC_PC_ALIGN:
695 case ESR_ELx_EC_UNKNOWN:
696 el0_undef(regs, esr);
701 case ESR_ELx_EC_MOPS:
704 case ESR_ELx_EC_BREAKPT_LOW:
705 case ESR_ELx_EC_SOFTSTP_LOW:
706 case ESR_ELx_EC_WATCHPT_LOW:
707 case ESR_ELx_EC_BRK64:
710 case ESR_ELx_EC_FPAC:
718 static void noinstr el0_interrupt(struct pt_regs *regs,
719 void (*handler)(struct pt_regs *))
721 enter_from_user_mode(regs);
723 write_sysreg(DAIF_PROCCTX_NOIRQ, daif);
725 if (regs->pc & BIT(55))
726 arm64_apply_bp_hardening();
729 do_interrupt_handler(regs, handler);
732 exit_to_user_mode(regs);
735 static void noinstr __el0_irq_handler_common(struct pt_regs *regs)
737 el0_interrupt(regs, handle_arch_irq);
740 asmlinkage void noinstr el0t_64_irq_handler(struct pt_regs *regs)
742 __el0_irq_handler_common(regs);
745 static void noinstr __el0_fiq_handler_common(struct pt_regs *regs)
747 el0_interrupt(regs, handle_arch_fiq);
750 asmlinkage void noinstr el0t_64_fiq_handler(struct pt_regs *regs)
752 __el0_fiq_handler_common(regs);
755 static void noinstr __el0_error_handler_common(struct pt_regs *regs)
757 unsigned long esr = read_sysreg(esr_el1);
759 enter_from_user_mode(regs);
760 local_daif_restore(DAIF_ERRCTX);
761 arm64_enter_nmi(regs);
762 do_serror(regs, esr);
763 arm64_exit_nmi(regs);
764 local_daif_restore(DAIF_PROCCTX);
765 exit_to_user_mode(regs);
768 asmlinkage void noinstr el0t_64_error_handler(struct pt_regs *regs)
770 __el0_error_handler_common(regs);
774 static void noinstr el0_cp15(struct pt_regs *regs, unsigned long esr)
776 enter_from_user_mode(regs);
777 local_daif_restore(DAIF_PROCCTX);
778 do_el0_cp15(esr, regs);
779 exit_to_user_mode(regs);
782 static void noinstr el0_svc_compat(struct pt_regs *regs)
784 enter_from_user_mode(regs);
785 cortex_a76_erratum_1463225_svc_handler();
786 do_el0_svc_compat(regs);
787 exit_to_user_mode(regs);
790 asmlinkage void noinstr el0t_32_sync_handler(struct pt_regs *regs)
792 unsigned long esr = read_sysreg(esr_el1);
794 switch (ESR_ELx_EC(esr)) {
795 case ESR_ELx_EC_SVC32:
796 el0_svc_compat(regs);
798 case ESR_ELx_EC_DABT_LOW:
801 case ESR_ELx_EC_IABT_LOW:
804 case ESR_ELx_EC_FP_ASIMD:
805 el0_fpsimd_acc(regs, esr);
807 case ESR_ELx_EC_FP_EXC32:
808 el0_fpsimd_exc(regs, esr);
810 case ESR_ELx_EC_PC_ALIGN:
813 case ESR_ELx_EC_UNKNOWN:
814 case ESR_ELx_EC_CP14_MR:
815 case ESR_ELx_EC_CP14_LS:
816 case ESR_ELx_EC_CP14_64:
817 el0_undef(regs, esr);
819 case ESR_ELx_EC_CP15_32:
820 case ESR_ELx_EC_CP15_64:
823 case ESR_ELx_EC_BREAKPT_LOW:
824 case ESR_ELx_EC_SOFTSTP_LOW:
825 case ESR_ELx_EC_WATCHPT_LOW:
826 case ESR_ELx_EC_BKPT32:
834 asmlinkage void noinstr el0t_32_irq_handler(struct pt_regs *regs)
836 __el0_irq_handler_common(regs);
839 asmlinkage void noinstr el0t_32_fiq_handler(struct pt_regs *regs)
841 __el0_fiq_handler_common(regs);
844 asmlinkage void noinstr el0t_32_error_handler(struct pt_regs *regs)
846 __el0_error_handler_common(regs);
848 #else /* CONFIG_COMPAT */
849 UNHANDLED(el0t, 32, sync)
850 UNHANDLED(el0t, 32, irq)
851 UNHANDLED(el0t, 32, fiq)
852 UNHANDLED(el0t, 32, error)
853 #endif /* CONFIG_COMPAT */
855 #ifdef CONFIG_VMAP_STACK
856 asmlinkage void noinstr __noreturn handle_bad_stack(struct pt_regs *regs)
858 unsigned long esr = read_sysreg(esr_el1);
859 unsigned long far = read_sysreg(far_el1);
861 arm64_enter_nmi(regs);
862 panic_bad_stack(regs, esr, far);
864 #endif /* CONFIG_VMAP_STACK */
866 #ifdef CONFIG_ARM_SDE_INTERFACE
867 asmlinkage noinstr unsigned long
868 __sdei_handler(struct pt_regs *regs, struct sdei_registered_event *arg)
873 * We didn't take an exception to get here, so the HW hasn't
874 * set/cleared bits in PSTATE that we may rely on.
876 * The original SDEI spec (ARM DEN 0054A) can be read ambiguously as to
877 * whether PSTATE bits are inherited unchanged or generated from
878 * scratch, and the TF-A implementation always clears PAN and always
879 * clears UAO. There are no other known implementations.
881 * Subsequent revisions (ARM DEN 0054B) follow the usual rules for how
882 * PSTATE is modified upon architectural exceptions, and so PAN is
883 * either inherited or set per SCTLR_ELx.SPAN, and UAO is always
886 * We must explicitly reset PAN to the expected state, including
887 * clearing it when the host isn't using it, in case a VM had it set.
889 if (system_uses_hw_pan())
891 else if (cpu_has_pan())
894 arm64_enter_nmi(regs);
895 ret = do_sdei_event(regs, arg);
896 arm64_exit_nmi(regs);
900 #endif /* CONFIG_ARM_SDE_INTERFACE */