arch/arm64/kernel/cpuinfo.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Record and handle CPU attributes.
   4  *
   5  * Copyright (C) 2014 ARM Ltd.
   6  */
   7 #include <asm/arch_timer.h>
   8 #include <asm/cache.h>
   9 #include <asm/cpu.h>
  10 #include <asm/cputype.h>
  11 #include <asm/cpufeature.h>
  12 #include <asm/fpsimd.h>
  13
  14 #include <linux/bitops.h>
  15 #include <linux/bug.h>
  16 #include <linux/compat.h>
  17 #include <linux/elf.h>
  18 #include <linux/init.h>
  19 #include <linux/kernel.h>
  20 #include <linux/personality.h>
  21 #include <linux/preempt.h>
  22 #include <linux/printk.h>
  23 #include <linux/seq_file.h>
  24 #include <linux/sched.h>
  25 #include <linux/smp.h>
  26 #include <linux/delay.h>
  27
  28 /*
  29  * In case the boot CPU is hotpluggable, we record its initial state and
  30  * current state separately. Certain system registers may contain different
  31  * values depending on configuration at or after reset.
  32  */
  33 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
  34 static struct cpuinfo_arm64 boot_cpu_data;
  35
  36 static const char *icache_policy_str[] = {
  37         [ICACHE_POLICY_VPIPT]           = "VPIPT",
  38         [ICACHE_POLICY_RESERVED]        = "RESERVED/UNKNOWN",
  39         [ICACHE_POLICY_VIPT]            = "VIPT",
  40         [ICACHE_POLICY_PIPT]            = "PIPT",
  41 };
  42
  43 unsigned long __icache_flags;
  44
  45 static const char *const hwcap_str[] = {
  46         [KERNEL_HWCAP_FP]               = "fp",
  47         [KERNEL_HWCAP_ASIMD]            = "asimd",
  48         [KERNEL_HWCAP_EVTSTRM]          = "evtstrm",
  49         [KERNEL_HWCAP_AES]              = "aes",
  50         [KERNEL_HWCAP_PMULL]            = "pmull",
  51         [KERNEL_HWCAP_SHA1]             = "sha1",
  52         [KERNEL_HWCAP_SHA2]             = "sha2",
  53         [KERNEL_HWCAP_CRC32]            = "crc32",
  54         [KERNEL_HWCAP_ATOMICS]          = "atomics",
  55         [KERNEL_HWCAP_FPHP]             = "fphp",
  56         [KERNEL_HWCAP_ASIMDHP]          = "asimdhp",
  57         [KERNEL_HWCAP_CPUID]            = "cpuid",
  58         [KERNEL_HWCAP_ASIMDRDM]         = "asimdrdm",
  59         [KERNEL_HWCAP_JSCVT]            = "jscvt",
  60         [KERNEL_HWCAP_FCMA]             = "fcma",
  61         [KERNEL_HWCAP_LRCPC]            = "lrcpc",
  62         [KERNEL_HWCAP_DCPOP]            = "dcpop",
  63         [KERNEL_HWCAP_SHA3]             = "sha3",
  64         [KERNEL_HWCAP_SM3]              = "sm3",
  65         [KERNEL_HWCAP_SM4]              = "sm4",
  66         [KERNEL_HWCAP_ASIMDDP]          = "asimddp",
  67         [KERNEL_HWCAP_SHA512]           = "sha512",
  68         [KERNEL_HWCAP_SVE]              = "sve",
  69         [KERNEL_HWCAP_ASIMDFHM]         = "asimdfhm",
  70         [KERNEL_HWCAP_DIT]              = "dit",
  71         [KERNEL_HWCAP_USCAT]            = "uscat",
  72         [KERNEL_HWCAP_ILRCPC]           = "ilrcpc",
  73         [KERNEL_HWCAP_FLAGM]            = "flagm",
  74         [KERNEL_HWCAP_SSBS]             = "ssbs",
  75         [KERNEL_HWCAP_SB]               = "sb",
  76         [KERNEL_HWCAP_PACA]             = "paca",
  77         [KERNEL_HWCAP_PACG]             = "pacg",
  78         [KERNEL_HWCAP_DCPODP]           = "dcpodp",
  79         [KERNEL_HWCAP_SVE2]             = "sve2",
  80         [KERNEL_HWCAP_SVEAES]           = "sveaes",
  81         [KERNEL_HWCAP_SVEPMULL]         = "svepmull",
  82         [KERNEL_HWCAP_SVEBITPERM]       = "svebitperm",
  83         [KERNEL_HWCAP_SVESHA3]          = "svesha3",
  84         [KERNEL_HWCAP_SVESM4]           = "svesm4",
  85         [KERNEL_HWCAP_FLAGM2]           = "flagm2",
  86         [KERNEL_HWCAP_FRINT]            = "frint",
  87         [KERNEL_HWCAP_SVEI8MM]          = "svei8mm",
  88         [KERNEL_HWCAP_SVEF32MM]         = "svef32mm",
  89         [KERNEL_HWCAP_SVEF64MM]         = "svef64mm",
  90         [KERNEL_HWCAP_SVEBF16]          = "svebf16",
  91         [KERNEL_HWCAP_I8MM]             = "i8mm",
  92         [KERNEL_HWCAP_BF16]             = "bf16",
  93         [KERNEL_HWCAP_DGH]              = "dgh",
  94         [KERNEL_HWCAP_RNG]              = "rng",
  95         [KERNEL_HWCAP_BTI]              = "bti",
  96         [KERNEL_HWCAP_MTE]              = "mte",
  97         [KERNEL_HWCAP_ECV]              = "ecv",
  98         [KERNEL_HWCAP_AFP]              = "afp",
  99         [KERNEL_HWCAP_RPRES]            = "rpres",
 100         [KERNEL_HWCAP_MTE3]             = "mte3",
 101         [KERNEL_HWCAP_SME]              = "sme",
 102         [KERNEL_HWCAP_SME_I16I64]       = "smei16i64",
 103         [KERNEL_HWCAP_SME_F64F64]       = "smef64f64",
 104         [KERNEL_HWCAP_SME_I8I32]        = "smei8i32",
 105         [KERNEL_HWCAP_SME_F16F32]       = "smef16f32",
 106         [KERNEL_HWCAP_SME_B16F32]       = "smeb16f32",
 107         [KERNEL_HWCAP_SME_F32F32]       = "smef32f32",
 108         [KERNEL_HWCAP_SME_FA64]         = "smefa64",
 109         [KERNEL_HWCAP_WFXT]             = "wfxt",
 110 };
 111
 112 #ifdef CONFIG_COMPAT
 113 #define COMPAT_KERNEL_HWCAP(x)  const_ilog2(COMPAT_HWCAP_ ## x)
 114 static const char *const compat_hwcap_str[] = {
 115         [COMPAT_KERNEL_HWCAP(SWP)]      = "swp",
 116         [COMPAT_KERNEL_HWCAP(HALF)]     = "half",
 117         [COMPAT_KERNEL_HWCAP(THUMB)]    = "thumb",
 118         [COMPAT_KERNEL_HWCAP(26BIT)]    = NULL, /* Not possible on arm64 */
 119         [COMPAT_KERNEL_HWCAP(FAST_MULT)] = "fastmult",
 120         [COMPAT_KERNEL_HWCAP(FPA)]      = NULL, /* Not possible on arm64 */
 121         [COMPAT_KERNEL_HWCAP(VFP)]      = "vfp",
 122         [COMPAT_KERNEL_HWCAP(EDSP)]     = "edsp",
 123         [COMPAT_KERNEL_HWCAP(JAVA)]     = NULL, /* Not possible on arm64 */
 124         [COMPAT_KERNEL_HWCAP(IWMMXT)]   = NULL, /* Not possible on arm64 */
 125         [COMPAT_KERNEL_HWCAP(CRUNCH)]   = NULL, /* Not possible on arm64 */
 126         [COMPAT_KERNEL_HWCAP(THUMBEE)]  = NULL, /* Not possible on arm64 */
 127         [COMPAT_KERNEL_HWCAP(NEON)]     = "neon",
 128         [COMPAT_KERNEL_HWCAP(VFPv3)]    = "vfpv3",
 129         [COMPAT_KERNEL_HWCAP(VFPV3D16)] = NULL, /* Not possible on arm64 */
 130         [COMPAT_KERNEL_HWCAP(TLS)]      = "tls",
 131         [COMPAT_KERNEL_HWCAP(VFPv4)]    = "vfpv4",
 132         [COMPAT_KERNEL_HWCAP(IDIVA)]    = "idiva",
 133         [COMPAT_KERNEL_HWCAP(IDIVT)]    = "idivt",
 134         [COMPAT_KERNEL_HWCAP(VFPD32)]   = NULL, /* Not possible on arm64 */
 135         [COMPAT_KERNEL_HWCAP(LPAE)]     = "lpae",
 136         [COMPAT_KERNEL_HWCAP(EVTSTRM)]  = "evtstrm",
 137 };
 138
 139 #define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_ ## x)
 140 static const char *const compat_hwcap2_str[] = {
 141         [COMPAT_KERNEL_HWCAP2(AES)]     = "aes",
 142         [COMPAT_KERNEL_HWCAP2(PMULL)]   = "pmull",
 143         [COMPAT_KERNEL_HWCAP2(SHA1)]    = "sha1",
 144         [COMPAT_KERNEL_HWCAP2(SHA2)]    = "sha2",
 145         [COMPAT_KERNEL_HWCAP2(CRC32)]   = "crc32",
 146 };
 147 #endif /* CONFIG_COMPAT */
 148
 149 static int c_show(struct seq_file *m, void *v)
 150 {
 151         int i, j;
 152         bool compat = personality(current->personality) == PER_LINUX32;
 153
 154         for_each_online_cpu(i) {
 155                 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
 156                 u32 midr = cpuinfo->reg_midr;
 157
 158                 /*
 159                  * glibc reads /proc/cpuinfo to determine the number of
 160                  * online processors, looking for lines beginning with
 161                  * "processor".  Give glibc what it expects.
 162                  */
 163                 seq_printf(m, "processor\t: %d\n", i);
 164                 if (compat)
 165                         seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
 166                                    MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
 167
 168                 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
 169                            loops_per_jiffy / (500000UL/HZ),
 170                            loops_per_jiffy / (5000UL/HZ) % 100);
 171
 172                 /*
 173                  * Dump out the common processor features in a single line.
 174                  * Userspace should read the hwcaps with getauxval(AT_HWCAP)
 175                  * rather than attempting to parse this, but there's a body of
 176                  * software which does already (at least for 32-bit).
 177                  */
 178                 seq_puts(m, "Features\t:");
 179                 if (compat) {
 180 #ifdef CONFIG_COMPAT
 181                         for (j = 0; j < ARRAY_SIZE(compat_hwcap_str); j++) {
 182                                 if (compat_elf_hwcap & (1 << j)) {
 183                                         /*
 184                                          * Warn once if any feature should not
 185                                          * have been present on arm64 platform.
 186                                          */
 187                                         if (WARN_ON_ONCE(!compat_hwcap_str[j]))
 188                                                 continue;
 189
 190                                         seq_printf(m, " %s", compat_hwcap_str[j]);
 191                                 }
 192                         }
 193
 194                         for (j = 0; j < ARRAY_SIZE(compat_hwcap2_str); j++)
 195                                 if (compat_elf_hwcap2 & (1 << j))
 196                                         seq_printf(m, " %s", compat_hwcap2_str[j]);
 197 #endif /* CONFIG_COMPAT */
 198                 } else {
 199                         for (j = 0; j < ARRAY_SIZE(hwcap_str); j++)
 200                                 if (cpu_have_feature(j))
 201                                         seq_printf(m, " %s", hwcap_str[j]);
 202                 }
 203                 seq_puts(m, "\n");
 204
 205                 seq_printf(m, "CPU implementer\t: 0x%02x\n",
 206                            MIDR_IMPLEMENTOR(midr));
 207                 seq_printf(m, "CPU architecture: 8\n");
 208                 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
 209                 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
 210                 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
 211         }
 212
 213         return 0;
 214 }
 215
 216 static void *c_start(struct seq_file *m, loff_t *pos)
 217 {
 218         return *pos < 1 ? (void *)1 : NULL;
 219 }
 220
 221 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
 222 {
 223         ++*pos;
 224         return NULL;
 225 }
 226
 227 static void c_stop(struct seq_file *m, void *v)
 228 {
 229 }
 230
 231 const struct seq_operations cpuinfo_op = {
 232         .start  = c_start,
 233         .next   = c_next,
 234         .stop   = c_stop,
 235         .show   = c_show
 236 };
 237
 238
 239 static struct kobj_type cpuregs_kobj_type = {
 240         .sysfs_ops = &kobj_sysfs_ops,
 241 };
 242
 243 /*
 244  * The ARM ARM uses the phrase "32-bit register" to describe a register
 245  * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however
 246  * no statement is made as to whether the upper 32 bits will or will not
 247  * be made use of in future, and between ARM DDI 0487A.c and ARM DDI
 248  * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit.
 249  *
 250  * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit
 251  * registers, we expose them both as 64 bit values to cater for possible
 252  * future expansion without an ABI break.
 253  */
 254 #define kobj_to_cpuinfo(kobj)   container_of(kobj, struct cpuinfo_arm64, kobj)
 255 #define CPUREGS_ATTR_RO(_name, _field)                                          \
 256         static ssize_t _name##_show(struct kobject *kobj,                       \
 257                         struct kobj_attribute *attr, char *buf)                 \
 258         {                                                                       \
 259                 struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj);             \
 260                                                                                 \
 261                 if (info->reg_midr)                                             \
 262                         return sprintf(buf, "0x%016llx\n", info->reg_##_field); \
 263                 else                                                            \
 264                         return 0;                                               \
 265         }                                                                       \
 266         static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name)
 267
 268 CPUREGS_ATTR_RO(midr_el1, midr);
 269 CPUREGS_ATTR_RO(revidr_el1, revidr);
 270
 271 static struct attribute *cpuregs_id_attrs[] = {
 272         &cpuregs_attr_midr_el1.attr,
 273         &cpuregs_attr_revidr_el1.attr,
 274         NULL
 275 };
 276
 277 static const struct attribute_group cpuregs_attr_group = {
 278         .attrs = cpuregs_id_attrs,
 279         .name = "identification"
 280 };
 281
 282 static int cpuid_cpu_online(unsigned int cpu)
 283 {
 284         int rc;
 285         struct device *dev;
 286         struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
 287
 288         dev = get_cpu_device(cpu);
 289         if (!dev) {
 290                 rc = -ENODEV;
 291                 goto out;
 292         }
 293         rc = kobject_add(&info->kobj, &dev->kobj, "regs");
 294         if (rc)
 295                 goto out;
 296         rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group);
 297         if (rc)
 298                 kobject_del(&info->kobj);
 299 out:
 300         return rc;
 301 }
 302
 303 static int cpuid_cpu_offline(unsigned int cpu)
 304 {
 305         struct device *dev;
 306         struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
 307
 308         dev = get_cpu_device(cpu);
 309         if (!dev)
 310                 return -ENODEV;
 311         if (info->kobj.parent) {
 312                 sysfs_remove_group(&info->kobj, &cpuregs_attr_group);
 313                 kobject_del(&info->kobj);
 314         }
 315
 316         return 0;
 317 }
 318
 319 static int __init cpuinfo_regs_init(void)
 320 {
 321         int cpu, ret;
 322
 323         for_each_possible_cpu(cpu) {
 324                 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
 325
 326                 kobject_init(&info->kobj, &cpuregs_kobj_type);
 327         }
 328
 329         ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online",
 330                                 cpuid_cpu_online, cpuid_cpu_offline);
 331         if (ret < 0) {
 332                 pr_err("cpuinfo: failed to register hotplug callbacks.\n");
 333                 return ret;
 334         }
 335         return 0;
 336 }
 337 device_initcall(cpuinfo_regs_init);
 338
 339 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
 340 {
 341         unsigned int cpu = smp_processor_id();
 342         u32 l1ip = CTR_L1IP(info->reg_ctr);
 343
 344         switch (l1ip) {
 345         case ICACHE_POLICY_PIPT:
 346                 break;
 347         case ICACHE_POLICY_VPIPT:
 348                 set_bit(ICACHEF_VPIPT, &__icache_flags);
 349                 break;
 350         case ICACHE_POLICY_RESERVED:
 351         case ICACHE_POLICY_VIPT:
 352                 /* Assume aliasing */
 353                 set_bit(ICACHEF_ALIASING, &__icache_flags);
 354                 break;
 355         }
 356
 357         pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);
 358 }
 359
 360 static void __cpuinfo_store_cpu_32bit(struct cpuinfo_32bit *info)
 361 {
 362         info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
 363         info->reg_id_dfr1 = read_cpuid(ID_DFR1_EL1);
 364         info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
 365         info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
 366         info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
 367         info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
 368         info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
 369         info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
 370         info->reg_id_isar6 = read_cpuid(ID_ISAR6_EL1);
 371         info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
 372         info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
 373         info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
 374         info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
 375         info->reg_id_mmfr4 = read_cpuid(ID_MMFR4_EL1);
 376         info->reg_id_mmfr5 = read_cpuid(ID_MMFR5_EL1);
 377         info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
 378         info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
 379         info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1);
 380
 381         info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
 382         info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
 383         info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
 384 }
 385
 386 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
 387 {
 388         info->reg_cntfrq = arch_timer_get_cntfrq();
 389         /*
 390          * Use the effective value of the CTR_EL0 than the raw value
 391          * exposed by the CPU. CTR_EL0.IDC field value must be interpreted
 392          * with the CLIDR_EL1 fields to avoid triggering false warnings
 393          * when there is a mismatch across the CPUs. Keep track of the
 394          * effective value of the CTR_EL0 in our internal records for
 395          * accurate sanity check and feature enablement.
 396          */
 397         info->reg_ctr = read_cpuid_effective_cachetype();
 398         info->reg_dczid = read_cpuid(DCZID_EL0);
 399         info->reg_midr = read_cpuid_id();
 400         info->reg_revidr = read_cpuid(REVIDR_EL1);
 401
 402         info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
 403         info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
 404         info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
 405         info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
 406         info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1);
 407         info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
 408         info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
 409         info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
 410         info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
 411         info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
 412         info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1);
 413         info->reg_id_aa64smfr0 = read_cpuid(ID_AA64SMFR0_EL1);
 414
 415         if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
 416                 info->reg_gmid = read_cpuid(GMID_EL1);
 417
 418         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
 419                 __cpuinfo_store_cpu_32bit(&info->aarch32);
 420
 421         if (IS_ENABLED(CONFIG_ARM64_SVE) &&
 422             id_aa64pfr0_sve(info->reg_id_aa64pfr0))
 423                 info->reg_zcr = read_zcr_features();
 424
 425         if (IS_ENABLED(CONFIG_ARM64_SME) &&
 426             id_aa64pfr1_sme(info->reg_id_aa64pfr1))
 427                 info->reg_smcr = read_smcr_features();
 428
 429         cpuinfo_detect_icache_policy(info);
 430 }
 431
 432 void cpuinfo_store_cpu(void)
 433 {
 434         struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
 435         __cpuinfo_store_cpu(info);
 436         update_cpu_features(smp_processor_id(), info, &boot_cpu_data);
 437 }
 438
 439 void __init cpuinfo_store_boot_cpu(void)
 440 {
 441         struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0);
 442         __cpuinfo_store_cpu(info);
 443
 444         boot_cpu_data = *info;
 445         init_cpu_features(&boot_cpu_data);
 446 }