2 * Record and handle CPU attributes.
4 * Copyright (C) 2014 ARM Ltd.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <asm/arch_timer.h>
18 #include <asm/cache.h>
20 #include <asm/cputype.h>
21 #include <asm/cpufeature.h>
22 #include <asm/fpsimd.h>
24 #include <linux/bitops.h>
25 #include <linux/bug.h>
26 #include <linux/compat.h>
27 #include <linux/elf.h>
28 #include <linux/init.h>
29 #include <linux/kernel.h>
30 #include <linux/personality.h>
31 #include <linux/preempt.h>
32 #include <linux/printk.h>
33 #include <linux/seq_file.h>
34 #include <linux/sched.h>
35 #include <linux/smp.h>
36 #include <linux/delay.h>
39 * In case the boot CPU is hotpluggable, we record its initial state and
40 * current state separately. Certain system registers may contain different
41 * values depending on configuration at or after reset.
43 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
44 static struct cpuinfo_arm64 boot_cpu_data;
46 static char *icache_policy_str[] = {
47 [0 ... ICACHE_POLICY_PIPT] = "RESERVED/UNKNOWN",
48 [ICACHE_POLICY_VIPT] = "VIPT",
49 [ICACHE_POLICY_PIPT] = "PIPT",
50 [ICACHE_POLICY_VPIPT] = "VPIPT",
53 unsigned long __icache_flags;
55 static const char *const hwcap_str[] = {
100 static const char *const compat_hwcap_str[] = {
126 static const char *const compat_hwcap2_str[] = {
134 #endif /* CONFIG_COMPAT */
136 static int c_show(struct seq_file *m, void *v)
139 bool compat = personality(current->personality) == PER_LINUX32;
141 for_each_online_cpu(i) {
142 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
143 u32 midr = cpuinfo->reg_midr;
146 * glibc reads /proc/cpuinfo to determine the number of
147 * online processors, looking for lines beginning with
148 * "processor". Give glibc what it expects.
150 seq_printf(m, "processor\t: %d\n", i);
152 seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
153 MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
155 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
156 loops_per_jiffy / (500000UL/HZ),
157 loops_per_jiffy / (5000UL/HZ) % 100);
160 * Dump out the common processor features in a single line.
161 * Userspace should read the hwcaps with getauxval(AT_HWCAP)
162 * rather than attempting to parse this, but there's a body of
163 * software which does already (at least for 32-bit).
165 seq_puts(m, "Features\t:");
168 for (j = 0; compat_hwcap_str[j]; j++)
169 if (compat_elf_hwcap & (1 << j))
170 seq_printf(m, " %s", compat_hwcap_str[j]);
172 for (j = 0; compat_hwcap2_str[j]; j++)
173 if (compat_elf_hwcap2 & (1 << j))
174 seq_printf(m, " %s", compat_hwcap2_str[j]);
175 #endif /* CONFIG_COMPAT */
177 for (j = 0; hwcap_str[j]; j++)
178 if (cpu_have_feature(j))
179 seq_printf(m, " %s", hwcap_str[j]);
183 seq_printf(m, "CPU implementer\t: 0x%02x\n",
184 MIDR_IMPLEMENTOR(midr));
185 seq_printf(m, "CPU architecture: 8\n");
186 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
187 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
188 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
194 static void *c_start(struct seq_file *m, loff_t *pos)
196 return *pos < 1 ? (void *)1 : NULL;
199 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
205 static void c_stop(struct seq_file *m, void *v)
209 const struct seq_operations cpuinfo_op = {
217 static struct kobj_type cpuregs_kobj_type = {
218 .sysfs_ops = &kobj_sysfs_ops,
222 * The ARM ARM uses the phrase "32-bit register" to describe a register
223 * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however
224 * no statement is made as to whether the upper 32 bits will or will not
225 * be made use of in future, and between ARM DDI 0487A.c and ARM DDI
226 * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit.
228 * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit
229 * registers, we expose them both as 64 bit values to cater for possible
230 * future expansion without an ABI break.
232 #define kobj_to_cpuinfo(kobj) container_of(kobj, struct cpuinfo_arm64, kobj)
233 #define CPUREGS_ATTR_RO(_name, _field) \
234 static ssize_t _name##_show(struct kobject *kobj, \
235 struct kobj_attribute *attr, char *buf) \
237 struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \
239 if (info->reg_midr) \
240 return sprintf(buf, "0x%016x\n", info->reg_##_field); \
244 static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name)
246 CPUREGS_ATTR_RO(midr_el1, midr);
247 CPUREGS_ATTR_RO(revidr_el1, revidr);
249 static struct attribute *cpuregs_id_attrs[] = {
250 &cpuregs_attr_midr_el1.attr,
251 &cpuregs_attr_revidr_el1.attr,
255 static const struct attribute_group cpuregs_attr_group = {
256 .attrs = cpuregs_id_attrs,
257 .name = "identification"
260 static int cpuid_cpu_online(unsigned int cpu)
264 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
266 dev = get_cpu_device(cpu);
271 rc = kobject_add(&info->kobj, &dev->kobj, "regs");
274 rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group);
276 kobject_del(&info->kobj);
281 static int cpuid_cpu_offline(unsigned int cpu)
284 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
286 dev = get_cpu_device(cpu);
289 if (info->kobj.parent) {
290 sysfs_remove_group(&info->kobj, &cpuregs_attr_group);
291 kobject_del(&info->kobj);
297 static int __init cpuinfo_regs_init(void)
301 for_each_possible_cpu(cpu) {
302 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
304 kobject_init(&info->kobj, &cpuregs_kobj_type);
307 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online",
308 cpuid_cpu_online, cpuid_cpu_offline);
310 pr_err("cpuinfo: failed to register hotplug callbacks.\n");
315 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
317 unsigned int cpu = smp_processor_id();
318 u32 l1ip = CTR_L1IP(info->reg_ctr);
321 case ICACHE_POLICY_PIPT:
323 case ICACHE_POLICY_VPIPT:
324 set_bit(ICACHEF_VPIPT, &__icache_flags);
328 case ICACHE_POLICY_VIPT:
329 /* Assume aliasing */
330 set_bit(ICACHEF_ALIASING, &__icache_flags);
333 pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);
336 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
338 info->reg_cntfrq = arch_timer_get_cntfrq();
340 * Use the effective value of the CTR_EL0 than the raw value
341 * exposed by the CPU. CTR_E0.IDC field value must be interpreted
342 * with the CLIDR_EL1 fields to avoid triggering false warnings
343 * when there is a mismatch across the CPUs. Keep track of the
344 * effective value of the CTR_EL0 in our internal records for
345 * acurate sanity check and feature enablement.
347 info->reg_ctr = read_cpuid_effective_cachetype();
348 info->reg_dczid = read_cpuid(DCZID_EL0);
349 info->reg_midr = read_cpuid_id();
350 info->reg_revidr = read_cpuid(REVIDR_EL1);
352 info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
353 info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
354 info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
355 info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
356 info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
357 info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
358 info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
359 info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
360 info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
361 info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1);
363 /* Update the 32bit ID registers only if AArch32 is implemented */
364 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
365 info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
366 info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
367 info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
368 info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
369 info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
370 info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
371 info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
372 info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
373 info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
374 info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
375 info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
376 info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
377 info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
379 info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
380 info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
381 info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
384 if (IS_ENABLED(CONFIG_ARM64_SVE) &&
385 id_aa64pfr0_sve(info->reg_id_aa64pfr0))
386 info->reg_zcr = read_zcr_features();
388 cpuinfo_detect_icache_policy(info);
391 void cpuinfo_store_cpu(void)
393 struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
394 __cpuinfo_store_cpu(info);
395 update_cpu_features(smp_processor_id(), info, &boot_cpu_data);
398 void __init cpuinfo_store_boot_cpu(void)
400 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0);
401 __cpuinfo_store_cpu(info);
403 boot_cpu_data = *info;
404 init_cpu_features(&boot_cpu_data);
407 device_initcall(cpuinfo_regs_init);