1 // SPDX-License-Identifier: GPL-2.0-only
3 * Contains CPU feature definitions
5 * Copyright (C) 2015 ARM Ltd.
7 * A note for the weary kernel hacker: the code here is confusing and hard to
8 * follow! That's partly because it's solving a nasty problem, but also because
9 * there's a little bit of over-abstraction that tends to obscure what's going
10 * on behind a maze of helper functions and macros.
12 * The basic problem is that hardware folks have started gluing together CPUs
13 * with distinct architectural features; in some cases even creating SoCs where
14 * user-visible instructions are available only on a subset of the available
15 * cores. We try to address this by snapshotting the feature registers of the
16 * boot CPU and comparing these with the feature registers of each secondary
17 * CPU when bringing them up. If there is a mismatch, then we update the
18 * snapshot state to indicate the lowest-common denominator of the feature,
19 * known as the "safe" value. This snapshot state can be queried to view the
20 * "sanitised" value of a feature register.
22 * The sanitised register values are used to decide which capabilities we
23 * have in the system. These may be in the form of traditional "hwcaps"
24 * advertised to userspace or internal "cpucaps" which are used to configure
25 * things like alternative patching and static keys. While a feature mismatch
26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch
27 * may prevent a CPU from being onlined at all.
29 * Some implementation details worth remembering:
31 * - Mismatched features are *always* sanitised to a "safe" value, which
32 * usually indicates that the feature is not supported.
34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
35 * warning when onlining an offending CPU and the kernel will be tainted
36 * with TAINT_CPU_OUT_OF_SPEC.
38 * - Features marked as FTR_VISIBLE have their sanitised value visible to
39 * userspace. FTR_VISIBLE features in registers that are only visible
40 * to EL0 by trapping *must* have a corresponding HWCAP so that late
41 * onlining of CPUs cannot lead to features disappearing at runtime.
43 * - A "feature" is typically a 4-bit register field. A "capability" is the
44 * high-level description derived from the sanitised field value.
46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID
47 * scheme for fields in ID registers") to understand when feature fields
48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly).
50 * - KVM exposes its own view of the feature registers to guest operating
51 * systems regardless of FTR_VISIBLE. This is typically driven from the
52 * sanitised register values to allow virtual CPUs to be migrated between
53 * arbitrary physical CPUs, but some features not present on the host are
54 * also advertised and emulated. Look at sys_reg_descs[] for the gory
57 * - If the arm64_ftr_bits[] for a register has a missing field, then this
58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg().
59 * This is stronger than FTR_HIDDEN and can be used to hide features from
63 #define pr_fmt(fmt) "CPU features: " fmt
65 #include <linux/bsearch.h>
66 #include <linux/cpumask.h>
67 #include <linux/crash_dump.h>
68 #include <linux/sort.h>
69 #include <linux/stop_machine.h>
70 #include <linux/sysfs.h>
71 #include <linux/types.h>
72 #include <linux/minmax.h>
74 #include <linux/cpu.h>
75 #include <linux/kasan.h>
76 #include <linux/percpu.h>
79 #include <asm/cpufeature.h>
80 #include <asm/cpu_ops.h>
81 #include <asm/fpsimd.h>
83 #include <asm/kvm_host.h>
84 #include <asm/mmu_context.h>
86 #include <asm/processor.h>
88 #include <asm/sysreg.h>
89 #include <asm/traps.h>
90 #include <asm/vectors.h>
93 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
94 static unsigned long elf_hwcap __read_mostly;
97 #define COMPAT_ELF_HWCAP_DEFAULT \
98 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
99 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
100 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
102 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
103 unsigned int compat_elf_hwcap2 __read_mostly;
106 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
107 EXPORT_SYMBOL(cpu_hwcaps);
108 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
110 /* Need also bit for ARM64_CB_PATCH */
111 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
113 bool arm64_use_ng_mappings = false;
114 EXPORT_SYMBOL(arm64_use_ng_mappings);
116 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors;
119 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs
122 static bool __read_mostly allow_mismatched_32bit_el0;
125 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have
126 * seen at least one CPU capable of 32-bit EL0.
128 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0);
131 * Mask of CPUs supporting 32-bit EL0.
132 * Only valid if arm64_mismatched_32bit_el0 is enabled.
134 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly;
137 * Flag to indicate if we have computed the system wide
138 * capabilities based on the boot time active CPUs. This
139 * will be used to determine if a new booting CPU should
140 * go through the verification process to make sure that it
141 * supports the system capabilities, without using a hotplug
142 * notifier. This is also used to decide if we could use
143 * the fast path for checking constant CPU caps.
145 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
146 EXPORT_SYMBOL(arm64_const_caps_ready);
147 static inline void finalize_system_capabilities(void)
149 static_branch_enable(&arm64_const_caps_ready);
152 void dump_cpu_features(void)
154 /* file-wide pr_fmt adds "CPU features: " prefix */
155 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
158 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
159 EXPORT_SYMBOL(cpu_hwcap_keys);
161 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
164 .visible = VISIBLE, \
169 .safe_val = SAFE_VAL, \
172 /* Define a feature with unsigned values */
173 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
174 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
176 /* Define a feature with a signed value */
177 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
178 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
180 #define ARM64_FTR_END \
185 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
187 static bool __system_matches_cap(unsigned int n);
190 * NOTE: Any changes to the visibility of features should be kept in
191 * sync with the documentation of the CPU feature register ABI.
193 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
194 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0),
195 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0),
196 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0),
197 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0),
198 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0),
199 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0),
200 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0),
201 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0),
202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0),
203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0),
204 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0),
205 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0),
206 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0),
207 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0),
211 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
212 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0),
213 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0),
214 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0),
215 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0),
216 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
217 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
218 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
219 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
220 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
221 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
222 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
225 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
226 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0),
227 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
228 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0),
229 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
233 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
234 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_CLEARBHB_SHIFT, 4, 0),
235 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
236 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_APA3_SHIFT, 4, 0),
237 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
238 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_GPA3_SHIFT, 4, 0),
239 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_RPRES_SHIFT, 4, 0),
240 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_WFXT_SHIFT, 4, 0),
244 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
245 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
246 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
247 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
248 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0),
249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0),
250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0),
251 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
252 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
253 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
254 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
255 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
256 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
257 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
258 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
259 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY),
260 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY),
264 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
265 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
266 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SME_SHIFT, 4, 0),
267 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0),
268 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0),
269 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE),
270 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, ID_AA64PFR1_MTE_NI),
271 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
272 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI),
273 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0),
277 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
278 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
279 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0),
280 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
281 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0),
282 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
283 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0),
284 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
285 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
286 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
287 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
288 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
289 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0),
290 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
291 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
292 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
293 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
294 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
295 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
299 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = {
300 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
301 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_FA64_SHIFT, 1, 0),
302 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
303 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_I16I64_SHIFT, 4, 0),
304 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
305 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_F64F64_SHIFT, 1, 0),
306 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
307 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_I8I32_SHIFT, 4, 0),
308 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
309 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_F16F32_SHIFT, 1, 0),
310 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
311 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_B16F32_SHIFT, 1, 0),
312 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
313 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_F32F32_SHIFT, 1, 0),
317 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
318 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0),
319 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0),
320 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0),
322 * Page size not being supported at Stage-2 is not fatal. You
323 * just give up KVM if PAGE_SIZE isn't supported there. Go fix
324 * your favourite nesting hypervisor.
326 * There is a small corner case where the hypervisor explicitly
327 * advertises a given granule size at Stage-2 (value 2) on some
328 * vCPUs, and uses the fallback to Stage-1 (value 0) for other
329 * vCPUs. Although this is not forbidden by the architecture, it
330 * indicates that the hypervisor is being silly (or buggy).
332 * We make no effort to cope with this and pretend that if these
333 * fields are inconsistent across vCPUs, then it isn't worth
334 * trying to bring KVM up.
336 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1),
337 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1),
338 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1),
340 * We already refuse to boot CPUs that don't support our configured
341 * page size, so we can only detect mismatches for a page size other
342 * than the one we're currently using. Unfortunately, SoCs like this
343 * exist in the wild so, even though we don't like it, we'll have to go
344 * along with it and treat them as non-strict.
346 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
347 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
348 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
350 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
351 /* Linux shouldn't care about secure memory */
352 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
353 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
354 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
356 * Differing PARange is fine as long as all peripherals and memory are mapped
357 * within the minimum PARange of all CPUs
359 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
363 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
364 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_AFP_SHIFT, 4, 0),
365 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0),
366 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0),
367 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0),
368 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0),
369 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
370 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
371 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
372 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
373 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
374 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
378 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
379 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0),
380 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EVT_SHIFT, 4, 0),
381 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_BBM_SHIFT, 4, 0),
382 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0),
383 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
384 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IDS_SHIFT, 4, 0),
385 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
386 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_ST_SHIFT, 4, 0),
387 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_NV_SHIFT, 4, 0),
388 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CCIDX_SHIFT, 4, 0),
389 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
390 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
391 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
392 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
393 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
397 static const struct arm64_ftr_bits ftr_ctr[] = {
398 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
399 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
400 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
401 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
402 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
403 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
405 * Linux can handle differing I-cache policies. Userspace JITs will
406 * make use of *minLine.
407 * If we have differing I-cache policies, report it as the weakest - VIPT.
409 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT), /* L1Ip */
410 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
414 static struct arm64_ftr_override __ro_after_init no_override = { };
416 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
417 .name = "SYS_CTR_EL0",
419 .override = &no_override,
422 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
423 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf),
424 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0),
425 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0),
426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0),
427 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0),
428 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf),
429 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0),
430 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0),
434 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
435 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_DOUBLELOCK_SHIFT, 4, 0),
436 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
437 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
438 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
441 * We can instantiate multiple PMU instances with different levels
444 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
445 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
449 static const struct arm64_ftr_bits ftr_mvfr2[] = {
450 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0),
451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0),
455 static const struct arm64_ftr_bits ftr_dczid[] = {
456 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1),
457 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0),
461 static const struct arm64_ftr_bits ftr_gmid[] = {
462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, SYS_GMID_EL1_BS_SHIFT, 4, 0),
466 static const struct arm64_ftr_bits ftr_id_isar0[] = {
467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),
468 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),
469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0),
470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0),
471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0),
472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0),
473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0),
477 static const struct arm64_ftr_bits ftr_id_isar5[] = {
478 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
479 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
480 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
487 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0),
489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0),
490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0),
491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0),
492 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0),
493 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0),
494 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0),
497 * SpecSEI = 1 indicates that the PE might generate an SError on an
498 * external abort on speculative read. It is safe to assume that an
499 * SError might be generated than it will not be. Hence it has been
500 * classified as FTR_HIGHER_SAFE.
502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0),
506 static const struct arm64_ftr_bits ftr_id_isar4[] = {
507 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0),
508 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0),
509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0),
510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0),
511 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0),
512 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0),
513 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0),
514 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0),
518 static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
519 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0),
523 static const struct arm64_ftr_bits ftr_id_isar6[] = {
524 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),
525 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
526 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),
527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
528 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),
529 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0),
530 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0),
534 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
535 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0),
536 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0),
537 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0),
538 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0),
539 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0),
540 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0),
544 static const struct arm64_ftr_bits ftr_id_pfr1[] = {
545 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0),
546 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0),
547 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0),
548 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0),
549 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0),
550 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0),
551 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0),
552 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0),
556 static const struct arm64_ftr_bits ftr_id_pfr2[] = {
557 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0),
558 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0),
562 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
563 /* [31:28] TraceFilt */
564 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_PERFMON_SHIFT, 4, 0xf),
565 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0),
566 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0),
567 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0),
568 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0),
569 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0),
570 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0),
574 static const struct arm64_ftr_bits ftr_id_dfr1[] = {
575 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0),
579 static const struct arm64_ftr_bits ftr_zcr[] = {
580 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
581 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_WIDTH, 0), /* LEN */
585 static const struct arm64_ftr_bits ftr_smcr[] = {
586 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
587 SMCR_ELx_LEN_SHIFT, SMCR_ELx_LEN_WIDTH, 0), /* LEN */
592 * Common ftr bits for a 32bit register with all hidden, strict
593 * attributes, with 4bit feature fields and a default safe value of
594 * 0. Covers the following 32bit registers:
595 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
597 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
598 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
599 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
600 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
601 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
602 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
603 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
604 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
605 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
609 /* Table for a single 32bit feature value */
610 static const struct arm64_ftr_bits ftr_single32[] = {
611 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
615 static const struct arm64_ftr_bits ftr_raz[] = {
619 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \
621 .reg = &(struct arm64_ftr_reg){ \
624 .ftr_bits = &((table)[0]), \
627 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \
628 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr)
630 #define ARM64_FTR_REG(id, table) \
631 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override)
633 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override;
634 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override;
635 struct arm64_ftr_override __ro_after_init id_aa64isar1_override;
636 struct arm64_ftr_override __ro_after_init id_aa64isar2_override;
638 static const struct __ftr_reg_entry {
640 struct arm64_ftr_reg *reg;
641 } arm64_ftr_regs[] = {
643 /* Op1 = 0, CRn = 0, CRm = 1 */
644 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
645 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1),
646 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
647 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
648 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
649 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
650 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
652 /* Op1 = 0, CRn = 0, CRm = 2 */
653 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0),
654 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
655 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
656 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
657 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4),
658 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
659 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
660 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
662 /* Op1 = 0, CRn = 0, CRm = 3 */
663 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
664 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
665 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
666 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
667 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),
668 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5),
670 /* Op1 = 0, CRn = 0, CRm = 4 */
671 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
672 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1,
673 &id_aa64pfr1_override),
674 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
675 ARM64_FTR_REG(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0),
677 /* Op1 = 0, CRn = 0, CRm = 5 */
678 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
679 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
681 /* Op1 = 0, CRn = 0, CRm = 6 */
682 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
683 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1,
684 &id_aa64isar1_override),
685 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2,
686 &id_aa64isar2_override),
688 /* Op1 = 0, CRn = 0, CRm = 7 */
689 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
690 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1,
691 &id_aa64mmfr1_override),
692 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
694 /* Op1 = 0, CRn = 1, CRm = 2 */
695 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
696 ARM64_FTR_REG(SYS_SMCR_EL1, ftr_smcr),
698 /* Op1 = 1, CRn = 0, CRm = 0 */
699 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid),
701 /* Op1 = 3, CRn = 0, CRm = 0 */
702 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
703 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
705 /* Op1 = 3, CRn = 14, CRm = 0 */
706 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
709 static int search_cmp_ftr_reg(const void *id, const void *regp)
711 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
715 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using
716 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the
717 * ascending order of sys_id, we use binary search to find a matching
720 * returns - Upon success, matching ftr_reg entry for id.
721 * - NULL on failure. It is upto the caller to decide
722 * the impact of a failure.
724 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id)
726 const struct __ftr_reg_entry *ret;
728 ret = bsearch((const void *)(unsigned long)sys_id,
730 ARRAY_SIZE(arm64_ftr_regs),
731 sizeof(arm64_ftr_regs[0]),
739 * get_arm64_ftr_reg - Looks up a feature register entry using
740 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn().
742 * returns - Upon success, matching ftr_reg entry for id.
743 * - NULL on failure but with an WARN_ON().
745 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
747 struct arm64_ftr_reg *reg;
749 reg = get_arm64_ftr_reg_nowarn(sys_id);
752 * Requesting a non-existent register search is an error. Warn
753 * and let the caller handle it.
759 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
762 u64 mask = arm64_ftr_mask(ftrp);
765 reg |= (ftr_val << ftrp->shift) & mask;
769 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
774 switch (ftrp->type) {
776 ret = ftrp->safe_val;
781 case FTR_HIGHER_OR_ZERO_SAFE:
785 case FTR_HIGHER_SAFE:
795 static void __init sort_ftr_regs(void)
799 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) {
800 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg;
801 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits;
805 * Features here must be sorted in descending order with respect
806 * to their shift values and should not overlap with each other.
808 for (; ftr_bits->width != 0; ftr_bits++, j++) {
809 unsigned int width = ftr_reg->ftr_bits[j].width;
810 unsigned int shift = ftr_reg->ftr_bits[j].shift;
811 unsigned int prev_shift;
813 WARN((shift + width) > 64,
814 "%s has invalid feature at shift %d\n",
815 ftr_reg->name, shift);
818 * Skip the first feature. There is nothing to
819 * compare against for now.
824 prev_shift = ftr_reg->ftr_bits[j - 1].shift;
825 WARN((shift + width) > prev_shift,
826 "%s has feature overlap at shift %d\n",
827 ftr_reg->name, shift);
831 * Skip the first register. There is nothing to
832 * compare against for now.
837 * Registers here must be sorted in ascending order with respect
838 * to sys_id for subsequent binary search in get_arm64_ftr_reg()
841 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id);
846 * Initialise the CPU feature register from Boot CPU values.
847 * Also initiliases the strict_mask for the register.
848 * Any bits that are not covered by an arm64_ftr_bits entry are considered
849 * RES0 for the system-wide value, and must strictly match.
851 static void init_cpu_ftr_reg(u32 sys_reg, u64 new)
854 u64 strict_mask = ~0x0ULL;
858 const struct arm64_ftr_bits *ftrp;
859 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
864 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
865 u64 ftr_mask = arm64_ftr_mask(ftrp);
866 s64 ftr_new = arm64_ftr_value(ftrp, new);
867 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val);
869 if ((ftr_mask & reg->override->mask) == ftr_mask) {
870 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new);
873 if (ftr_ovr != tmp) {
874 /* Unsafe, remove the override */
875 reg->override->mask &= ~ftr_mask;
876 reg->override->val &= ~ftr_mask;
878 str = "ignoring override";
879 } else if (ftr_new != tmp) {
880 /* Override was valid */
883 } else if (ftr_ovr == tmp) {
884 /* Override was the safe value */
889 pr_warn("%s[%d:%d]: %s to %llx\n",
891 ftrp->shift + ftrp->width - 1,
892 ftrp->shift, str, tmp);
893 } else if ((ftr_mask & reg->override->val) == ftr_mask) {
894 reg->override->val &= ~ftr_mask;
895 pr_warn("%s[%d:%d]: impossible override, ignored\n",
897 ftrp->shift + ftrp->width - 1,
901 val = arm64_ftr_set_value(ftrp, val, ftr_new);
903 valid_mask |= ftr_mask;
905 strict_mask &= ~ftr_mask;
907 user_mask |= ftr_mask;
909 reg->user_val = arm64_ftr_set_value(ftrp,
917 reg->strict_mask = strict_mask;
918 reg->user_mask = user_mask;
921 extern const struct arm64_cpu_capabilities arm64_errata[];
922 static const struct arm64_cpu_capabilities arm64_features[];
925 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
927 for (; caps->matches; caps++) {
928 if (WARN(caps->capability >= ARM64_NCAPS,
929 "Invalid capability %d\n", caps->capability))
931 if (WARN(cpu_hwcaps_ptrs[caps->capability],
932 "Duplicate entry for capability %d\n",
935 cpu_hwcaps_ptrs[caps->capability] = caps;
939 static void __init init_cpu_hwcaps_indirect_list(void)
941 init_cpu_hwcaps_indirect_list_from_array(arm64_features);
942 init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
945 static void __init setup_boot_cpu_capabilities(void);
947 static void init_32bit_cpu_features(struct cpuinfo_32bit *info)
949 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
950 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1);
951 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
952 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
953 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
954 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
955 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
956 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
957 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6);
958 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
959 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
960 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
961 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
962 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4);
963 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5);
964 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
965 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
966 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2);
967 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
968 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
969 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
972 void __init init_cpu_features(struct cpuinfo_arm64 *info)
974 /* Before we start using the tables, make sure it is sorted */
977 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
978 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
979 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
980 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
981 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
982 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
983 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
984 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2);
985 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
986 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
987 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
988 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
989 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
990 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
991 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0);
993 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
994 init_32bit_cpu_features(&info->aarch32);
996 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
997 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
998 vec_init_vq_map(ARM64_VEC_SVE);
1001 if (id_aa64pfr1_sme(info->reg_id_aa64pfr1)) {
1002 init_cpu_ftr_reg(SYS_SMCR_EL1, info->reg_smcr);
1003 if (IS_ENABLED(CONFIG_ARM64_SME))
1004 vec_init_vq_map(ARM64_VEC_SME);
1007 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
1008 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid);
1011 * Initialize the indirect array of CPU hwcaps capabilities pointers
1012 * before we handle the boot CPU below.
1014 init_cpu_hwcaps_indirect_list();
1017 * Detect and enable early CPU capabilities based on the boot CPU,
1018 * after we have initialised the CPU feature infrastructure.
1020 setup_boot_cpu_capabilities();
1023 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
1025 const struct arm64_ftr_bits *ftrp;
1027 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
1028 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
1029 s64 ftr_new = arm64_ftr_value(ftrp, new);
1031 if (ftr_cur == ftr_new)
1033 /* Find a safe value */
1034 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
1035 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
1040 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
1042 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
1047 update_cpu_ftr_reg(regp, val);
1048 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
1050 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
1051 regp->name, boot, cpu, val);
1055 static void relax_cpu_ftr_reg(u32 sys_id, int field)
1057 const struct arm64_ftr_bits *ftrp;
1058 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
1063 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) {
1064 if (ftrp->shift == field) {
1065 regp->strict_mask &= ~arm64_ftr_mask(ftrp);
1071 WARN_ON(!ftrp->width);
1074 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info,
1075 struct cpuinfo_arm64 *boot)
1077 static bool boot_cpu_32bit_regs_overridden = false;
1079 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden)
1082 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0))
1085 boot->aarch32 = info->aarch32;
1086 init_32bit_cpu_features(&boot->aarch32);
1087 boot_cpu_32bit_regs_overridden = true;
1090 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info,
1091 struct cpuinfo_32bit *boot)
1094 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1097 * If we don't have AArch32 at EL1, then relax the strictness of
1098 * EL1-dependent register fields to avoid spurious sanity check fails.
1100 if (!id_aa64pfr0_32bit_el1(pfr0)) {
1101 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT);
1102 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT);
1103 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT);
1104 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT);
1105 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT);
1106 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT);
1109 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
1110 info->reg_id_dfr0, boot->reg_id_dfr0);
1111 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu,
1112 info->reg_id_dfr1, boot->reg_id_dfr1);
1113 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
1114 info->reg_id_isar0, boot->reg_id_isar0);
1115 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
1116 info->reg_id_isar1, boot->reg_id_isar1);
1117 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
1118 info->reg_id_isar2, boot->reg_id_isar2);
1119 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
1120 info->reg_id_isar3, boot->reg_id_isar3);
1121 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
1122 info->reg_id_isar4, boot->reg_id_isar4);
1123 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
1124 info->reg_id_isar5, boot->reg_id_isar5);
1125 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu,
1126 info->reg_id_isar6, boot->reg_id_isar6);
1129 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
1130 * ACTLR formats could differ across CPUs and therefore would have to
1131 * be trapped for virtualization anyway.
1133 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
1134 info->reg_id_mmfr0, boot->reg_id_mmfr0);
1135 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
1136 info->reg_id_mmfr1, boot->reg_id_mmfr1);
1137 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
1138 info->reg_id_mmfr2, boot->reg_id_mmfr2);
1139 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
1140 info->reg_id_mmfr3, boot->reg_id_mmfr3);
1141 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu,
1142 info->reg_id_mmfr4, boot->reg_id_mmfr4);
1143 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu,
1144 info->reg_id_mmfr5, boot->reg_id_mmfr5);
1145 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
1146 info->reg_id_pfr0, boot->reg_id_pfr0);
1147 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
1148 info->reg_id_pfr1, boot->reg_id_pfr1);
1149 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu,
1150 info->reg_id_pfr2, boot->reg_id_pfr2);
1151 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
1152 info->reg_mvfr0, boot->reg_mvfr0);
1153 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
1154 info->reg_mvfr1, boot->reg_mvfr1);
1155 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
1156 info->reg_mvfr2, boot->reg_mvfr2);
1162 * Update system wide CPU feature registers with the values from a
1163 * non-boot CPU. Also performs SANITY checks to make sure that there
1164 * aren't any insane variations from that of the boot CPU.
1166 void update_cpu_features(int cpu,
1167 struct cpuinfo_arm64 *info,
1168 struct cpuinfo_arm64 *boot)
1173 * The kernel can handle differing I-cache policies, but otherwise
1174 * caches should look identical. Userspace JITs will make use of
1177 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
1178 info->reg_ctr, boot->reg_ctr);
1181 * Userspace may perform DC ZVA instructions. Mismatched block sizes
1182 * could result in too much or too little memory being zeroed if a
1183 * process is preempted and migrated between CPUs.
1185 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
1186 info->reg_dczid, boot->reg_dczid);
1188 /* If different, timekeeping will be broken (especially with KVM) */
1189 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
1190 info->reg_cntfrq, boot->reg_cntfrq);
1193 * The kernel uses self-hosted debug features and expects CPUs to
1194 * support identical debug features. We presently need CTX_CMPs, WRPs,
1195 * and BRPs to be identical.
1196 * ID_AA64DFR1 is currently RES0.
1198 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
1199 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
1200 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
1201 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
1203 * Even in big.LITTLE, processors should be identical instruction-set
1206 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
1207 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
1208 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
1209 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
1210 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu,
1211 info->reg_id_aa64isar2, boot->reg_id_aa64isar2);
1214 * Differing PARange support is fine as long as all peripherals and
1215 * memory are mapped within the minimum PARange of all CPUs.
1216 * Linux should not care about secure memory.
1218 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
1219 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
1220 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
1221 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
1222 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
1223 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
1225 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
1226 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
1227 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
1228 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
1230 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
1231 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
1233 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu,
1234 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0);
1236 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
1237 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
1238 info->reg_zcr, boot->reg_zcr);
1240 /* Probe vector lengths, unless we already gave up on SVE */
1241 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
1242 !system_capabilities_finalized())
1243 vec_update_vq_map(ARM64_VEC_SVE);
1246 if (id_aa64pfr1_sme(info->reg_id_aa64pfr1)) {
1247 taint |= check_update_ftr_reg(SYS_SMCR_EL1, cpu,
1248 info->reg_smcr, boot->reg_smcr);
1250 /* Probe vector lengths, unless we already gave up on SME */
1251 if (id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1)) &&
1252 !system_capabilities_finalized())
1253 vec_update_vq_map(ARM64_VEC_SME);
1257 * The kernel uses the LDGM/STGM instructions and the number of tags
1258 * they read/write depends on the GMID_EL1.BS field. Check that the
1259 * value is the same on all CPUs.
1261 if (IS_ENABLED(CONFIG_ARM64_MTE) &&
1262 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) {
1263 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu,
1264 info->reg_gmid, boot->reg_gmid);
1268 * If we don't have AArch32 at all then skip the checks entirely
1269 * as the register values may be UNKNOWN and we're not going to be
1270 * using them for anything.
1272 * This relies on a sanitised view of the AArch64 ID registers
1273 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last.
1275 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
1276 lazy_init_32bit_cpu_features(info, boot);
1277 taint |= update_32bit_cpu_features(cpu, &info->aarch32,
1282 * Mismatched CPU features are a recipe for disaster. Don't even
1283 * pretend to support them.
1286 pr_warn_once("Unsupported CPU feature variation detected.\n");
1287 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1291 u64 read_sanitised_ftr_reg(u32 id)
1293 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
1297 return regp->sys_val;
1299 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg);
1301 #define read_sysreg_case(r) \
1302 case r: val = read_sysreg_s(r); break;
1305 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
1306 * Read the system register on the current CPU
1308 u64 __read_sysreg_by_encoding(u32 sys_id)
1310 struct arm64_ftr_reg *regp;
1314 read_sysreg_case(SYS_ID_PFR0_EL1);
1315 read_sysreg_case(SYS_ID_PFR1_EL1);
1316 read_sysreg_case(SYS_ID_PFR2_EL1);
1317 read_sysreg_case(SYS_ID_DFR0_EL1);
1318 read_sysreg_case(SYS_ID_DFR1_EL1);
1319 read_sysreg_case(SYS_ID_MMFR0_EL1);
1320 read_sysreg_case(SYS_ID_MMFR1_EL1);
1321 read_sysreg_case(SYS_ID_MMFR2_EL1);
1322 read_sysreg_case(SYS_ID_MMFR3_EL1);
1323 read_sysreg_case(SYS_ID_MMFR4_EL1);
1324 read_sysreg_case(SYS_ID_MMFR5_EL1);
1325 read_sysreg_case(SYS_ID_ISAR0_EL1);
1326 read_sysreg_case(SYS_ID_ISAR1_EL1);
1327 read_sysreg_case(SYS_ID_ISAR2_EL1);
1328 read_sysreg_case(SYS_ID_ISAR3_EL1);
1329 read_sysreg_case(SYS_ID_ISAR4_EL1);
1330 read_sysreg_case(SYS_ID_ISAR5_EL1);
1331 read_sysreg_case(SYS_ID_ISAR6_EL1);
1332 read_sysreg_case(SYS_MVFR0_EL1);
1333 read_sysreg_case(SYS_MVFR1_EL1);
1334 read_sysreg_case(SYS_MVFR2_EL1);
1336 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
1337 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
1338 read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
1339 read_sysreg_case(SYS_ID_AA64SMFR0_EL1);
1340 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
1341 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
1342 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
1343 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
1344 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
1345 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
1346 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
1347 read_sysreg_case(SYS_ID_AA64ISAR2_EL1);
1349 read_sysreg_case(SYS_CNTFRQ_EL0);
1350 read_sysreg_case(SYS_CTR_EL0);
1351 read_sysreg_case(SYS_DCZID_EL0);
1358 regp = get_arm64_ftr_reg(sys_id);
1360 val &= ~regp->override->mask;
1361 val |= (regp->override->val & regp->override->mask);
1367 #include <linux/irqchip/arm-gic-v3.h>
1370 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
1372 int val = cpuid_feature_extract_field_width(reg, entry->field_pos,
1376 return val >= entry->min_field_value;
1380 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
1384 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1385 if (scope == SCOPE_SYSTEM)
1386 val = read_sanitised_ftr_reg(entry->sys_reg);
1388 val = __read_sysreg_by_encoding(entry->sys_reg);
1390 return feature_matches(val, entry);
1393 const struct cpumask *system_32bit_el0_cpumask(void)
1395 if (!system_supports_32bit_el0())
1396 return cpu_none_mask;
1398 if (static_branch_unlikely(&arm64_mismatched_32bit_el0))
1399 return cpu_32bit_el0_mask;
1401 return cpu_possible_mask;
1404 static int __init parse_32bit_el0_param(char *str)
1406 allow_mismatched_32bit_el0 = true;
1409 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param);
1411 static ssize_t aarch32_el0_show(struct device *dev,
1412 struct device_attribute *attr, char *buf)
1414 const struct cpumask *mask = system_32bit_el0_cpumask();
1416 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask));
1418 static const DEVICE_ATTR_RO(aarch32_el0);
1420 static int __init aarch32_el0_sysfs_init(void)
1422 if (!allow_mismatched_32bit_el0)
1425 return device_create_file(cpu_subsys.dev_root, &dev_attr_aarch32_el0);
1427 device_initcall(aarch32_el0_sysfs_init);
1429 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope)
1431 if (!has_cpuid_feature(entry, scope))
1432 return allow_mismatched_32bit_el0;
1434 if (scope == SCOPE_SYSTEM)
1435 pr_info("detected: 32-bit EL0 Support\n");
1440 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
1444 if (!has_cpuid_feature(entry, scope))
1447 has_sre = gic_enable_sre();
1449 pr_warn_once("%s present but disabled by higher exception level\n",
1455 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
1457 u32 midr = read_cpuid_id();
1459 /* Cavium ThunderX pass 1.x and 2.x */
1460 return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
1461 MIDR_CPU_VAR_REV(0, 0),
1462 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
1465 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
1467 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1469 return cpuid_feature_extract_signed_field(pfr0,
1470 ID_AA64PFR0_FP_SHIFT) < 0;
1473 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
1478 if (scope == SCOPE_SYSTEM)
1479 ctr = arm64_ftr_reg_ctrel0.sys_val;
1481 ctr = read_cpuid_effective_cachetype();
1483 return ctr & BIT(CTR_IDC_SHIFT);
1486 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
1489 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
1490 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
1491 * to the CTR_EL0 on this CPU and emulate it with the real/safe
1494 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
1495 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
1498 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
1503 if (scope == SCOPE_SYSTEM)
1504 ctr = arm64_ftr_reg_ctrel0.sys_val;
1506 ctr = read_cpuid_cachetype();
1508 return ctr & BIT(CTR_DIC_SHIFT);
1511 static bool __maybe_unused
1512 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
1515 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
1516 * may share TLB entries with a CPU stuck in the crashed
1519 if (is_kdump_kernel())
1522 if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP))
1525 return has_cpuid_feature(entry, scope);
1529 * This check is triggered during the early boot before the cpufeature
1530 * is initialised. Checking the status on the local CPU allows the boot
1531 * CPU to detect the need for non-global mappings and thus avoiding a
1532 * pagetable re-write after all the CPUs are booted. This check will be
1533 * anyway run on individual CPUs, allowing us to get the consistent
1534 * state once the SMP CPUs are up and thus make the switch to non-global
1535 * mappings if required.
1537 bool kaslr_requires_kpti(void)
1539 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE))
1543 * E0PD does a similar job to KPTI so can be used instead
1546 if (IS_ENABLED(CONFIG_ARM64_E0PD)) {
1547 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1);
1548 if (cpuid_feature_extract_unsigned_field(mmfr2,
1549 ID_AA64MMFR2_E0PD_SHIFT))
1554 * Systems affected by Cavium erratum 24756 are incompatible
1557 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) {
1558 extern const struct midr_range cavium_erratum_27456_cpus[];
1560 if (is_midr_in_range_list(read_cpuid_id(),
1561 cavium_erratum_27456_cpus))
1565 return kaslr_offset() > 0;
1568 static bool __meltdown_safe = true;
1569 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
1571 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
1574 /* List of CPUs that are not vulnerable and don't need KPTI */
1575 static const struct midr_range kpti_safe_list[] = {
1576 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
1577 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
1578 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
1579 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
1580 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
1581 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1582 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
1583 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
1584 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
1585 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
1586 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
1587 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD),
1588 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER),
1589 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
1590 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
1593 char const *str = "kpti command line option";
1596 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
1598 /* Defer to CPU feature registers */
1599 if (has_cpuid_feature(entry, scope))
1600 meltdown_safe = true;
1603 __meltdown_safe = false;
1606 * For reasons that aren't entirely clear, enabling KPTI on Cavium
1607 * ThunderX leads to apparent I-cache corruption of kernel text, which
1608 * ends as well as you might imagine. Don't even try. We cannot rely
1609 * on the cpus_have_*cap() helpers here to detect the CPU erratum
1610 * because cpucap detection order may change. However, since we know
1611 * affected CPUs are always in a homogeneous configuration, it is
1612 * safe to rely on this_cpu_has_cap() here.
1614 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1615 str = "ARM64_WORKAROUND_CAVIUM_27456";
1619 /* Useful for KASLR robustness */
1620 if (kaslr_requires_kpti()) {
1621 if (!__kpti_forced) {
1627 if (cpu_mitigations_off() && !__kpti_forced) {
1628 str = "mitigations=off";
1632 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1633 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1638 if (__kpti_forced) {
1639 pr_info_once("kernel page table isolation forced %s by %s\n",
1640 __kpti_forced > 0 ? "ON" : "OFF", str);
1641 return __kpti_forced > 0;
1644 return !meltdown_safe;
1647 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1649 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1651 typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1652 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1653 kpti_remap_fn *remap_fn;
1655 int cpu = smp_processor_id();
1657 if (__this_cpu_read(this_cpu_vector) == vectors) {
1658 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI);
1660 __this_cpu_write(this_cpu_vector, v);
1664 * We don't need to rewrite the page-tables if either we've done
1665 * it already or we have KASLR enabled and therefore have not
1666 * created any global mappings at all.
1668 if (arm64_use_ng_mappings)
1671 remap_fn = (void *)__pa_symbol(function_nocfi(idmap_kpti_install_ng_mappings));
1673 cpu_install_idmap();
1674 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1675 cpu_uninstall_idmap();
1678 arm64_use_ng_mappings = true;
1682 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1685 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1687 static int __init parse_kpti(char *str)
1690 int ret = strtobool(str, &enabled);
1695 __kpti_forced = enabled ? 1 : -1;
1698 early_param("kpti", parse_kpti);
1700 #ifdef CONFIG_ARM64_HW_AFDBM
1701 static inline void __cpu_enable_hw_dbm(void)
1703 u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1705 write_sysreg(tcr, tcr_el1);
1707 local_flush_tlb_all();
1710 static bool cpu_has_broken_dbm(void)
1712 /* List of CPUs which have broken DBM support. */
1713 static const struct midr_range cpus[] = {
1714 #ifdef CONFIG_ARM64_ERRATUM_1024718
1715 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1716 /* Kryo4xx Silver (rdpe => r1p0) */
1717 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
1719 #ifdef CONFIG_ARM64_ERRATUM_2051678
1720 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2),
1725 return is_midr_in_range_list(read_cpuid_id(), cpus);
1728 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1730 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1731 !cpu_has_broken_dbm();
1734 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1736 if (cpu_can_use_dbm(cap))
1737 __cpu_enable_hw_dbm();
1740 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1743 static bool detected = false;
1745 * DBM is a non-conflicting feature. i.e, the kernel can safely
1746 * run a mix of CPUs with and without the feature. So, we
1747 * unconditionally enable the capability to allow any late CPU
1748 * to use the feature. We only enable the control bits on the
1749 * CPU, if it actually supports.
1751 * We have to make sure we print the "feature" detection only
1752 * when at least one CPU actually uses it. So check if this CPU
1753 * can actually use it and print the message exactly once.
1755 * This is safe as all CPUs (including secondary CPUs - due to the
1756 * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1757 * goes through the "matches" check exactly once. Also if a CPU
1758 * matches the criteria, it is guaranteed that the CPU will turn
1759 * the DBM on, as the capability is unconditionally enabled.
1761 if (!detected && cpu_can_use_dbm(cap)) {
1763 pr_info("detected: Hardware dirty bit management\n");
1771 #ifdef CONFIG_ARM64_AMU_EXTN
1774 * The "amu_cpus" cpumask only signals that the CPU implementation for the
1775 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide
1776 * information regarding all the events that it supports. When a CPU bit is
1777 * set in the cpumask, the user of this feature can only rely on the presence
1778 * of the 4 fixed counters for that CPU. But this does not guarantee that the
1779 * counters are enabled or access to these counters is enabled by code
1780 * executed at higher exception levels (firmware).
1782 static struct cpumask amu_cpus __read_mostly;
1784 bool cpu_has_amu_feat(int cpu)
1786 return cpumask_test_cpu(cpu, &amu_cpus);
1789 int get_cpu_with_amu_feat(void)
1791 return cpumask_any(&amu_cpus);
1794 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
1796 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) {
1797 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n",
1798 smp_processor_id());
1799 cpumask_set_cpu(smp_processor_id(), &amu_cpus);
1800 update_freq_counters_refs();
1804 static bool has_amu(const struct arm64_cpu_capabilities *cap,
1808 * The AMU extension is a non-conflicting feature: the kernel can
1809 * safely run a mix of CPUs with and without support for the
1810 * activity monitors extension. Therefore, unconditionally enable
1811 * the capability to allow any late CPU to use the feature.
1813 * With this feature unconditionally enabled, the cpu_enable
1814 * function will be called for all CPUs that match the criteria,
1815 * including secondary and hotplugged, marking this feature as
1816 * present on that respective CPU. The enable function will also
1817 * print a detection message.
1823 int get_cpu_with_amu_feat(void)
1829 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1831 return is_kernel_in_hyp_mode();
1834 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1837 * Copy register values that aren't redirected by hardware.
1839 * Before code patching, we only set tpidr_el1, all CPUs need to copy
1840 * this value to tpidr_el2 before we patch the code. Once we've done
1841 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1844 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1845 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1848 #ifdef CONFIG_ARM64_PAN
1849 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1852 * We modify PSTATE. This won't work from irq context as the PSTATE
1853 * is discarded once we return from the exception.
1855 WARN_ON_ONCE(in_interrupt());
1857 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1860 #endif /* CONFIG_ARM64_PAN */
1862 #ifdef CONFIG_ARM64_RAS_EXTN
1863 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1865 /* Firmware may have left a deferred SError in this register. */
1866 write_sysreg_s(0, SYS_DISR_EL1);
1868 #endif /* CONFIG_ARM64_RAS_EXTN */
1870 #ifdef CONFIG_ARM64_PTR_AUTH
1871 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope)
1873 int boot_val, sec_val;
1875 /* We don't expect to be called with SCOPE_SYSTEM */
1876 WARN_ON(scope == SCOPE_SYSTEM);
1878 * The ptr-auth feature levels are not intercompatible with lower
1879 * levels. Hence we must match ptr-auth feature level of the secondary
1880 * CPUs with that of the boot CPU. The level of boot cpu is fetched
1881 * from the sanitised register whereas direct register read is done for
1882 * the secondary CPUs.
1883 * The sanitised feature state is guaranteed to match that of the
1884 * boot CPU as a mismatched secondary CPU is parked before it gets
1885 * a chance to update the state, with the capability.
1887 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg),
1888 entry->field_pos, entry->sign);
1889 if (scope & SCOPE_BOOT_CPU)
1890 return boot_val >= entry->min_field_value;
1891 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */
1892 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg),
1893 entry->field_pos, entry->sign);
1894 return (sec_val >= entry->min_field_value) && (sec_val == boot_val);
1897 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry,
1900 bool api = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope);
1901 bool apa = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope);
1902 bool apa3 = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope);
1904 return apa || apa3 || api;
1907 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,
1910 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF);
1911 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5);
1912 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3);
1914 return gpa || gpa3 || gpi;
1916 #endif /* CONFIG_ARM64_PTR_AUTH */
1918 #ifdef CONFIG_ARM64_E0PD
1919 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
1921 if (this_cpu_has_cap(ARM64_HAS_E0PD))
1922 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
1924 #endif /* CONFIG_ARM64_E0PD */
1926 #ifdef CONFIG_ARM64_PSEUDO_NMI
1927 static bool enable_pseudo_nmi;
1929 static int __init early_enable_pseudo_nmi(char *p)
1931 return strtobool(p, &enable_pseudo_nmi);
1933 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1935 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1938 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
1942 #ifdef CONFIG_ARM64_BTI
1943 static void bti_enable(const struct arm64_cpu_capabilities *__unused)
1946 * Use of X16/X17 for tail-calls and trampolines that jump to
1947 * function entry points using BR is a requirement for
1948 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI.
1949 * So, be strict and forbid other BRs using other registers to
1950 * jump onto a PACIxSP instruction:
1952 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1);
1955 #endif /* CONFIG_ARM64_BTI */
1957 #ifdef CONFIG_ARM64_MTE
1958 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap)
1960 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0);
1964 * Clear the tags in the zero page. This needs to be done via the
1965 * linear map which has the Tagged attribute.
1967 if (!test_and_set_bit(PG_mte_tagged, &ZERO_PAGE(0)->flags))
1968 mte_clear_page_tags(lm_alias(empty_zero_page));
1970 kasan_init_hw_tags_cpu();
1972 #endif /* CONFIG_ARM64_MTE */
1975 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused)
1977 return kvm_get_mode() == KVM_MODE_PROTECTED;
1979 #endif /* CONFIG_KVM */
1981 /* Internal helper functions to match cpu capability type */
1983 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
1985 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);
1989 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap)
1991 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);
1995 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap)
1997 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT);
2000 static const struct arm64_cpu_capabilities arm64_features[] = {
2002 .desc = "GIC system register CPU interface",
2003 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
2004 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2005 .matches = has_useable_gicv3_cpuif,
2006 .sys_reg = SYS_ID_AA64PFR0_EL1,
2007 .field_pos = ID_AA64PFR0_GIC_SHIFT,
2009 .sign = FTR_UNSIGNED,
2010 .min_field_value = 1,
2013 .desc = "Enhanced Counter Virtualization",
2014 .capability = ARM64_HAS_ECV,
2015 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2016 .matches = has_cpuid_feature,
2017 .sys_reg = SYS_ID_AA64MMFR0_EL1,
2018 .field_pos = ID_AA64MMFR0_ECV_SHIFT,
2020 .sign = FTR_UNSIGNED,
2021 .min_field_value = 1,
2023 #ifdef CONFIG_ARM64_PAN
2025 .desc = "Privileged Access Never",
2026 .capability = ARM64_HAS_PAN,
2027 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2028 .matches = has_cpuid_feature,
2029 .sys_reg = SYS_ID_AA64MMFR1_EL1,
2030 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
2032 .sign = FTR_UNSIGNED,
2033 .min_field_value = 1,
2034 .cpu_enable = cpu_enable_pan,
2036 #endif /* CONFIG_ARM64_PAN */
2037 #ifdef CONFIG_ARM64_EPAN
2039 .desc = "Enhanced Privileged Access Never",
2040 .capability = ARM64_HAS_EPAN,
2041 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2042 .matches = has_cpuid_feature,
2043 .sys_reg = SYS_ID_AA64MMFR1_EL1,
2044 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
2046 .sign = FTR_UNSIGNED,
2047 .min_field_value = 3,
2049 #endif /* CONFIG_ARM64_EPAN */
2050 #ifdef CONFIG_ARM64_LSE_ATOMICS
2052 .desc = "LSE atomic instructions",
2053 .capability = ARM64_HAS_LSE_ATOMICS,
2054 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2055 .matches = has_cpuid_feature,
2056 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2057 .field_pos = ID_AA64ISAR0_EL1_ATOMIC_SHIFT,
2059 .sign = FTR_UNSIGNED,
2060 .min_field_value = 2,
2062 #endif /* CONFIG_ARM64_LSE_ATOMICS */
2064 .desc = "Software prefetching using PRFM",
2065 .capability = ARM64_HAS_NO_HW_PREFETCH,
2066 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2067 .matches = has_no_hw_prefetch,
2070 .desc = "Virtualization Host Extensions",
2071 .capability = ARM64_HAS_VIRT_HOST_EXTN,
2072 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2073 .matches = runs_at_el2,
2074 .cpu_enable = cpu_copy_el2regs,
2077 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE,
2078 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2079 .matches = has_32bit_el0,
2080 .sys_reg = SYS_ID_AA64PFR0_EL1,
2081 .sign = FTR_UNSIGNED,
2082 .field_pos = ID_AA64PFR0_EL0_SHIFT,
2084 .min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT,
2088 .desc = "32-bit EL1 Support",
2089 .capability = ARM64_HAS_32BIT_EL1,
2090 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2091 .matches = has_cpuid_feature,
2092 .sys_reg = SYS_ID_AA64PFR0_EL1,
2093 .sign = FTR_UNSIGNED,
2094 .field_pos = ID_AA64PFR0_EL1_SHIFT,
2096 .min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT,
2099 .desc = "Protected KVM",
2100 .capability = ARM64_KVM_PROTECTED_MODE,
2101 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2102 .matches = is_kvm_protected_mode,
2106 .desc = "Kernel page table isolation (KPTI)",
2107 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
2108 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
2110 * The ID feature fields below are used to indicate that
2111 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
2114 .sys_reg = SYS_ID_AA64PFR0_EL1,
2115 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
2117 .min_field_value = 1,
2118 .matches = unmap_kernel_at_el0,
2119 .cpu_enable = kpti_install_ng_mappings,
2122 /* FP/SIMD is not implemented */
2123 .capability = ARM64_HAS_NO_FPSIMD,
2124 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
2125 .min_field_value = 0,
2126 .matches = has_no_fpsimd,
2128 #ifdef CONFIG_ARM64_PMEM
2130 .desc = "Data cache clean to Point of Persistence",
2131 .capability = ARM64_HAS_DCPOP,
2132 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2133 .matches = has_cpuid_feature,
2134 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2135 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
2137 .min_field_value = 1,
2140 .desc = "Data cache clean to Point of Deep Persistence",
2141 .capability = ARM64_HAS_DCPODP,
2142 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2143 .matches = has_cpuid_feature,
2144 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2145 .sign = FTR_UNSIGNED,
2146 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
2148 .min_field_value = 2,
2151 #ifdef CONFIG_ARM64_SVE
2153 .desc = "Scalable Vector Extension",
2154 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2155 .capability = ARM64_SVE,
2156 .sys_reg = SYS_ID_AA64PFR0_EL1,
2157 .sign = FTR_UNSIGNED,
2158 .field_pos = ID_AA64PFR0_SVE_SHIFT,
2160 .min_field_value = ID_AA64PFR0_SVE,
2161 .matches = has_cpuid_feature,
2162 .cpu_enable = sve_kernel_enable,
2164 #endif /* CONFIG_ARM64_SVE */
2165 #ifdef CONFIG_ARM64_RAS_EXTN
2167 .desc = "RAS Extension Support",
2168 .capability = ARM64_HAS_RAS_EXTN,
2169 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2170 .matches = has_cpuid_feature,
2171 .sys_reg = SYS_ID_AA64PFR0_EL1,
2172 .sign = FTR_UNSIGNED,
2173 .field_pos = ID_AA64PFR0_RAS_SHIFT,
2175 .min_field_value = ID_AA64PFR0_RAS_V1,
2176 .cpu_enable = cpu_clear_disr,
2178 #endif /* CONFIG_ARM64_RAS_EXTN */
2179 #ifdef CONFIG_ARM64_AMU_EXTN
2182 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y.
2183 * Therefore, don't provide .desc as we don't want the detection
2184 * message to be shown until at least one CPU is detected to
2185 * support the feature.
2187 .capability = ARM64_HAS_AMU_EXTN,
2188 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2190 .sys_reg = SYS_ID_AA64PFR0_EL1,
2191 .sign = FTR_UNSIGNED,
2192 .field_pos = ID_AA64PFR0_AMU_SHIFT,
2194 .min_field_value = ID_AA64PFR0_AMU,
2195 .cpu_enable = cpu_amu_enable,
2197 #endif /* CONFIG_ARM64_AMU_EXTN */
2199 .desc = "Data cache clean to the PoU not required for I/D coherence",
2200 .capability = ARM64_HAS_CACHE_IDC,
2201 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2202 .matches = has_cache_idc,
2203 .cpu_enable = cpu_emulate_effective_ctr,
2206 .desc = "Instruction cache invalidation not required for I/D coherence",
2207 .capability = ARM64_HAS_CACHE_DIC,
2208 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2209 .matches = has_cache_dic,
2212 .desc = "Stage-2 Force Write-Back",
2213 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2214 .capability = ARM64_HAS_STAGE2_FWB,
2215 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2216 .sign = FTR_UNSIGNED,
2217 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
2219 .min_field_value = 1,
2220 .matches = has_cpuid_feature,
2223 .desc = "ARMv8.4 Translation Table Level",
2224 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2225 .capability = ARM64_HAS_ARMv8_4_TTL,
2226 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2227 .sign = FTR_UNSIGNED,
2228 .field_pos = ID_AA64MMFR2_TTL_SHIFT,
2230 .min_field_value = 1,
2231 .matches = has_cpuid_feature,
2234 .desc = "TLB range maintenance instructions",
2235 .capability = ARM64_HAS_TLB_RANGE,
2236 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2237 .matches = has_cpuid_feature,
2238 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2239 .field_pos = ID_AA64ISAR0_EL1_TLB_SHIFT,
2241 .sign = FTR_UNSIGNED,
2242 .min_field_value = ID_AA64ISAR0_EL1_TLB_RANGE,
2244 #ifdef CONFIG_ARM64_HW_AFDBM
2247 * Since we turn this on always, we don't want the user to
2248 * think that the feature is available when it may not be.
2249 * So hide the description.
2251 * .desc = "Hardware pagetable Dirty Bit Management",
2254 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2255 .capability = ARM64_HW_DBM,
2256 .sys_reg = SYS_ID_AA64MMFR1_EL1,
2257 .sign = FTR_UNSIGNED,
2258 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
2260 .min_field_value = 2,
2261 .matches = has_hw_dbm,
2262 .cpu_enable = cpu_enable_hw_dbm,
2266 .desc = "CRC32 instructions",
2267 .capability = ARM64_HAS_CRC32,
2268 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2269 .matches = has_cpuid_feature,
2270 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2271 .field_pos = ID_AA64ISAR0_EL1_CRC32_SHIFT,
2273 .min_field_value = 1,
2276 .desc = "Speculative Store Bypassing Safe (SSBS)",
2277 .capability = ARM64_SSBS,
2278 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2279 .matches = has_cpuid_feature,
2280 .sys_reg = SYS_ID_AA64PFR1_EL1,
2281 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
2283 .sign = FTR_UNSIGNED,
2284 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
2286 #ifdef CONFIG_ARM64_CNP
2288 .desc = "Common not Private translations",
2289 .capability = ARM64_HAS_CNP,
2290 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2291 .matches = has_useable_cnp,
2292 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2293 .sign = FTR_UNSIGNED,
2294 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
2296 .min_field_value = 1,
2297 .cpu_enable = cpu_enable_cnp,
2301 .desc = "Speculation barrier (SB)",
2302 .capability = ARM64_HAS_SB,
2303 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2304 .matches = has_cpuid_feature,
2305 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2306 .field_pos = ID_AA64ISAR1_SB_SHIFT,
2308 .sign = FTR_UNSIGNED,
2309 .min_field_value = 1,
2311 #ifdef CONFIG_ARM64_PTR_AUTH
2313 .desc = "Address authentication (architected QARMA5 algorithm)",
2314 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5,
2315 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2316 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2317 .sign = FTR_UNSIGNED,
2318 .field_pos = ID_AA64ISAR1_APA_SHIFT,
2320 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
2321 .matches = has_address_auth_cpucap,
2324 .desc = "Address authentication (architected QARMA3 algorithm)",
2325 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3,
2326 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2327 .sys_reg = SYS_ID_AA64ISAR2_EL1,
2328 .sign = FTR_UNSIGNED,
2329 .field_pos = ID_AA64ISAR2_APA3_SHIFT,
2331 .min_field_value = ID_AA64ISAR2_APA3_ARCHITECTED,
2332 .matches = has_address_auth_cpucap,
2335 .desc = "Address authentication (IMP DEF algorithm)",
2336 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
2337 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2338 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2339 .sign = FTR_UNSIGNED,
2340 .field_pos = ID_AA64ISAR1_API_SHIFT,
2342 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
2343 .matches = has_address_auth_cpucap,
2346 .capability = ARM64_HAS_ADDRESS_AUTH,
2347 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2348 .matches = has_address_auth_metacap,
2351 .desc = "Generic authentication (architected QARMA5 algorithm)",
2352 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5,
2353 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2354 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2355 .sign = FTR_UNSIGNED,
2356 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
2358 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
2359 .matches = has_cpuid_feature,
2362 .desc = "Generic authentication (architected QARMA3 algorithm)",
2363 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3,
2364 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2365 .sys_reg = SYS_ID_AA64ISAR2_EL1,
2366 .sign = FTR_UNSIGNED,
2367 .field_pos = ID_AA64ISAR2_GPA3_SHIFT,
2369 .min_field_value = ID_AA64ISAR2_GPA3_ARCHITECTED,
2370 .matches = has_cpuid_feature,
2373 .desc = "Generic authentication (IMP DEF algorithm)",
2374 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
2375 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2376 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2377 .sign = FTR_UNSIGNED,
2378 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
2380 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
2381 .matches = has_cpuid_feature,
2384 .capability = ARM64_HAS_GENERIC_AUTH,
2385 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2386 .matches = has_generic_auth,
2388 #endif /* CONFIG_ARM64_PTR_AUTH */
2389 #ifdef CONFIG_ARM64_PSEUDO_NMI
2392 * Depends on having GICv3
2394 .desc = "IRQ priority masking",
2395 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
2396 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2397 .matches = can_use_gic_priorities,
2398 .sys_reg = SYS_ID_AA64PFR0_EL1,
2399 .field_pos = ID_AA64PFR0_GIC_SHIFT,
2401 .sign = FTR_UNSIGNED,
2402 .min_field_value = 1,
2405 #ifdef CONFIG_ARM64_E0PD
2408 .capability = ARM64_HAS_E0PD,
2409 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2410 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2411 .sign = FTR_UNSIGNED,
2413 .field_pos = ID_AA64MMFR2_E0PD_SHIFT,
2414 .matches = has_cpuid_feature,
2415 .min_field_value = 1,
2416 .cpu_enable = cpu_enable_e0pd,
2419 #ifdef CONFIG_ARCH_RANDOM
2421 .desc = "Random Number Generator",
2422 .capability = ARM64_HAS_RNG,
2423 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2424 .matches = has_cpuid_feature,
2425 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2426 .field_pos = ID_AA64ISAR0_EL1_RNDR_SHIFT,
2428 .sign = FTR_UNSIGNED,
2429 .min_field_value = 1,
2432 #ifdef CONFIG_ARM64_BTI
2434 .desc = "Branch Target Identification",
2435 .capability = ARM64_BTI,
2436 #ifdef CONFIG_ARM64_BTI_KERNEL
2437 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2439 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2441 .matches = has_cpuid_feature,
2442 .cpu_enable = bti_enable,
2443 .sys_reg = SYS_ID_AA64PFR1_EL1,
2444 .field_pos = ID_AA64PFR1_BT_SHIFT,
2446 .min_field_value = ID_AA64PFR1_BT_BTI,
2447 .sign = FTR_UNSIGNED,
2450 #ifdef CONFIG_ARM64_MTE
2452 .desc = "Memory Tagging Extension",
2453 .capability = ARM64_MTE,
2454 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2455 .matches = has_cpuid_feature,
2456 .sys_reg = SYS_ID_AA64PFR1_EL1,
2457 .field_pos = ID_AA64PFR1_MTE_SHIFT,
2459 .min_field_value = ID_AA64PFR1_MTE,
2460 .sign = FTR_UNSIGNED,
2461 .cpu_enable = cpu_enable_mte,
2464 .desc = "Asymmetric MTE Tag Check Fault",
2465 .capability = ARM64_MTE_ASYMM,
2466 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2467 .matches = has_cpuid_feature,
2468 .sys_reg = SYS_ID_AA64PFR1_EL1,
2469 .field_pos = ID_AA64PFR1_MTE_SHIFT,
2471 .min_field_value = ID_AA64PFR1_MTE_ASYMM,
2472 .sign = FTR_UNSIGNED,
2474 #endif /* CONFIG_ARM64_MTE */
2476 .desc = "RCpc load-acquire (LDAPR)",
2477 .capability = ARM64_HAS_LDAPR,
2478 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2479 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2480 .sign = FTR_UNSIGNED,
2481 .field_pos = ID_AA64ISAR1_LRCPC_SHIFT,
2483 .matches = has_cpuid_feature,
2484 .min_field_value = 1,
2486 #ifdef CONFIG_ARM64_SME
2488 .desc = "Scalable Matrix Extension",
2489 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2490 .capability = ARM64_SME,
2491 .sys_reg = SYS_ID_AA64PFR1_EL1,
2492 .sign = FTR_UNSIGNED,
2493 .field_pos = ID_AA64PFR1_SME_SHIFT,
2495 .min_field_value = ID_AA64PFR1_SME,
2496 .matches = has_cpuid_feature,
2497 .cpu_enable = sme_kernel_enable,
2499 /* FA64 should be sorted after the base SME capability */
2502 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2503 .capability = ARM64_SME_FA64,
2504 .sys_reg = SYS_ID_AA64SMFR0_EL1,
2505 .sign = FTR_UNSIGNED,
2506 .field_pos = ID_AA64SMFR0_FA64_SHIFT,
2508 .min_field_value = ID_AA64SMFR0_FA64,
2509 .matches = has_cpuid_feature,
2510 .cpu_enable = fa64_kernel_enable,
2512 #endif /* CONFIG_ARM64_SME */
2514 .desc = "WFx with timeout",
2515 .capability = ARM64_HAS_WFXT,
2516 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2517 .sys_reg = SYS_ID_AA64ISAR2_EL1,
2518 .sign = FTR_UNSIGNED,
2519 .field_pos = ID_AA64ISAR2_WFXT_SHIFT,
2521 .matches = has_cpuid_feature,
2522 .min_field_value = ID_AA64ISAR2_WFXT_SUPPORTED,
2527 #define HWCAP_CPUID_MATCH(reg, field, width, s, min_value) \
2528 .matches = has_cpuid_feature, \
2530 .field_pos = field, \
2531 .field_width = width, \
2533 .min_field_value = min_value,
2535 #define __HWCAP_CAP(name, cap_type, cap) \
2537 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
2538 .hwcap_type = cap_type, \
2541 #define HWCAP_CAP(reg, field, width, s, min_value, cap_type, cap) \
2543 __HWCAP_CAP(#cap, cap_type, cap) \
2544 HWCAP_CPUID_MATCH(reg, field, width, s, min_value) \
2547 #define HWCAP_MULTI_CAP(list, cap_type, cap) \
2549 __HWCAP_CAP(#cap, cap_type, cap) \
2550 .matches = cpucap_multi_entry_cap_matches, \
2551 .match_list = list, \
2554 #define HWCAP_CAP_MATCH(match, cap_type, cap) \
2556 __HWCAP_CAP(#cap, cap_type, cap) \
2560 #ifdef CONFIG_ARM64_PTR_AUTH
2561 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
2563 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
2565 ID_AA64ISAR1_APA_ARCHITECTED)
2568 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_APA3_SHIFT,
2569 4, FTR_UNSIGNED, ID_AA64ISAR2_APA3_ARCHITECTED)
2572 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
2573 4, FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
2578 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
2580 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
2581 4, FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
2584 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_GPA3_SHIFT,
2585 4, FTR_UNSIGNED, ID_AA64ISAR2_GPA3_ARCHITECTED)
2588 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
2589 4, FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
2595 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
2596 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
2597 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
2598 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
2599 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
2600 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
2601 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
2602 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
2603 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
2604 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
2605 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
2606 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
2607 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_DP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
2608 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
2609 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_TS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
2610 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_TS_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
2611 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG),
2612 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
2613 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
2614 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
2615 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
2616 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
2617 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
2618 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
2619 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
2620 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
2621 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
2622 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
2623 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
2624 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
2625 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16),
2626 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH),
2627 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM),
2628 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
2629 #ifdef CONFIG_ARM64_SVE
2630 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
2631 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
2632 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
2633 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
2634 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
2635 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
2636 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
2637 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
2638 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
2639 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
2640 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
2642 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
2643 #ifdef CONFIG_ARM64_BTI
2644 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_BT_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI),
2646 #ifdef CONFIG_ARM64_PTR_AUTH
2647 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
2648 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
2650 #ifdef CONFIG_ARM64_MTE
2651 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE),
2652 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_MTE_ASYMM, CAP_HWCAP, KERNEL_HWCAP_MTE3),
2653 #endif /* CONFIG_ARM64_MTE */
2654 HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
2655 HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
2656 HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES),
2657 HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_WFXT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_WFXT_SUPPORTED, CAP_HWCAP, KERNEL_HWCAP_WFXT),
2658 #ifdef CONFIG_ARM64_SME
2659 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SME_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SME, CAP_HWCAP, KERNEL_HWCAP_SME),
2660 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_FA64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_FA64, CAP_HWCAP, KERNEL_HWCAP_SME_FA64),
2661 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_I16I64_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_I16I64, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64),
2662 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_F64F64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_F64F64, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64),
2663 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_I8I32_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_I8I32, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32),
2664 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_F16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_F16F32, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32),
2665 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_B16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_B16F32, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32),
2666 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_F32F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_F32F32, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32),
2667 #endif /* CONFIG_ARM64_SME */
2671 #ifdef CONFIG_COMPAT
2672 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
2675 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
2676 * in line with that of arm32 as in vfp_init(). We make sure that the
2677 * check is future proof, by making sure value is non-zero.
2681 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
2682 if (scope == SCOPE_SYSTEM)
2683 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
2685 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
2687 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
2688 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
2689 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
2693 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
2694 #ifdef CONFIG_COMPAT
2695 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
2696 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
2697 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
2698 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
2699 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
2700 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
2701 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
2702 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
2703 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
2704 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
2709 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2711 switch (cap->hwcap_type) {
2713 cpu_set_feature(cap->hwcap);
2715 #ifdef CONFIG_COMPAT
2716 case CAP_COMPAT_HWCAP:
2717 compat_elf_hwcap |= (u32)cap->hwcap;
2719 case CAP_COMPAT_HWCAP2:
2720 compat_elf_hwcap2 |= (u32)cap->hwcap;
2729 /* Check if we have a particular HWCAP enabled */
2730 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2734 switch (cap->hwcap_type) {
2736 rc = cpu_have_feature(cap->hwcap);
2738 #ifdef CONFIG_COMPAT
2739 case CAP_COMPAT_HWCAP:
2740 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
2742 case CAP_COMPAT_HWCAP2:
2743 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
2754 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
2756 /* We support emulation of accesses to CPU ID feature registers */
2757 cpu_set_named_feature(CPUID);
2758 for (; hwcaps->matches; hwcaps++)
2759 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
2760 cap_set_elf_hwcap(hwcaps);
2763 static void update_cpu_capabilities(u16 scope_mask)
2766 const struct arm64_cpu_capabilities *caps;
2768 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2769 for (i = 0; i < ARM64_NCAPS; i++) {
2770 caps = cpu_hwcaps_ptrs[i];
2771 if (!caps || !(caps->type & scope_mask) ||
2772 cpus_have_cap(caps->capability) ||
2773 !caps->matches(caps, cpucap_default_scope(caps)))
2777 pr_info("detected: %s\n", caps->desc);
2778 cpus_set_cap(caps->capability);
2780 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
2781 set_bit(caps->capability, boot_capabilities);
2786 * Enable all the available capabilities on this CPU. The capabilities
2787 * with BOOT_CPU scope are handled separately and hence skipped here.
2789 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
2792 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
2794 for_each_available_cap(i) {
2795 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
2800 if (!(cap->type & non_boot_scope))
2803 if (cap->cpu_enable)
2804 cap->cpu_enable(cap);
2810 * Run through the enabled capabilities and enable() it on all active
2813 static void __init enable_cpu_capabilities(u16 scope_mask)
2816 const struct arm64_cpu_capabilities *caps;
2819 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2820 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
2822 for (i = 0; i < ARM64_NCAPS; i++) {
2825 caps = cpu_hwcaps_ptrs[i];
2826 if (!caps || !(caps->type & scope_mask))
2828 num = caps->capability;
2829 if (!cpus_have_cap(num))
2832 /* Ensure cpus_have_const_cap(num) works */
2833 static_branch_enable(&cpu_hwcap_keys[num]);
2835 if (boot_scope && caps->cpu_enable)
2837 * Capabilities with SCOPE_BOOT_CPU scope are finalised
2838 * before any secondary CPU boots. Thus, each secondary
2839 * will enable the capability as appropriate via
2840 * check_local_cpu_capabilities(). The only exception is
2841 * the boot CPU, for which the capability must be
2842 * enabled here. This approach avoids costly
2843 * stop_machine() calls for this case.
2845 caps->cpu_enable(caps);
2849 * For all non-boot scope capabilities, use stop_machine()
2850 * as it schedules the work allowing us to modify PSTATE,
2851 * instead of on_each_cpu() which uses an IPI, giving us a
2852 * PSTATE that disappears when we return.
2855 stop_machine(cpu_enable_non_boot_scope_capabilities,
2856 NULL, cpu_online_mask);
2860 * Run through the list of capabilities to check for conflicts.
2861 * If the system has already detected a capability, take necessary
2862 * action on this CPU.
2864 static void verify_local_cpu_caps(u16 scope_mask)
2867 bool cpu_has_cap, system_has_cap;
2868 const struct arm64_cpu_capabilities *caps;
2870 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2872 for (i = 0; i < ARM64_NCAPS; i++) {
2873 caps = cpu_hwcaps_ptrs[i];
2874 if (!caps || !(caps->type & scope_mask))
2877 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
2878 system_has_cap = cpus_have_cap(caps->capability);
2880 if (system_has_cap) {
2882 * Check if the new CPU misses an advertised feature,
2883 * which is not safe to miss.
2885 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
2888 * We have to issue cpu_enable() irrespective of
2889 * whether the CPU has it or not, as it is enabeld
2890 * system wide. It is upto the call back to take
2891 * appropriate action on this CPU.
2893 if (caps->cpu_enable)
2894 caps->cpu_enable(caps);
2897 * Check if the CPU has this capability if it isn't
2898 * safe to have when the system doesn't.
2900 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
2905 if (i < ARM64_NCAPS) {
2906 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
2907 smp_processor_id(), caps->capability,
2908 caps->desc, system_has_cap, cpu_has_cap);
2910 if (cpucap_panic_on_conflict(caps))
2918 * Check for CPU features that are used in early boot
2919 * based on the Boot CPU value.
2921 static void check_early_cpu_features(void)
2923 verify_cpu_asid_bits();
2925 verify_local_cpu_caps(SCOPE_BOOT_CPU);
2929 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
2932 for (; caps->matches; caps++)
2933 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
2934 pr_crit("CPU%d: missing HWCAP: %s\n",
2935 smp_processor_id(), caps->desc);
2940 static void verify_local_elf_hwcaps(void)
2942 __verify_local_elf_hwcaps(arm64_elf_hwcaps);
2944 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1)))
2945 __verify_local_elf_hwcaps(compat_elf_hwcaps);
2948 static void verify_sve_features(void)
2950 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
2951 u64 zcr = read_zcr_features();
2953 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
2954 unsigned int len = zcr & ZCR_ELx_LEN_MASK;
2956 if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SVE)) {
2957 pr_crit("CPU%d: SVE: vector length support mismatch\n",
2958 smp_processor_id());
2962 /* Add checks on other ZCR bits here if necessary */
2965 static void verify_sme_features(void)
2967 u64 safe_smcr = read_sanitised_ftr_reg(SYS_SMCR_EL1);
2968 u64 smcr = read_smcr_features();
2970 unsigned int safe_len = safe_smcr & SMCR_ELx_LEN_MASK;
2971 unsigned int len = smcr & SMCR_ELx_LEN_MASK;
2973 if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SME)) {
2974 pr_crit("CPU%d: SME: vector length support mismatch\n",
2975 smp_processor_id());
2979 /* Add checks on other SMCR bits here if necessary */
2982 static void verify_hyp_capabilities(void)
2984 u64 safe_mmfr1, mmfr0, mmfr1;
2985 int parange, ipa_max;
2986 unsigned int safe_vmid_bits, vmid_bits;
2988 if (!IS_ENABLED(CONFIG_KVM))
2991 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
2992 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
2993 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
2995 /* Verify VMID bits */
2996 safe_vmid_bits = get_vmid_bits(safe_mmfr1);
2997 vmid_bits = get_vmid_bits(mmfr1);
2998 if (vmid_bits < safe_vmid_bits) {
2999 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id());
3003 /* Verify IPA range */
3004 parange = cpuid_feature_extract_unsigned_field(mmfr0,
3005 ID_AA64MMFR0_PARANGE_SHIFT);
3006 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange);
3007 if (ipa_max < get_kvm_ipa_limit()) {
3008 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id());
3014 * Run through the enabled system capabilities and enable() it on this CPU.
3015 * The capabilities were decided based on the available CPUs at the boot time.
3016 * Any new CPU should match the system wide status of the capability. If the
3017 * new CPU doesn't have a capability which the system now has enabled, we
3018 * cannot do anything to fix it up and could cause unexpected failures. So
3021 static void verify_local_cpu_capabilities(void)
3024 * The capabilities with SCOPE_BOOT_CPU are checked from
3025 * check_early_cpu_features(), as they need to be verified
3026 * on all secondary CPUs.
3028 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU);
3029 verify_local_elf_hwcaps();
3031 if (system_supports_sve())
3032 verify_sve_features();
3034 if (system_supports_sme())
3035 verify_sme_features();
3037 if (is_hyp_mode_available())
3038 verify_hyp_capabilities();
3041 void check_local_cpu_capabilities(void)
3044 * All secondary CPUs should conform to the early CPU features
3045 * in use by the kernel based on boot CPU.
3047 check_early_cpu_features();
3050 * If we haven't finalised the system capabilities, this CPU gets
3051 * a chance to update the errata work arounds and local features.
3052 * Otherwise, this CPU should verify that it has all the system
3053 * advertised capabilities.
3055 if (!system_capabilities_finalized())
3056 update_cpu_capabilities(SCOPE_LOCAL_CPU);
3058 verify_local_cpu_capabilities();
3061 static void __init setup_boot_cpu_capabilities(void)
3063 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
3064 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
3065 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
3066 enable_cpu_capabilities(SCOPE_BOOT_CPU);
3069 bool this_cpu_has_cap(unsigned int n)
3071 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
3072 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
3075 return cap->matches(cap, SCOPE_LOCAL_CPU);
3080 EXPORT_SYMBOL_GPL(this_cpu_has_cap);
3083 * This helper function is used in a narrow window when,
3084 * - The system wide safe registers are set with all the SMP CPUs and,
3085 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set.
3086 * In all other cases cpus_have_{const_}cap() should be used.
3088 static bool __maybe_unused __system_matches_cap(unsigned int n)
3090 if (n < ARM64_NCAPS) {
3091 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
3094 return cap->matches(cap, SCOPE_SYSTEM);
3099 void cpu_set_feature(unsigned int num)
3101 WARN_ON(num >= MAX_CPU_FEATURES);
3102 elf_hwcap |= BIT(num);
3104 EXPORT_SYMBOL_GPL(cpu_set_feature);
3106 bool cpu_have_feature(unsigned int num)
3108 WARN_ON(num >= MAX_CPU_FEATURES);
3109 return elf_hwcap & BIT(num);
3111 EXPORT_SYMBOL_GPL(cpu_have_feature);
3113 unsigned long cpu_get_elf_hwcap(void)
3116 * We currently only populate the first 32 bits of AT_HWCAP. Please
3117 * note that for userspace compatibility we guarantee that bits 62
3118 * and 63 will always be returned as 0.
3120 return lower_32_bits(elf_hwcap);
3123 unsigned long cpu_get_elf_hwcap2(void)
3125 return upper_32_bits(elf_hwcap);
3128 static void __init setup_system_capabilities(void)
3131 * We have finalised the system-wide safe feature
3132 * registers, finalise the capabilities that depend
3133 * on it. Also enable all the available capabilities,
3134 * that are not enabled already.
3136 update_cpu_capabilities(SCOPE_SYSTEM);
3137 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
3140 void __init setup_cpu_features(void)
3144 setup_system_capabilities();
3145 setup_elf_hwcaps(arm64_elf_hwcaps);
3147 if (system_supports_32bit_el0())
3148 setup_elf_hwcaps(compat_elf_hwcaps);
3150 if (system_uses_ttbr0_pan())
3151 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
3155 minsigstksz_setup();
3157 /* Advertise that we have computed the system capabilities */
3158 finalize_system_capabilities();
3161 * Check for sane CTR_EL0.CWG value.
3163 cwg = cache_type_cwg();
3165 pr_warn("No Cache Writeback Granule information, assuming %d\n",
3169 static int enable_mismatched_32bit_el0(unsigned int cpu)
3172 * The first 32-bit-capable CPU we detected and so can no longer
3173 * be offlined by userspace. -1 indicates we haven't yet onlined
3174 * a 32-bit-capable CPU.
3176 static int lucky_winner = -1;
3178 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
3179 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0);
3182 cpumask_set_cpu(cpu, cpu_32bit_el0_mask);
3183 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0);
3186 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit)
3189 if (lucky_winner >= 0)
3193 * We've detected a mismatch. We need to keep one of our CPUs with
3194 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting
3195 * every CPU in the system for a 32-bit task.
3197 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask,
3199 get_cpu_device(lucky_winner)->offline_disabled = true;
3200 setup_elf_hwcaps(compat_elf_hwcaps);
3201 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n",
3206 static int __init init_32bit_el0_mask(void)
3208 if (!allow_mismatched_32bit_el0)
3211 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL))
3214 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
3215 "arm64/mismatched_32bit_el0:online",
3216 enable_mismatched_32bit_el0, NULL);
3218 subsys_initcall_sync(init_32bit_el0_mask);
3220 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
3222 cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
3226 * We emulate only the following system register space.
3227 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
3228 * See Table C5-6 System instruction encodings for System register accesses,
3229 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
3231 static inline bool __attribute_const__ is_emulated(u32 id)
3233 return (sys_reg_Op0(id) == 0x3 &&
3234 sys_reg_CRn(id) == 0x0 &&
3235 sys_reg_Op1(id) == 0x0 &&
3236 (sys_reg_CRm(id) == 0 ||
3237 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
3241 * With CRm == 0, reg should be one of :
3242 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
3244 static inline int emulate_id_reg(u32 id, u64 *valp)
3248 *valp = read_cpuid_id();
3251 *valp = SYS_MPIDR_SAFE_VAL;
3253 case SYS_REVIDR_EL1:
3254 /* IMPLEMENTATION DEFINED values are emulated with 0 */
3264 static int emulate_sys_reg(u32 id, u64 *valp)
3266 struct arm64_ftr_reg *regp;
3268 if (!is_emulated(id))
3271 if (sys_reg_CRm(id) == 0)
3272 return emulate_id_reg(id, valp);
3274 regp = get_arm64_ftr_reg_nowarn(id);
3276 *valp = arm64_ftr_reg_user_value(regp);
3279 * The untracked registers are either IMPLEMENTATION DEFINED
3280 * (e.g, ID_AFR0_EL1) or reserved RAZ.
3286 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
3291 rc = emulate_sys_reg(sys_reg, &val);
3293 pt_regs_write_reg(regs, rt, val);
3294 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
3299 static int emulate_mrs(struct pt_regs *regs, u32 insn)
3304 * sys_reg values are defined as used in mrs/msr instruction.
3305 * shift the imm value to get the encoding.
3307 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
3308 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
3309 return do_emulate_mrs(regs, sys_reg, rt);
3312 static struct undef_hook mrs_hook = {
3313 .instr_mask = 0xffff0000,
3314 .instr_val = 0xd5380000,
3315 .pstate_mask = PSR_AA32_MODE_MASK,
3316 .pstate_val = PSR_MODE_EL0t,
3320 static int __init enable_mrs_emulation(void)
3322 register_undef_hook(&mrs_hook);
3326 core_initcall(enable_mrs_emulation);
3328 enum mitigation_state arm64_get_meltdown_state(void)
3330 if (__meltdown_safe)
3331 return SPECTRE_UNAFFECTED;
3333 if (arm64_kernel_unmapped_at_el0())
3334 return SPECTRE_MITIGATED;
3336 return SPECTRE_VULNERABLE;
3339 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
3342 switch (arm64_get_meltdown_state()) {
3343 case SPECTRE_UNAFFECTED:
3344 return sprintf(buf, "Not affected\n");
3346 case SPECTRE_MITIGATED:
3347 return sprintf(buf, "Mitigation: PTI\n");
3350 return sprintf(buf, "Vulnerable\n");