1 // SPDX-License-Identifier: GPL-2.0-only
3 * Contains CPU feature definitions
5 * Copyright (C) 2015 ARM Ltd.
7 * A note for the weary kernel hacker: the code here is confusing and hard to
8 * follow! That's partly because it's solving a nasty problem, but also because
9 * there's a little bit of over-abstraction that tends to obscure what's going
10 * on behind a maze of helper functions and macros.
12 * The basic problem is that hardware folks have started gluing together CPUs
13 * with distinct architectural features; in some cases even creating SoCs where
14 * user-visible instructions are available only on a subset of the available
15 * cores. We try to address this by snapshotting the feature registers of the
16 * boot CPU and comparing these with the feature registers of each secondary
17 * CPU when bringing them up. If there is a mismatch, then we update the
18 * snapshot state to indicate the lowest-common denominator of the feature,
19 * known as the "safe" value. This snapshot state can be queried to view the
20 * "sanitised" value of a feature register.
22 * The sanitised register values are used to decide which capabilities we
23 * have in the system. These may be in the form of traditional "hwcaps"
24 * advertised to userspace or internal "cpucaps" which are used to configure
25 * things like alternative patching and static keys. While a feature mismatch
26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch
27 * may prevent a CPU from being onlined at all.
29 * Some implementation details worth remembering:
31 * - Mismatched features are *always* sanitised to a "safe" value, which
32 * usually indicates that the feature is not supported.
34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
35 * warning when onlining an offending CPU and the kernel will be tainted
36 * with TAINT_CPU_OUT_OF_SPEC.
38 * - Features marked as FTR_VISIBLE have their sanitised value visible to
39 * userspace. FTR_VISIBLE features in registers that are only visible
40 * to EL0 by trapping *must* have a corresponding HWCAP so that late
41 * onlining of CPUs cannot lead to features disappearing at runtime.
43 * - A "feature" is typically a 4-bit register field. A "capability" is the
44 * high-level description derived from the sanitised field value.
46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID
47 * scheme for fields in ID registers") to understand when feature fields
48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly).
50 * - KVM exposes its own view of the feature registers to guest operating
51 * systems regardless of FTR_VISIBLE. This is typically driven from the
52 * sanitised register values to allow virtual CPUs to be migrated between
53 * arbitrary physical CPUs, but some features not present on the host are
54 * also advertised and emulated. Look at sys_reg_descs[] for the gory
57 * - If the arm64_ftr_bits[] for a register has a missing field, then this
58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg().
59 * This is stronger than FTR_HIDDEN and can be used to hide features from
63 #define pr_fmt(fmt) "CPU features: " fmt
65 #include <linux/bsearch.h>
66 #include <linux/cpumask.h>
67 #include <linux/crash_dump.h>
68 #include <linux/sort.h>
69 #include <linux/stop_machine.h>
70 #include <linux/types.h>
72 #include <linux/cpu.h>
73 #include <linux/kasan.h>
75 #include <asm/cpufeature.h>
76 #include <asm/cpu_ops.h>
77 #include <asm/fpsimd.h>
78 #include <asm/kvm_host.h>
79 #include <asm/mmu_context.h>
81 #include <asm/processor.h>
82 #include <asm/sysreg.h>
83 #include <asm/traps.h>
86 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
87 static unsigned long elf_hwcap __read_mostly;
90 #define COMPAT_ELF_HWCAP_DEFAULT \
91 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
92 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
93 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
95 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
96 unsigned int compat_elf_hwcap2 __read_mostly;
99 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
100 EXPORT_SYMBOL(cpu_hwcaps);
101 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
103 /* Need also bit for ARM64_CB_PATCH */
104 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
106 bool arm64_use_ng_mappings = false;
107 EXPORT_SYMBOL(arm64_use_ng_mappings);
110 * Flag to indicate if we have computed the system wide
111 * capabilities based on the boot time active CPUs. This
112 * will be used to determine if a new booting CPU should
113 * go through the verification process to make sure that it
114 * supports the system capabilities, without using a hotplug
115 * notifier. This is also used to decide if we could use
116 * the fast path for checking constant CPU caps.
118 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
119 EXPORT_SYMBOL(arm64_const_caps_ready);
120 static inline void finalize_system_capabilities(void)
122 static_branch_enable(&arm64_const_caps_ready);
125 void dump_cpu_features(void)
127 /* file-wide pr_fmt adds "CPU features: " prefix */
128 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
131 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
132 EXPORT_SYMBOL(cpu_hwcap_keys);
134 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
137 .visible = VISIBLE, \
142 .safe_val = SAFE_VAL, \
145 /* Define a feature with unsigned values */
146 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
147 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
149 /* Define a feature with a signed value */
150 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
151 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
153 #define ARM64_FTR_END \
158 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
160 static bool __system_matches_cap(unsigned int n);
163 * NOTE: Any changes to the visibility of features should be kept in
164 * sync with the documentation of the CPU feature register ABI.
166 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
167 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0),
168 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLB_SHIFT, 4, 0),
169 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
170 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
171 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
172 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
173 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
174 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
175 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
176 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
177 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
178 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
179 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
180 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
184 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
185 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0),
186 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0),
187 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0),
188 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0),
189 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
190 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
191 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
192 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
193 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
194 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
196 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
197 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
198 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
199 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0),
200 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
201 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0),
202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
206 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
207 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
208 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
209 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
210 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0),
211 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0),
212 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0),
213 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
214 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
215 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
216 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
217 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
218 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
219 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
220 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
221 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
222 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
226 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
227 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0),
228 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0),
229 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE),
230 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, ID_AA64PFR1_MTE_NI),
231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
232 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI),
233 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0),
237 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
238 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
239 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0),
240 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
241 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0),
242 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
243 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0),
244 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
245 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
246 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
247 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
248 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
249 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0),
250 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
251 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
252 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
253 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
254 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
255 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
259 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
260 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0),
261 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0),
262 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0),
264 * Page size not being supported at Stage-2 is not fatal. You
265 * just give up KVM if PAGE_SIZE isn't supported there. Go fix
266 * your favourite nesting hypervisor.
268 * There is a small corner case where the hypervisor explicitly
269 * advertises a given granule size at Stage-2 (value 2) on some
270 * vCPUs, and uses the fallback to Stage-1 (value 0) for other
271 * vCPUs. Although this is not forbidden by the architecture, it
272 * indicates that the hypervisor is being silly (or buggy).
274 * We make no effort to cope with this and pretend that if these
275 * fields are inconsistent across vCPUs, then it isn't worth
276 * trying to bring KVM up.
278 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1),
279 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1),
280 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1),
282 * We already refuse to boot CPUs that don't support our configured
283 * page size, so we can only detect mismatches for a page size other
284 * than the one we're currently using. Unfortunately, SoCs like this
285 * exist in the wild so, even though we don't like it, we'll have to go
286 * along with it and treat them as non-strict.
288 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
289 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
292 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
293 /* Linux shouldn't care about secure memory */
294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
296 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
298 * Differing PARange is fine as long as all peripherals and memory are mapped
299 * within the minimum PARange of all CPUs
301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
305 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
306 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0),
307 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0),
308 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0),
309 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0),
310 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
311 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
312 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
313 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
314 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
315 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
319 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
320 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0),
321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EVT_SHIFT, 4, 0),
322 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_BBM_SHIFT, 4, 0),
323 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0),
324 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
325 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IDS_SHIFT, 4, 0),
326 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
327 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_ST_SHIFT, 4, 0),
328 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_NV_SHIFT, 4, 0),
329 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CCIDX_SHIFT, 4, 0),
330 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
331 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
332 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
333 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
334 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
338 static const struct arm64_ftr_bits ftr_ctr[] = {
339 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
340 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
341 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
342 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
343 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
344 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
346 * Linux can handle differing I-cache policies. Userspace JITs will
347 * make use of *minLine.
348 * If we have differing I-cache policies, report it as the weakest - VIPT.
350 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT), /* L1Ip */
351 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
355 static struct arm64_ftr_override __ro_after_init no_override = { };
357 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
358 .name = "SYS_CTR_EL0",
360 .override = &no_override,
363 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
364 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf),
365 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0),
366 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0),
367 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0),
368 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0),
369 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf),
370 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0),
371 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0),
375 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
376 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_DOUBLELOCK_SHIFT, 4, 0),
377 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
378 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
379 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
380 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
382 * We can instantiate multiple PMU instances with different levels
385 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
386 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
390 static const struct arm64_ftr_bits ftr_mvfr2[] = {
391 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0),
392 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0),
396 static const struct arm64_ftr_bits ftr_dczid[] = {
397 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1),
398 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0),
402 static const struct arm64_ftr_bits ftr_id_isar0[] = {
403 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),
404 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),
405 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0),
406 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0),
407 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0),
408 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0),
409 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0),
413 static const struct arm64_ftr_bits ftr_id_isar5[] = {
414 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
415 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
416 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
417 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
418 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
419 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
423 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
424 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0),
425 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0),
426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0),
427 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0),
428 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0),
429 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0),
430 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0),
433 * SpecSEI = 1 indicates that the PE might generate an SError on an
434 * external abort on speculative read. It is safe to assume that an
435 * SError might be generated than it will not be. Hence it has been
436 * classified as FTR_HIGHER_SAFE.
438 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0),
442 static const struct arm64_ftr_bits ftr_id_isar4[] = {
443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0),
444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0),
445 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0),
446 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0),
447 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0),
448 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0),
449 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0),
450 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0),
454 static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
455 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0),
459 static const struct arm64_ftr_bits ftr_id_isar6[] = {
460 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),
461 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),
463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),
465 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0),
466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0),
470 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0),
472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0),
473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0),
474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0),
475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0),
476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0),
480 static const struct arm64_ftr_bits ftr_id_pfr1[] = {
481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0),
482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0),
483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0),
484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0),
485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0),
486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0),
487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0),
488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0),
492 static const struct arm64_ftr_bits ftr_id_pfr2[] = {
493 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0),
494 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0),
498 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
499 /* [31:28] TraceFilt */
500 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_PERFMON_SHIFT, 4, 0xf),
501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0),
502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0),
503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0),
504 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0),
505 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0),
506 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0),
510 static const struct arm64_ftr_bits ftr_id_dfr1[] = {
511 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0),
515 static const struct arm64_ftr_bits ftr_zcr[] = {
516 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
517 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */
522 * Common ftr bits for a 32bit register with all hidden, strict
523 * attributes, with 4bit feature fields and a default safe value of
524 * 0. Covers the following 32bit registers:
525 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
527 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
528 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
529 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
530 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
531 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
532 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
533 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
534 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
535 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
539 /* Table for a single 32bit feature value */
540 static const struct arm64_ftr_bits ftr_single32[] = {
541 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
545 static const struct arm64_ftr_bits ftr_raz[] = {
549 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) { \
551 .reg = &(struct arm64_ftr_reg){ \
554 .ftr_bits = &((table)[0]), \
557 #define ARM64_FTR_REG(id, table) ARM64_FTR_REG_OVERRIDE(id, table, &no_override)
559 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override;
560 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override;
561 struct arm64_ftr_override __ro_after_init id_aa64isar1_override;
563 static const struct __ftr_reg_entry {
565 struct arm64_ftr_reg *reg;
566 } arm64_ftr_regs[] = {
568 /* Op1 = 0, CRn = 0, CRm = 1 */
569 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
570 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1),
571 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
572 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
573 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
574 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
575 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
577 /* Op1 = 0, CRn = 0, CRm = 2 */
578 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0),
579 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
580 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
581 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
582 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4),
583 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
584 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
585 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
587 /* Op1 = 0, CRn = 0, CRm = 3 */
588 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
589 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
590 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
591 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
592 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),
593 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5),
595 /* Op1 = 0, CRn = 0, CRm = 4 */
596 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
597 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1,
598 &id_aa64pfr1_override),
599 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
601 /* Op1 = 0, CRn = 0, CRm = 5 */
602 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
603 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
605 /* Op1 = 0, CRn = 0, CRm = 6 */
606 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
607 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1,
608 &id_aa64isar1_override),
610 /* Op1 = 0, CRn = 0, CRm = 7 */
611 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
612 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1,
613 &id_aa64mmfr1_override),
614 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
616 /* Op1 = 0, CRn = 1, CRm = 2 */
617 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
619 /* Op1 = 3, CRn = 0, CRm = 0 */
620 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
621 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
623 /* Op1 = 3, CRn = 14, CRm = 0 */
624 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
627 static int search_cmp_ftr_reg(const void *id, const void *regp)
629 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
633 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using
634 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the
635 * ascending order of sys_id, we use binary search to find a matching
638 * returns - Upon success, matching ftr_reg entry for id.
639 * - NULL on failure. It is upto the caller to decide
640 * the impact of a failure.
642 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id)
644 const struct __ftr_reg_entry *ret;
646 ret = bsearch((const void *)(unsigned long)sys_id,
648 ARRAY_SIZE(arm64_ftr_regs),
649 sizeof(arm64_ftr_regs[0]),
657 * get_arm64_ftr_reg - Looks up a feature register entry using
658 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn().
660 * returns - Upon success, matching ftr_reg entry for id.
661 * - NULL on failure but with an WARN_ON().
663 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
665 struct arm64_ftr_reg *reg;
667 reg = get_arm64_ftr_reg_nowarn(sys_id);
670 * Requesting a non-existent register search is an error. Warn
671 * and let the caller handle it.
677 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
680 u64 mask = arm64_ftr_mask(ftrp);
683 reg |= (ftr_val << ftrp->shift) & mask;
687 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
692 switch (ftrp->type) {
694 ret = ftrp->safe_val;
697 ret = new < cur ? new : cur;
699 case FTR_HIGHER_OR_ZERO_SAFE:
703 case FTR_HIGHER_SAFE:
704 ret = new > cur ? new : cur;
713 static void __init sort_ftr_regs(void)
717 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) {
718 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg;
719 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits;
723 * Features here must be sorted in descending order with respect
724 * to their shift values and should not overlap with each other.
726 for (; ftr_bits->width != 0; ftr_bits++, j++) {
727 unsigned int width = ftr_reg->ftr_bits[j].width;
728 unsigned int shift = ftr_reg->ftr_bits[j].shift;
729 unsigned int prev_shift;
731 WARN((shift + width) > 64,
732 "%s has invalid feature at shift %d\n",
733 ftr_reg->name, shift);
736 * Skip the first feature. There is nothing to
737 * compare against for now.
742 prev_shift = ftr_reg->ftr_bits[j - 1].shift;
743 WARN((shift + width) > prev_shift,
744 "%s has feature overlap at shift %d\n",
745 ftr_reg->name, shift);
749 * Skip the first register. There is nothing to
750 * compare against for now.
755 * Registers here must be sorted in ascending order with respect
756 * to sys_id for subsequent binary search in get_arm64_ftr_reg()
759 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
764 * Initialise the CPU feature register from Boot CPU values.
765 * Also initiliases the strict_mask for the register.
766 * Any bits that are not covered by an arm64_ftr_bits entry are considered
767 * RES0 for the system-wide value, and must strictly match.
769 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
772 u64 strict_mask = ~0x0ULL;
776 const struct arm64_ftr_bits *ftrp;
777 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
782 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
783 u64 ftr_mask = arm64_ftr_mask(ftrp);
784 s64 ftr_new = arm64_ftr_value(ftrp, new);
785 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val);
787 if ((ftr_mask & reg->override->mask) == ftr_mask) {
788 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new);
791 if (ftr_ovr != tmp) {
792 /* Unsafe, remove the override */
793 reg->override->mask &= ~ftr_mask;
794 reg->override->val &= ~ftr_mask;
796 str = "ignoring override";
797 } else if (ftr_new != tmp) {
798 /* Override was valid */
801 } else if (ftr_ovr == tmp) {
802 /* Override was the safe value */
807 pr_warn("%s[%d:%d]: %s to %llx\n",
809 ftrp->shift + ftrp->width - 1,
810 ftrp->shift, str, tmp);
811 } else if ((ftr_mask & reg->override->val) == ftr_mask) {
812 reg->override->val &= ~ftr_mask;
813 pr_warn("%s[%d:%d]: impossible override, ignored\n",
815 ftrp->shift + ftrp->width - 1,
819 val = arm64_ftr_set_value(ftrp, val, ftr_new);
821 valid_mask |= ftr_mask;
823 strict_mask &= ~ftr_mask;
825 user_mask |= ftr_mask;
827 reg->user_val = arm64_ftr_set_value(ftrp,
835 reg->strict_mask = strict_mask;
836 reg->user_mask = user_mask;
839 extern const struct arm64_cpu_capabilities arm64_errata[];
840 static const struct arm64_cpu_capabilities arm64_features[];
843 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
845 for (; caps->matches; caps++) {
846 if (WARN(caps->capability >= ARM64_NCAPS,
847 "Invalid capability %d\n", caps->capability))
849 if (WARN(cpu_hwcaps_ptrs[caps->capability],
850 "Duplicate entry for capability %d\n",
853 cpu_hwcaps_ptrs[caps->capability] = caps;
857 static void __init init_cpu_hwcaps_indirect_list(void)
859 init_cpu_hwcaps_indirect_list_from_array(arm64_features);
860 init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
863 static void __init setup_boot_cpu_capabilities(void);
865 void __init init_cpu_features(struct cpuinfo_arm64 *info)
867 /* Before we start using the tables, make sure it is sorted */
870 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
871 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
872 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
873 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
874 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
875 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
876 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
877 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
878 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
879 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
880 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
881 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
882 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
884 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
885 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
886 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1);
887 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
888 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
889 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
890 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
891 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
892 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
893 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6);
894 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
895 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
896 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
897 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
898 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4);
899 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5);
900 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
901 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
902 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2);
903 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
904 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
905 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
908 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
909 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
914 * Initialize the indirect array of CPU hwcaps capabilities pointers
915 * before we handle the boot CPU below.
917 init_cpu_hwcaps_indirect_list();
920 * Detect and enable early CPU capabilities based on the boot CPU,
921 * after we have initialised the CPU feature infrastructure.
923 setup_boot_cpu_capabilities();
926 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
928 const struct arm64_ftr_bits *ftrp;
930 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
931 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
932 s64 ftr_new = arm64_ftr_value(ftrp, new);
934 if (ftr_cur == ftr_new)
936 /* Find a safe value */
937 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
938 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
943 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
945 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
950 update_cpu_ftr_reg(regp, val);
951 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
953 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
954 regp->name, boot, cpu, val);
958 static void relax_cpu_ftr_reg(u32 sys_id, int field)
960 const struct arm64_ftr_bits *ftrp;
961 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
966 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) {
967 if (ftrp->shift == field) {
968 regp->strict_mask &= ~arm64_ftr_mask(ftrp);
974 WARN_ON(!ftrp->width);
977 static int update_32bit_cpu_features(int cpu, struct cpuinfo_arm64 *info,
978 struct cpuinfo_arm64 *boot)
981 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
984 * If we don't have AArch32 at all then skip the checks entirely
985 * as the register values may be UNKNOWN and we're not going to be
986 * using them for anything.
988 if (!id_aa64pfr0_32bit_el0(pfr0))
992 * If we don't have AArch32 at EL1, then relax the strictness of
993 * EL1-dependent register fields to avoid spurious sanity check fails.
995 if (!id_aa64pfr0_32bit_el1(pfr0)) {
996 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT);
997 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT);
998 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT);
999 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT);
1000 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT);
1001 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT);
1004 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
1005 info->reg_id_dfr0, boot->reg_id_dfr0);
1006 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu,
1007 info->reg_id_dfr1, boot->reg_id_dfr1);
1008 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
1009 info->reg_id_isar0, boot->reg_id_isar0);
1010 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
1011 info->reg_id_isar1, boot->reg_id_isar1);
1012 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
1013 info->reg_id_isar2, boot->reg_id_isar2);
1014 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
1015 info->reg_id_isar3, boot->reg_id_isar3);
1016 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
1017 info->reg_id_isar4, boot->reg_id_isar4);
1018 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
1019 info->reg_id_isar5, boot->reg_id_isar5);
1020 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu,
1021 info->reg_id_isar6, boot->reg_id_isar6);
1024 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
1025 * ACTLR formats could differ across CPUs and therefore would have to
1026 * be trapped for virtualization anyway.
1028 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
1029 info->reg_id_mmfr0, boot->reg_id_mmfr0);
1030 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
1031 info->reg_id_mmfr1, boot->reg_id_mmfr1);
1032 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
1033 info->reg_id_mmfr2, boot->reg_id_mmfr2);
1034 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
1035 info->reg_id_mmfr3, boot->reg_id_mmfr3);
1036 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu,
1037 info->reg_id_mmfr4, boot->reg_id_mmfr4);
1038 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu,
1039 info->reg_id_mmfr5, boot->reg_id_mmfr5);
1040 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
1041 info->reg_id_pfr0, boot->reg_id_pfr0);
1042 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
1043 info->reg_id_pfr1, boot->reg_id_pfr1);
1044 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu,
1045 info->reg_id_pfr2, boot->reg_id_pfr2);
1046 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
1047 info->reg_mvfr0, boot->reg_mvfr0);
1048 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
1049 info->reg_mvfr1, boot->reg_mvfr1);
1050 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
1051 info->reg_mvfr2, boot->reg_mvfr2);
1057 * Update system wide CPU feature registers with the values from a
1058 * non-boot CPU. Also performs SANITY checks to make sure that there
1059 * aren't any insane variations from that of the boot CPU.
1061 void update_cpu_features(int cpu,
1062 struct cpuinfo_arm64 *info,
1063 struct cpuinfo_arm64 *boot)
1068 * The kernel can handle differing I-cache policies, but otherwise
1069 * caches should look identical. Userspace JITs will make use of
1072 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
1073 info->reg_ctr, boot->reg_ctr);
1076 * Userspace may perform DC ZVA instructions. Mismatched block sizes
1077 * could result in too much or too little memory being zeroed if a
1078 * process is preempted and migrated between CPUs.
1080 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
1081 info->reg_dczid, boot->reg_dczid);
1083 /* If different, timekeeping will be broken (especially with KVM) */
1084 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
1085 info->reg_cntfrq, boot->reg_cntfrq);
1088 * The kernel uses self-hosted debug features and expects CPUs to
1089 * support identical debug features. We presently need CTX_CMPs, WRPs,
1090 * and BRPs to be identical.
1091 * ID_AA64DFR1 is currently RES0.
1093 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
1094 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
1095 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
1096 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
1098 * Even in big.LITTLE, processors should be identical instruction-set
1101 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
1102 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
1103 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
1104 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
1107 * Differing PARange support is fine as long as all peripherals and
1108 * memory are mapped within the minimum PARange of all CPUs.
1109 * Linux should not care about secure memory.
1111 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
1112 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
1113 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
1114 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
1115 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
1116 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
1118 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
1119 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
1120 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
1121 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
1123 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
1124 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
1126 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
1127 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
1128 info->reg_zcr, boot->reg_zcr);
1130 /* Probe vector lengths, unless we already gave up on SVE */
1131 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
1132 !system_capabilities_finalized())
1133 sve_update_vq_map();
1137 * This relies on a sanitised view of the AArch64 ID registers
1138 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last.
1140 taint |= update_32bit_cpu_features(cpu, info, boot);
1143 * Mismatched CPU features are a recipe for disaster. Don't even
1144 * pretend to support them.
1147 pr_warn_once("Unsupported CPU feature variation detected.\n");
1148 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1152 u64 read_sanitised_ftr_reg(u32 id)
1154 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
1158 return regp->sys_val;
1160 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg);
1162 #define read_sysreg_case(r) \
1163 case r: val = read_sysreg_s(r); break;
1166 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
1167 * Read the system register on the current CPU
1169 u64 __read_sysreg_by_encoding(u32 sys_id)
1171 struct arm64_ftr_reg *regp;
1175 read_sysreg_case(SYS_ID_PFR0_EL1);
1176 read_sysreg_case(SYS_ID_PFR1_EL1);
1177 read_sysreg_case(SYS_ID_PFR2_EL1);
1178 read_sysreg_case(SYS_ID_DFR0_EL1);
1179 read_sysreg_case(SYS_ID_DFR1_EL1);
1180 read_sysreg_case(SYS_ID_MMFR0_EL1);
1181 read_sysreg_case(SYS_ID_MMFR1_EL1);
1182 read_sysreg_case(SYS_ID_MMFR2_EL1);
1183 read_sysreg_case(SYS_ID_MMFR3_EL1);
1184 read_sysreg_case(SYS_ID_MMFR4_EL1);
1185 read_sysreg_case(SYS_ID_MMFR5_EL1);
1186 read_sysreg_case(SYS_ID_ISAR0_EL1);
1187 read_sysreg_case(SYS_ID_ISAR1_EL1);
1188 read_sysreg_case(SYS_ID_ISAR2_EL1);
1189 read_sysreg_case(SYS_ID_ISAR3_EL1);
1190 read_sysreg_case(SYS_ID_ISAR4_EL1);
1191 read_sysreg_case(SYS_ID_ISAR5_EL1);
1192 read_sysreg_case(SYS_ID_ISAR6_EL1);
1193 read_sysreg_case(SYS_MVFR0_EL1);
1194 read_sysreg_case(SYS_MVFR1_EL1);
1195 read_sysreg_case(SYS_MVFR2_EL1);
1197 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
1198 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
1199 read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
1200 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
1201 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
1202 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
1203 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
1204 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
1205 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
1206 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
1208 read_sysreg_case(SYS_CNTFRQ_EL0);
1209 read_sysreg_case(SYS_CTR_EL0);
1210 read_sysreg_case(SYS_DCZID_EL0);
1217 regp = get_arm64_ftr_reg(sys_id);
1219 val &= ~regp->override->mask;
1220 val |= (regp->override->val & regp->override->mask);
1226 #include <linux/irqchip/arm-gic-v3.h>
1229 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
1231 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
1233 return val >= entry->min_field_value;
1237 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
1241 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1242 if (scope == SCOPE_SYSTEM)
1243 val = read_sanitised_ftr_reg(entry->sys_reg);
1245 val = __read_sysreg_by_encoding(entry->sys_reg);
1247 return feature_matches(val, entry);
1250 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
1254 if (!has_cpuid_feature(entry, scope))
1257 has_sre = gic_enable_sre();
1259 pr_warn_once("%s present but disabled by higher exception level\n",
1265 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
1267 u32 midr = read_cpuid_id();
1269 /* Cavium ThunderX pass 1.x and 2.x */
1270 return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
1271 MIDR_CPU_VAR_REV(0, 0),
1272 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
1275 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
1277 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1279 return cpuid_feature_extract_signed_field(pfr0,
1280 ID_AA64PFR0_FP_SHIFT) < 0;
1283 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
1288 if (scope == SCOPE_SYSTEM)
1289 ctr = arm64_ftr_reg_ctrel0.sys_val;
1291 ctr = read_cpuid_effective_cachetype();
1293 return ctr & BIT(CTR_IDC_SHIFT);
1296 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
1299 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
1300 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
1301 * to the CTR_EL0 on this CPU and emulate it with the real/safe
1304 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
1305 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
1308 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
1313 if (scope == SCOPE_SYSTEM)
1314 ctr = arm64_ftr_reg_ctrel0.sys_val;
1316 ctr = read_cpuid_cachetype();
1318 return ctr & BIT(CTR_DIC_SHIFT);
1321 static bool __maybe_unused
1322 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
1325 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
1326 * may share TLB entries with a CPU stuck in the crashed
1329 if (is_kdump_kernel())
1332 if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP))
1335 return has_cpuid_feature(entry, scope);
1339 * This check is triggered during the early boot before the cpufeature
1340 * is initialised. Checking the status on the local CPU allows the boot
1341 * CPU to detect the need for non-global mappings and thus avoiding a
1342 * pagetable re-write after all the CPUs are booted. This check will be
1343 * anyway run on individual CPUs, allowing us to get the consistent
1344 * state once the SMP CPUs are up and thus make the switch to non-global
1345 * mappings if required.
1347 bool kaslr_requires_kpti(void)
1349 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE))
1353 * E0PD does a similar job to KPTI so can be used instead
1356 if (IS_ENABLED(CONFIG_ARM64_E0PD)) {
1357 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1);
1358 if (cpuid_feature_extract_unsigned_field(mmfr2,
1359 ID_AA64MMFR2_E0PD_SHIFT))
1364 * Systems affected by Cavium erratum 24756 are incompatible
1367 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) {
1368 extern const struct midr_range cavium_erratum_27456_cpus[];
1370 if (is_midr_in_range_list(read_cpuid_id(),
1371 cavium_erratum_27456_cpus))
1375 return kaslr_offset() > 0;
1378 static bool __meltdown_safe = true;
1379 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
1381 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
1384 /* List of CPUs that are not vulnerable and don't need KPTI */
1385 static const struct midr_range kpti_safe_list[] = {
1386 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
1387 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
1388 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
1389 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
1390 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
1391 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1392 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
1393 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
1394 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
1395 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
1396 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
1397 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD),
1398 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER),
1399 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
1400 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
1403 char const *str = "kpti command line option";
1406 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
1408 /* Defer to CPU feature registers */
1409 if (has_cpuid_feature(entry, scope))
1410 meltdown_safe = true;
1413 __meltdown_safe = false;
1416 * For reasons that aren't entirely clear, enabling KPTI on Cavium
1417 * ThunderX leads to apparent I-cache corruption of kernel text, which
1418 * ends as well as you might imagine. Don't even try.
1420 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1421 str = "ARM64_WORKAROUND_CAVIUM_27456";
1425 /* Useful for KASLR robustness */
1426 if (kaslr_requires_kpti()) {
1427 if (!__kpti_forced) {
1433 if (cpu_mitigations_off() && !__kpti_forced) {
1434 str = "mitigations=off";
1438 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1439 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1444 if (__kpti_forced) {
1445 pr_info_once("kernel page table isolation forced %s by %s\n",
1446 __kpti_forced > 0 ? "ON" : "OFF", str);
1447 return __kpti_forced > 0;
1450 return !meltdown_safe;
1453 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1455 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1457 typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1458 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1459 kpti_remap_fn *remap_fn;
1461 int cpu = smp_processor_id();
1464 * We don't need to rewrite the page-tables if either we've done
1465 * it already or we have KASLR enabled and therefore have not
1466 * created any global mappings at all.
1468 if (arm64_use_ng_mappings)
1471 remap_fn = (void *)__pa_symbol(function_nocfi(idmap_kpti_install_ng_mappings));
1473 cpu_install_idmap();
1474 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1475 cpu_uninstall_idmap();
1478 arm64_use_ng_mappings = true;
1484 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1487 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1489 static int __init parse_kpti(char *str)
1492 int ret = strtobool(str, &enabled);
1497 __kpti_forced = enabled ? 1 : -1;
1500 early_param("kpti", parse_kpti);
1502 #ifdef CONFIG_ARM64_HW_AFDBM
1503 static inline void __cpu_enable_hw_dbm(void)
1505 u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1507 write_sysreg(tcr, tcr_el1);
1509 local_flush_tlb_all();
1512 static bool cpu_has_broken_dbm(void)
1514 /* List of CPUs which have broken DBM support. */
1515 static const struct midr_range cpus[] = {
1516 #ifdef CONFIG_ARM64_ERRATUM_1024718
1517 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1518 /* Kryo4xx Silver (rdpe => r1p0) */
1519 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
1524 return is_midr_in_range_list(read_cpuid_id(), cpus);
1527 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1529 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1530 !cpu_has_broken_dbm();
1533 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1535 if (cpu_can_use_dbm(cap))
1536 __cpu_enable_hw_dbm();
1539 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1542 static bool detected = false;
1544 * DBM is a non-conflicting feature. i.e, the kernel can safely
1545 * run a mix of CPUs with and without the feature. So, we
1546 * unconditionally enable the capability to allow any late CPU
1547 * to use the feature. We only enable the control bits on the
1548 * CPU, if it actually supports.
1550 * We have to make sure we print the "feature" detection only
1551 * when at least one CPU actually uses it. So check if this CPU
1552 * can actually use it and print the message exactly once.
1554 * This is safe as all CPUs (including secondary CPUs - due to the
1555 * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1556 * goes through the "matches" check exactly once. Also if a CPU
1557 * matches the criteria, it is guaranteed that the CPU will turn
1558 * the DBM on, as the capability is unconditionally enabled.
1560 if (!detected && cpu_can_use_dbm(cap)) {
1562 pr_info("detected: Hardware dirty bit management\n");
1570 #ifdef CONFIG_ARM64_AMU_EXTN
1573 * The "amu_cpus" cpumask only signals that the CPU implementation for the
1574 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide
1575 * information regarding all the events that it supports. When a CPU bit is
1576 * set in the cpumask, the user of this feature can only rely on the presence
1577 * of the 4 fixed counters for that CPU. But this does not guarantee that the
1578 * counters are enabled or access to these counters is enabled by code
1579 * executed at higher exception levels (firmware).
1581 static struct cpumask amu_cpus __read_mostly;
1583 bool cpu_has_amu_feat(int cpu)
1585 return cpumask_test_cpu(cpu, &amu_cpus);
1588 int get_cpu_with_amu_feat(void)
1590 return cpumask_any(&amu_cpus);
1593 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
1595 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) {
1596 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n",
1597 smp_processor_id());
1598 cpumask_set_cpu(smp_processor_id(), &amu_cpus);
1599 update_freq_counters_refs();
1603 static bool has_amu(const struct arm64_cpu_capabilities *cap,
1607 * The AMU extension is a non-conflicting feature: the kernel can
1608 * safely run a mix of CPUs with and without support for the
1609 * activity monitors extension. Therefore, unconditionally enable
1610 * the capability to allow any late CPU to use the feature.
1612 * With this feature unconditionally enabled, the cpu_enable
1613 * function will be called for all CPUs that match the criteria,
1614 * including secondary and hotplugged, marking this feature as
1615 * present on that respective CPU. The enable function will also
1616 * print a detection message.
1622 int get_cpu_with_amu_feat(void)
1628 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1630 return is_kernel_in_hyp_mode();
1633 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1636 * Copy register values that aren't redirected by hardware.
1638 * Before code patching, we only set tpidr_el1, all CPUs need to copy
1639 * this value to tpidr_el2 before we patch the code. Once we've done
1640 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1643 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1644 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1647 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1649 u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1651 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1652 WARN_ON(val & (7 << 27 | 7 << 21));
1655 #ifdef CONFIG_ARM64_PAN
1656 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1659 * We modify PSTATE. This won't work from irq context as the PSTATE
1660 * is discarded once we return from the exception.
1662 WARN_ON_ONCE(in_interrupt());
1664 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1667 #endif /* CONFIG_ARM64_PAN */
1669 #ifdef CONFIG_ARM64_RAS_EXTN
1670 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1672 /* Firmware may have left a deferred SError in this register. */
1673 write_sysreg_s(0, SYS_DISR_EL1);
1675 #endif /* CONFIG_ARM64_RAS_EXTN */
1677 #ifdef CONFIG_ARM64_PTR_AUTH
1678 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope)
1680 int boot_val, sec_val;
1682 /* We don't expect to be called with SCOPE_SYSTEM */
1683 WARN_ON(scope == SCOPE_SYSTEM);
1685 * The ptr-auth feature levels are not intercompatible with lower
1686 * levels. Hence we must match ptr-auth feature level of the secondary
1687 * CPUs with that of the boot CPU. The level of boot cpu is fetched
1688 * from the sanitised register whereas direct register read is done for
1689 * the secondary CPUs.
1690 * The sanitised feature state is guaranteed to match that of the
1691 * boot CPU as a mismatched secondary CPU is parked before it gets
1692 * a chance to update the state, with the capability.
1694 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg),
1695 entry->field_pos, entry->sign);
1696 if (scope & SCOPE_BOOT_CPU)
1697 return boot_val >= entry->min_field_value;
1698 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */
1699 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg),
1700 entry->field_pos, entry->sign);
1701 return sec_val == boot_val;
1704 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry,
1707 return has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH], scope) ||
1708 has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope);
1711 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,
1714 return __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH) ||
1715 __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF);
1717 #endif /* CONFIG_ARM64_PTR_AUTH */
1719 #ifdef CONFIG_ARM64_E0PD
1720 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
1722 if (this_cpu_has_cap(ARM64_HAS_E0PD))
1723 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
1725 #endif /* CONFIG_ARM64_E0PD */
1727 #ifdef CONFIG_ARM64_PSEUDO_NMI
1728 static bool enable_pseudo_nmi;
1730 static int __init early_enable_pseudo_nmi(char *p)
1732 return strtobool(p, &enable_pseudo_nmi);
1734 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1736 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1739 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
1743 #ifdef CONFIG_ARM64_BTI
1744 static void bti_enable(const struct arm64_cpu_capabilities *__unused)
1747 * Use of X16/X17 for tail-calls and trampolines that jump to
1748 * function entry points using BR is a requirement for
1749 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI.
1750 * So, be strict and forbid other BRs using other registers to
1751 * jump onto a PACIxSP instruction:
1753 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1);
1756 #endif /* CONFIG_ARM64_BTI */
1758 #ifdef CONFIG_ARM64_MTE
1759 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap)
1762 * Clear the tags in the zero page. This needs to be done via the
1763 * linear map which has the Tagged attribute.
1765 if (!test_and_set_bit(PG_mte_tagged, &ZERO_PAGE(0)->flags))
1766 mte_clear_page_tags(lm_alias(empty_zero_page));
1768 kasan_init_hw_tags_cpu();
1770 #endif /* CONFIG_ARM64_MTE */
1773 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused)
1775 if (kvm_get_mode() != KVM_MODE_PROTECTED)
1778 if (is_kernel_in_hyp_mode()) {
1779 pr_warn("Protected KVM not available with VHE\n");
1785 #endif /* CONFIG_KVM */
1787 /* Internal helper functions to match cpu capability type */
1789 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
1791 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);
1795 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap)
1797 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);
1801 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap)
1803 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT);
1806 static const struct arm64_cpu_capabilities arm64_features[] = {
1808 .desc = "GIC system register CPU interface",
1809 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1810 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1811 .matches = has_useable_gicv3_cpuif,
1812 .sys_reg = SYS_ID_AA64PFR0_EL1,
1813 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1814 .sign = FTR_UNSIGNED,
1815 .min_field_value = 1,
1817 #ifdef CONFIG_ARM64_PAN
1819 .desc = "Privileged Access Never",
1820 .capability = ARM64_HAS_PAN,
1821 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1822 .matches = has_cpuid_feature,
1823 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1824 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1825 .sign = FTR_UNSIGNED,
1826 .min_field_value = 1,
1827 .cpu_enable = cpu_enable_pan,
1829 #endif /* CONFIG_ARM64_PAN */
1830 #ifdef CONFIG_ARM64_EPAN
1832 .desc = "Enhanced Privileged Access Never",
1833 .capability = ARM64_HAS_EPAN,
1834 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1835 .matches = has_cpuid_feature,
1836 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1837 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1838 .sign = FTR_UNSIGNED,
1839 .min_field_value = 3,
1841 #endif /* CONFIG_ARM64_EPAN */
1842 #ifdef CONFIG_ARM64_LSE_ATOMICS
1844 .desc = "LSE atomic instructions",
1845 .capability = ARM64_HAS_LSE_ATOMICS,
1846 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1847 .matches = has_cpuid_feature,
1848 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1849 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1850 .sign = FTR_UNSIGNED,
1851 .min_field_value = 2,
1853 #endif /* CONFIG_ARM64_LSE_ATOMICS */
1855 .desc = "Software prefetching using PRFM",
1856 .capability = ARM64_HAS_NO_HW_PREFETCH,
1857 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1858 .matches = has_no_hw_prefetch,
1861 .desc = "Virtualization Host Extensions",
1862 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1863 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1864 .matches = runs_at_el2,
1865 .cpu_enable = cpu_copy_el2regs,
1868 .desc = "32-bit EL0 Support",
1869 .capability = ARM64_HAS_32BIT_EL0,
1870 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1871 .matches = has_cpuid_feature,
1872 .sys_reg = SYS_ID_AA64PFR0_EL1,
1873 .sign = FTR_UNSIGNED,
1874 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1875 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1879 .desc = "32-bit EL1 Support",
1880 .capability = ARM64_HAS_32BIT_EL1,
1881 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1882 .matches = has_cpuid_feature,
1883 .sys_reg = SYS_ID_AA64PFR0_EL1,
1884 .sign = FTR_UNSIGNED,
1885 .field_pos = ID_AA64PFR0_EL1_SHIFT,
1886 .min_field_value = ID_AA64PFR0_EL1_32BIT_64BIT,
1889 .desc = "Protected KVM",
1890 .capability = ARM64_KVM_PROTECTED_MODE,
1891 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1892 .matches = is_kvm_protected_mode,
1896 .desc = "Kernel page table isolation (KPTI)",
1897 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1898 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1900 * The ID feature fields below are used to indicate that
1901 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1904 .sys_reg = SYS_ID_AA64PFR0_EL1,
1905 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1906 .min_field_value = 1,
1907 .matches = unmap_kernel_at_el0,
1908 .cpu_enable = kpti_install_ng_mappings,
1911 /* FP/SIMD is not implemented */
1912 .capability = ARM64_HAS_NO_FPSIMD,
1913 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1914 .min_field_value = 0,
1915 .matches = has_no_fpsimd,
1917 #ifdef CONFIG_ARM64_PMEM
1919 .desc = "Data cache clean to Point of Persistence",
1920 .capability = ARM64_HAS_DCPOP,
1921 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1922 .matches = has_cpuid_feature,
1923 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1924 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1925 .min_field_value = 1,
1928 .desc = "Data cache clean to Point of Deep Persistence",
1929 .capability = ARM64_HAS_DCPODP,
1930 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1931 .matches = has_cpuid_feature,
1932 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1933 .sign = FTR_UNSIGNED,
1934 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1935 .min_field_value = 2,
1938 #ifdef CONFIG_ARM64_SVE
1940 .desc = "Scalable Vector Extension",
1941 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1942 .capability = ARM64_SVE,
1943 .sys_reg = SYS_ID_AA64PFR0_EL1,
1944 .sign = FTR_UNSIGNED,
1945 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1946 .min_field_value = ID_AA64PFR0_SVE,
1947 .matches = has_cpuid_feature,
1948 .cpu_enable = sve_kernel_enable,
1950 #endif /* CONFIG_ARM64_SVE */
1951 #ifdef CONFIG_ARM64_RAS_EXTN
1953 .desc = "RAS Extension Support",
1954 .capability = ARM64_HAS_RAS_EXTN,
1955 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1956 .matches = has_cpuid_feature,
1957 .sys_reg = SYS_ID_AA64PFR0_EL1,
1958 .sign = FTR_UNSIGNED,
1959 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1960 .min_field_value = ID_AA64PFR0_RAS_V1,
1961 .cpu_enable = cpu_clear_disr,
1963 #endif /* CONFIG_ARM64_RAS_EXTN */
1964 #ifdef CONFIG_ARM64_AMU_EXTN
1967 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y.
1968 * Therefore, don't provide .desc as we don't want the detection
1969 * message to be shown until at least one CPU is detected to
1970 * support the feature.
1972 .capability = ARM64_HAS_AMU_EXTN,
1973 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1975 .sys_reg = SYS_ID_AA64PFR0_EL1,
1976 .sign = FTR_UNSIGNED,
1977 .field_pos = ID_AA64PFR0_AMU_SHIFT,
1978 .min_field_value = ID_AA64PFR0_AMU,
1979 .cpu_enable = cpu_amu_enable,
1981 #endif /* CONFIG_ARM64_AMU_EXTN */
1983 .desc = "Data cache clean to the PoU not required for I/D coherence",
1984 .capability = ARM64_HAS_CACHE_IDC,
1985 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1986 .matches = has_cache_idc,
1987 .cpu_enable = cpu_emulate_effective_ctr,
1990 .desc = "Instruction cache invalidation not required for I/D coherence",
1991 .capability = ARM64_HAS_CACHE_DIC,
1992 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1993 .matches = has_cache_dic,
1996 .desc = "Stage-2 Force Write-Back",
1997 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1998 .capability = ARM64_HAS_STAGE2_FWB,
1999 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2000 .sign = FTR_UNSIGNED,
2001 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
2002 .min_field_value = 1,
2003 .matches = has_cpuid_feature,
2004 .cpu_enable = cpu_has_fwb,
2007 .desc = "ARMv8.4 Translation Table Level",
2008 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2009 .capability = ARM64_HAS_ARMv8_4_TTL,
2010 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2011 .sign = FTR_UNSIGNED,
2012 .field_pos = ID_AA64MMFR2_TTL_SHIFT,
2013 .min_field_value = 1,
2014 .matches = has_cpuid_feature,
2017 .desc = "TLB range maintenance instructions",
2018 .capability = ARM64_HAS_TLB_RANGE,
2019 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2020 .matches = has_cpuid_feature,
2021 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2022 .field_pos = ID_AA64ISAR0_TLB_SHIFT,
2023 .sign = FTR_UNSIGNED,
2024 .min_field_value = ID_AA64ISAR0_TLB_RANGE,
2026 #ifdef CONFIG_ARM64_HW_AFDBM
2029 * Since we turn this on always, we don't want the user to
2030 * think that the feature is available when it may not be.
2031 * So hide the description.
2033 * .desc = "Hardware pagetable Dirty Bit Management",
2036 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2037 .capability = ARM64_HW_DBM,
2038 .sys_reg = SYS_ID_AA64MMFR1_EL1,
2039 .sign = FTR_UNSIGNED,
2040 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
2041 .min_field_value = 2,
2042 .matches = has_hw_dbm,
2043 .cpu_enable = cpu_enable_hw_dbm,
2047 .desc = "CRC32 instructions",
2048 .capability = ARM64_HAS_CRC32,
2049 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2050 .matches = has_cpuid_feature,
2051 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2052 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
2053 .min_field_value = 1,
2056 .desc = "Speculative Store Bypassing Safe (SSBS)",
2057 .capability = ARM64_SSBS,
2058 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2059 .matches = has_cpuid_feature,
2060 .sys_reg = SYS_ID_AA64PFR1_EL1,
2061 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
2062 .sign = FTR_UNSIGNED,
2063 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
2065 #ifdef CONFIG_ARM64_CNP
2067 .desc = "Common not Private translations",
2068 .capability = ARM64_HAS_CNP,
2069 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2070 .matches = has_useable_cnp,
2071 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2072 .sign = FTR_UNSIGNED,
2073 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
2074 .min_field_value = 1,
2075 .cpu_enable = cpu_enable_cnp,
2079 .desc = "Speculation barrier (SB)",
2080 .capability = ARM64_HAS_SB,
2081 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2082 .matches = has_cpuid_feature,
2083 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2084 .field_pos = ID_AA64ISAR1_SB_SHIFT,
2085 .sign = FTR_UNSIGNED,
2086 .min_field_value = 1,
2088 #ifdef CONFIG_ARM64_PTR_AUTH
2090 .desc = "Address authentication (architected algorithm)",
2091 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
2092 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2093 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2094 .sign = FTR_UNSIGNED,
2095 .field_pos = ID_AA64ISAR1_APA_SHIFT,
2096 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
2097 .matches = has_address_auth_cpucap,
2100 .desc = "Address authentication (IMP DEF algorithm)",
2101 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
2102 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2103 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2104 .sign = FTR_UNSIGNED,
2105 .field_pos = ID_AA64ISAR1_API_SHIFT,
2106 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
2107 .matches = has_address_auth_cpucap,
2110 .capability = ARM64_HAS_ADDRESS_AUTH,
2111 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2112 .matches = has_address_auth_metacap,
2115 .desc = "Generic authentication (architected algorithm)",
2116 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
2117 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2118 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2119 .sign = FTR_UNSIGNED,
2120 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
2121 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
2122 .matches = has_cpuid_feature,
2125 .desc = "Generic authentication (IMP DEF algorithm)",
2126 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
2127 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2128 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2129 .sign = FTR_UNSIGNED,
2130 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
2131 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
2132 .matches = has_cpuid_feature,
2135 .capability = ARM64_HAS_GENERIC_AUTH,
2136 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2137 .matches = has_generic_auth,
2139 #endif /* CONFIG_ARM64_PTR_AUTH */
2140 #ifdef CONFIG_ARM64_PSEUDO_NMI
2143 * Depends on having GICv3
2145 .desc = "IRQ priority masking",
2146 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
2147 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2148 .matches = can_use_gic_priorities,
2149 .sys_reg = SYS_ID_AA64PFR0_EL1,
2150 .field_pos = ID_AA64PFR0_GIC_SHIFT,
2151 .sign = FTR_UNSIGNED,
2152 .min_field_value = 1,
2155 #ifdef CONFIG_ARM64_E0PD
2158 .capability = ARM64_HAS_E0PD,
2159 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2160 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2161 .sign = FTR_UNSIGNED,
2162 .field_pos = ID_AA64MMFR2_E0PD_SHIFT,
2163 .matches = has_cpuid_feature,
2164 .min_field_value = 1,
2165 .cpu_enable = cpu_enable_e0pd,
2168 #ifdef CONFIG_ARCH_RANDOM
2170 .desc = "Random Number Generator",
2171 .capability = ARM64_HAS_RNG,
2172 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2173 .matches = has_cpuid_feature,
2174 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2175 .field_pos = ID_AA64ISAR0_RNDR_SHIFT,
2176 .sign = FTR_UNSIGNED,
2177 .min_field_value = 1,
2180 #ifdef CONFIG_ARM64_BTI
2182 .desc = "Branch Target Identification",
2183 .capability = ARM64_BTI,
2184 #ifdef CONFIG_ARM64_BTI_KERNEL
2185 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2187 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2189 .matches = has_cpuid_feature,
2190 .cpu_enable = bti_enable,
2191 .sys_reg = SYS_ID_AA64PFR1_EL1,
2192 .field_pos = ID_AA64PFR1_BT_SHIFT,
2193 .min_field_value = ID_AA64PFR1_BT_BTI,
2194 .sign = FTR_UNSIGNED,
2197 #ifdef CONFIG_ARM64_MTE
2199 .desc = "Memory Tagging Extension",
2200 .capability = ARM64_MTE,
2201 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2202 .matches = has_cpuid_feature,
2203 .sys_reg = SYS_ID_AA64PFR1_EL1,
2204 .field_pos = ID_AA64PFR1_MTE_SHIFT,
2205 .min_field_value = ID_AA64PFR1_MTE,
2206 .sign = FTR_UNSIGNED,
2207 .cpu_enable = cpu_enable_mte,
2209 #endif /* CONFIG_ARM64_MTE */
2211 .desc = "RCpc load-acquire (LDAPR)",
2212 .capability = ARM64_HAS_LDAPR,
2213 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2214 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2215 .sign = FTR_UNSIGNED,
2216 .field_pos = ID_AA64ISAR1_LRCPC_SHIFT,
2217 .matches = has_cpuid_feature,
2218 .min_field_value = 1,
2223 #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \
2224 .matches = has_cpuid_feature, \
2226 .field_pos = field, \
2228 .min_field_value = min_value,
2230 #define __HWCAP_CAP(name, cap_type, cap) \
2232 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
2233 .hwcap_type = cap_type, \
2236 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \
2238 __HWCAP_CAP(#cap, cap_type, cap) \
2239 HWCAP_CPUID_MATCH(reg, field, s, min_value) \
2242 #define HWCAP_MULTI_CAP(list, cap_type, cap) \
2244 __HWCAP_CAP(#cap, cap_type, cap) \
2245 .matches = cpucap_multi_entry_cap_matches, \
2246 .match_list = list, \
2249 #define HWCAP_CAP_MATCH(match, cap_type, cap) \
2251 __HWCAP_CAP(#cap, cap_type, cap) \
2255 #ifdef CONFIG_ARM64_PTR_AUTH
2256 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
2258 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
2259 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
2262 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
2263 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
2268 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
2270 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
2271 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
2274 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
2275 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
2281 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
2282 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
2283 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
2284 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
2285 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
2286 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
2287 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
2288 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
2289 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
2290 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
2291 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
2292 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
2293 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
2294 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
2295 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
2296 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
2297 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG),
2298 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
2299 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
2300 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
2301 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
2302 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
2303 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
2304 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
2305 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
2306 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
2307 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
2308 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
2309 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
2310 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
2311 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16),
2312 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH),
2313 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM),
2314 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
2315 #ifdef CONFIG_ARM64_SVE
2316 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
2317 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
2318 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
2319 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
2320 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
2321 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
2322 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
2323 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
2324 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
2325 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
2326 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
2328 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
2329 #ifdef CONFIG_ARM64_BTI
2330 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_BT_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI),
2332 #ifdef CONFIG_ARM64_PTR_AUTH
2333 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
2334 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
2336 #ifdef CONFIG_ARM64_MTE
2337 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE),
2338 #endif /* CONFIG_ARM64_MTE */
2342 #ifdef CONFIG_COMPAT
2343 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
2346 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
2347 * in line with that of arm32 as in vfp_init(). We make sure that the
2348 * check is future proof, by making sure value is non-zero.
2352 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
2353 if (scope == SCOPE_SYSTEM)
2354 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
2356 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
2358 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
2359 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
2360 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
2364 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
2365 #ifdef CONFIG_COMPAT
2366 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
2367 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
2368 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
2369 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
2370 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
2371 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
2372 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
2373 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
2374 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
2375 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
2380 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2382 switch (cap->hwcap_type) {
2384 cpu_set_feature(cap->hwcap);
2386 #ifdef CONFIG_COMPAT
2387 case CAP_COMPAT_HWCAP:
2388 compat_elf_hwcap |= (u32)cap->hwcap;
2390 case CAP_COMPAT_HWCAP2:
2391 compat_elf_hwcap2 |= (u32)cap->hwcap;
2400 /* Check if we have a particular HWCAP enabled */
2401 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2405 switch (cap->hwcap_type) {
2407 rc = cpu_have_feature(cap->hwcap);
2409 #ifdef CONFIG_COMPAT
2410 case CAP_COMPAT_HWCAP:
2411 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
2413 case CAP_COMPAT_HWCAP2:
2414 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
2425 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
2427 /* We support emulation of accesses to CPU ID feature registers */
2428 cpu_set_named_feature(CPUID);
2429 for (; hwcaps->matches; hwcaps++)
2430 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
2431 cap_set_elf_hwcap(hwcaps);
2434 static void update_cpu_capabilities(u16 scope_mask)
2437 const struct arm64_cpu_capabilities *caps;
2439 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2440 for (i = 0; i < ARM64_NCAPS; i++) {
2441 caps = cpu_hwcaps_ptrs[i];
2442 if (!caps || !(caps->type & scope_mask) ||
2443 cpus_have_cap(caps->capability) ||
2444 !caps->matches(caps, cpucap_default_scope(caps)))
2448 pr_info("detected: %s\n", caps->desc);
2449 cpus_set_cap(caps->capability);
2451 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
2452 set_bit(caps->capability, boot_capabilities);
2457 * Enable all the available capabilities on this CPU. The capabilities
2458 * with BOOT_CPU scope are handled separately and hence skipped here.
2460 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
2463 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
2465 for_each_available_cap(i) {
2466 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
2471 if (!(cap->type & non_boot_scope))
2474 if (cap->cpu_enable)
2475 cap->cpu_enable(cap);
2481 * Run through the enabled capabilities and enable() it on all active
2484 static void __init enable_cpu_capabilities(u16 scope_mask)
2487 const struct arm64_cpu_capabilities *caps;
2490 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2491 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
2493 for (i = 0; i < ARM64_NCAPS; i++) {
2496 caps = cpu_hwcaps_ptrs[i];
2497 if (!caps || !(caps->type & scope_mask))
2499 num = caps->capability;
2500 if (!cpus_have_cap(num))
2503 /* Ensure cpus_have_const_cap(num) works */
2504 static_branch_enable(&cpu_hwcap_keys[num]);
2506 if (boot_scope && caps->cpu_enable)
2508 * Capabilities with SCOPE_BOOT_CPU scope are finalised
2509 * before any secondary CPU boots. Thus, each secondary
2510 * will enable the capability as appropriate via
2511 * check_local_cpu_capabilities(). The only exception is
2512 * the boot CPU, for which the capability must be
2513 * enabled here. This approach avoids costly
2514 * stop_machine() calls for this case.
2516 caps->cpu_enable(caps);
2520 * For all non-boot scope capabilities, use stop_machine()
2521 * as it schedules the work allowing us to modify PSTATE,
2522 * instead of on_each_cpu() which uses an IPI, giving us a
2523 * PSTATE that disappears when we return.
2526 stop_machine(cpu_enable_non_boot_scope_capabilities,
2527 NULL, cpu_online_mask);
2531 * Run through the list of capabilities to check for conflicts.
2532 * If the system has already detected a capability, take necessary
2533 * action on this CPU.
2535 static void verify_local_cpu_caps(u16 scope_mask)
2538 bool cpu_has_cap, system_has_cap;
2539 const struct arm64_cpu_capabilities *caps;
2541 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2543 for (i = 0; i < ARM64_NCAPS; i++) {
2544 caps = cpu_hwcaps_ptrs[i];
2545 if (!caps || !(caps->type & scope_mask))
2548 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
2549 system_has_cap = cpus_have_cap(caps->capability);
2551 if (system_has_cap) {
2553 * Check if the new CPU misses an advertised feature,
2554 * which is not safe to miss.
2556 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
2559 * We have to issue cpu_enable() irrespective of
2560 * whether the CPU has it or not, as it is enabeld
2561 * system wide. It is upto the call back to take
2562 * appropriate action on this CPU.
2564 if (caps->cpu_enable)
2565 caps->cpu_enable(caps);
2568 * Check if the CPU has this capability if it isn't
2569 * safe to have when the system doesn't.
2571 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
2576 if (i < ARM64_NCAPS) {
2577 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
2578 smp_processor_id(), caps->capability,
2579 caps->desc, system_has_cap, cpu_has_cap);
2581 if (cpucap_panic_on_conflict(caps))
2589 * Check for CPU features that are used in early boot
2590 * based on the Boot CPU value.
2592 static void check_early_cpu_features(void)
2594 verify_cpu_asid_bits();
2596 verify_local_cpu_caps(SCOPE_BOOT_CPU);
2600 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
2603 for (; caps->matches; caps++)
2604 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
2605 pr_crit("CPU%d: missing HWCAP: %s\n",
2606 smp_processor_id(), caps->desc);
2611 static void verify_sve_features(void)
2613 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
2614 u64 zcr = read_zcr_features();
2616 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
2617 unsigned int len = zcr & ZCR_ELx_LEN_MASK;
2619 if (len < safe_len || sve_verify_vq_map()) {
2620 pr_crit("CPU%d: SVE: vector length support mismatch\n",
2621 smp_processor_id());
2625 /* Add checks on other ZCR bits here if necessary */
2628 static void verify_hyp_capabilities(void)
2630 u64 safe_mmfr1, mmfr0, mmfr1;
2631 int parange, ipa_max;
2632 unsigned int safe_vmid_bits, vmid_bits;
2634 if (!IS_ENABLED(CONFIG_KVM))
2637 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
2638 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
2639 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
2641 /* Verify VMID bits */
2642 safe_vmid_bits = get_vmid_bits(safe_mmfr1);
2643 vmid_bits = get_vmid_bits(mmfr1);
2644 if (vmid_bits < safe_vmid_bits) {
2645 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id());
2649 /* Verify IPA range */
2650 parange = cpuid_feature_extract_unsigned_field(mmfr0,
2651 ID_AA64MMFR0_PARANGE_SHIFT);
2652 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange);
2653 if (ipa_max < get_kvm_ipa_limit()) {
2654 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id());
2660 * Run through the enabled system capabilities and enable() it on this CPU.
2661 * The capabilities were decided based on the available CPUs at the boot time.
2662 * Any new CPU should match the system wide status of the capability. If the
2663 * new CPU doesn't have a capability which the system now has enabled, we
2664 * cannot do anything to fix it up and could cause unexpected failures. So
2667 static void verify_local_cpu_capabilities(void)
2670 * The capabilities with SCOPE_BOOT_CPU are checked from
2671 * check_early_cpu_features(), as they need to be verified
2672 * on all secondary CPUs.
2674 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2676 verify_local_elf_hwcaps(arm64_elf_hwcaps);
2678 if (system_supports_32bit_el0())
2679 verify_local_elf_hwcaps(compat_elf_hwcaps);
2681 if (system_supports_sve())
2682 verify_sve_features();
2684 if (is_hyp_mode_available())
2685 verify_hyp_capabilities();
2688 void check_local_cpu_capabilities(void)
2691 * All secondary CPUs should conform to the early CPU features
2692 * in use by the kernel based on boot CPU.
2694 check_early_cpu_features();
2697 * If we haven't finalised the system capabilities, this CPU gets
2698 * a chance to update the errata work arounds and local features.
2699 * Otherwise, this CPU should verify that it has all the system
2700 * advertised capabilities.
2702 if (!system_capabilities_finalized())
2703 update_cpu_capabilities(SCOPE_LOCAL_CPU);
2705 verify_local_cpu_capabilities();
2708 static void __init setup_boot_cpu_capabilities(void)
2710 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
2711 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
2712 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
2713 enable_cpu_capabilities(SCOPE_BOOT_CPU);
2716 bool this_cpu_has_cap(unsigned int n)
2718 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
2719 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2722 return cap->matches(cap, SCOPE_LOCAL_CPU);
2729 * This helper function is used in a narrow window when,
2730 * - The system wide safe registers are set with all the SMP CPUs and,
2731 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set.
2732 * In all other cases cpus_have_{const_}cap() should be used.
2734 static bool __maybe_unused __system_matches_cap(unsigned int n)
2736 if (n < ARM64_NCAPS) {
2737 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2740 return cap->matches(cap, SCOPE_SYSTEM);
2745 void cpu_set_feature(unsigned int num)
2747 WARN_ON(num >= MAX_CPU_FEATURES);
2748 elf_hwcap |= BIT(num);
2750 EXPORT_SYMBOL_GPL(cpu_set_feature);
2752 bool cpu_have_feature(unsigned int num)
2754 WARN_ON(num >= MAX_CPU_FEATURES);
2755 return elf_hwcap & BIT(num);
2757 EXPORT_SYMBOL_GPL(cpu_have_feature);
2759 unsigned long cpu_get_elf_hwcap(void)
2762 * We currently only populate the first 32 bits of AT_HWCAP. Please
2763 * note that for userspace compatibility we guarantee that bits 62
2764 * and 63 will always be returned as 0.
2766 return lower_32_bits(elf_hwcap);
2769 unsigned long cpu_get_elf_hwcap2(void)
2771 return upper_32_bits(elf_hwcap);
2774 static void __init setup_system_capabilities(void)
2777 * We have finalised the system-wide safe feature
2778 * registers, finalise the capabilities that depend
2779 * on it. Also enable all the available capabilities,
2780 * that are not enabled already.
2782 update_cpu_capabilities(SCOPE_SYSTEM);
2783 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2786 void __init setup_cpu_features(void)
2790 setup_system_capabilities();
2791 setup_elf_hwcaps(arm64_elf_hwcaps);
2793 if (system_supports_32bit_el0())
2794 setup_elf_hwcaps(compat_elf_hwcaps);
2796 if (system_uses_ttbr0_pan())
2797 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
2800 minsigstksz_setup();
2802 /* Advertise that we have computed the system capabilities */
2803 finalize_system_capabilities();
2806 * Check for sane CTR_EL0.CWG value.
2808 cwg = cache_type_cwg();
2810 pr_warn("No Cache Writeback Granule information, assuming %d\n",
2814 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
2816 cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
2820 * We emulate only the following system register space.
2821 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
2822 * See Table C5-6 System instruction encodings for System register accesses,
2823 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
2825 static inline bool __attribute_const__ is_emulated(u32 id)
2827 return (sys_reg_Op0(id) == 0x3 &&
2828 sys_reg_CRn(id) == 0x0 &&
2829 sys_reg_Op1(id) == 0x0 &&
2830 (sys_reg_CRm(id) == 0 ||
2831 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
2835 * With CRm == 0, reg should be one of :
2836 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
2838 static inline int emulate_id_reg(u32 id, u64 *valp)
2842 *valp = read_cpuid_id();
2845 *valp = SYS_MPIDR_SAFE_VAL;
2847 case SYS_REVIDR_EL1:
2848 /* IMPLEMENTATION DEFINED values are emulated with 0 */
2858 static int emulate_sys_reg(u32 id, u64 *valp)
2860 struct arm64_ftr_reg *regp;
2862 if (!is_emulated(id))
2865 if (sys_reg_CRm(id) == 0)
2866 return emulate_id_reg(id, valp);
2868 regp = get_arm64_ftr_reg_nowarn(id);
2870 *valp = arm64_ftr_reg_user_value(regp);
2873 * The untracked registers are either IMPLEMENTATION DEFINED
2874 * (e.g, ID_AFR0_EL1) or reserved RAZ.
2880 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
2885 rc = emulate_sys_reg(sys_reg, &val);
2887 pt_regs_write_reg(regs, rt, val);
2888 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
2893 static int emulate_mrs(struct pt_regs *regs, u32 insn)
2898 * sys_reg values are defined as used in mrs/msr instruction.
2899 * shift the imm value to get the encoding.
2901 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
2902 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
2903 return do_emulate_mrs(regs, sys_reg, rt);
2906 static struct undef_hook mrs_hook = {
2907 .instr_mask = 0xfff00000,
2908 .instr_val = 0xd5300000,
2909 .pstate_mask = PSR_AA32_MODE_MASK,
2910 .pstate_val = PSR_MODE_EL0t,
2914 static int __init enable_mrs_emulation(void)
2916 register_undef_hook(&mrs_hook);
2920 core_initcall(enable_mrs_emulation);
2922 enum mitigation_state arm64_get_meltdown_state(void)
2924 if (__meltdown_safe)
2925 return SPECTRE_UNAFFECTED;
2927 if (arm64_kernel_unmapped_at_el0())
2928 return SPECTRE_MITIGATED;
2930 return SPECTRE_VULNERABLE;
2933 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
2936 switch (arm64_get_meltdown_state()) {
2937 case SPECTRE_UNAFFECTED:
2938 return sprintf(buf, "Not affected\n");
2940 case SPECTRE_MITIGATED:
2941 return sprintf(buf, "Mitigation: PTI\n");
2944 return sprintf(buf, "Vulnerable\n");