1 // SPDX-License-Identifier: GPL-2.0-only
3 * Contains CPU feature definitions
5 * Copyright (C) 2015 ARM Ltd.
7 * A note for the weary kernel hacker: the code here is confusing and hard to
8 * follow! That's partly because it's solving a nasty problem, but also because
9 * there's a little bit of over-abstraction that tends to obscure what's going
10 * on behind a maze of helper functions and macros.
12 * The basic problem is that hardware folks have started gluing together CPUs
13 * with distinct architectural features; in some cases even creating SoCs where
14 * user-visible instructions are available only on a subset of the available
15 * cores. We try to address this by snapshotting the feature registers of the
16 * boot CPU and comparing these with the feature registers of each secondary
17 * CPU when bringing them up. If there is a mismatch, then we update the
18 * snapshot state to indicate the lowest-common denominator of the feature,
19 * known as the "safe" value. This snapshot state can be queried to view the
20 * "sanitised" value of a feature register.
22 * The sanitised register values are used to decide which capabilities we
23 * have in the system. These may be in the form of traditional "hwcaps"
24 * advertised to userspace or internal "cpucaps" which are used to configure
25 * things like alternative patching and static keys. While a feature mismatch
26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch
27 * may prevent a CPU from being onlined at all.
29 * Some implementation details worth remembering:
31 * - Mismatched features are *always* sanitised to a "safe" value, which
32 * usually indicates that the feature is not supported.
34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
35 * warning when onlining an offending CPU and the kernel will be tainted
36 * with TAINT_CPU_OUT_OF_SPEC.
38 * - Features marked as FTR_VISIBLE have their sanitised value visible to
39 * userspace. FTR_VISIBLE features in registers that are only visible
40 * to EL0 by trapping *must* have a corresponding HWCAP so that late
41 * onlining of CPUs cannot lead to features disappearing at runtime.
43 * - A "feature" is typically a 4-bit register field. A "capability" is the
44 * high-level description derived from the sanitised field value.
46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID
47 * scheme for fields in ID registers") to understand when feature fields
48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly).
50 * - KVM exposes its own view of the feature registers to guest operating
51 * systems regardless of FTR_VISIBLE. This is typically driven from the
52 * sanitised register values to allow virtual CPUs to be migrated between
53 * arbitrary physical CPUs, but some features not present on the host are
54 * also advertised and emulated. Look at sys_reg_descs[] for the gory
57 * - If the arm64_ftr_bits[] for a register has a missing field, then this
58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg().
59 * This is stronger than FTR_HIDDEN and can be used to hide features from
63 #define pr_fmt(fmt) "CPU features: " fmt
65 #include <linux/bsearch.h>
66 #include <linux/cpumask.h>
67 #include <linux/crash_dump.h>
68 #include <linux/sort.h>
69 #include <linux/stop_machine.h>
70 #include <linux/types.h>
71 #include <linux/minmax.h>
73 #include <linux/cpu.h>
74 #include <linux/kasan.h>
76 #include <asm/cpufeature.h>
77 #include <asm/cpu_ops.h>
78 #include <asm/fpsimd.h>
80 #include <asm/kvm_host.h>
81 #include <asm/mmu_context.h>
83 #include <asm/processor.h>
84 #include <asm/sysreg.h>
85 #include <asm/traps.h>
88 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
89 static unsigned long elf_hwcap __read_mostly;
92 #define COMPAT_ELF_HWCAP_DEFAULT \
93 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
94 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
95 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
97 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
98 unsigned int compat_elf_hwcap2 __read_mostly;
101 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
102 EXPORT_SYMBOL(cpu_hwcaps);
103 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
105 /* Need also bit for ARM64_CB_PATCH */
106 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
108 bool arm64_use_ng_mappings = false;
109 EXPORT_SYMBOL(arm64_use_ng_mappings);
112 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs
115 static bool __read_mostly allow_mismatched_32bit_el0;
118 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have
119 * seen at least one CPU capable of 32-bit EL0.
121 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0);
124 * Mask of CPUs supporting 32-bit EL0.
125 * Only valid if arm64_mismatched_32bit_el0 is enabled.
127 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly;
130 * Flag to indicate if we have computed the system wide
131 * capabilities based on the boot time active CPUs. This
132 * will be used to determine if a new booting CPU should
133 * go through the verification process to make sure that it
134 * supports the system capabilities, without using a hotplug
135 * notifier. This is also used to decide if we could use
136 * the fast path for checking constant CPU caps.
138 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
139 EXPORT_SYMBOL(arm64_const_caps_ready);
140 static inline void finalize_system_capabilities(void)
142 static_branch_enable(&arm64_const_caps_ready);
145 void dump_cpu_features(void)
147 /* file-wide pr_fmt adds "CPU features: " prefix */
148 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
151 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
152 EXPORT_SYMBOL(cpu_hwcap_keys);
154 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
157 .visible = VISIBLE, \
162 .safe_val = SAFE_VAL, \
165 /* Define a feature with unsigned values */
166 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
167 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
169 /* Define a feature with a signed value */
170 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
171 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
173 #define ARM64_FTR_END \
178 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
180 static bool __system_matches_cap(unsigned int n);
183 * NOTE: Any changes to the visibility of features should be kept in
184 * sync with the documentation of the CPU feature register ABI.
186 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
187 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0),
188 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLB_SHIFT, 4, 0),
189 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
190 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
191 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
192 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
193 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
194 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
196 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
197 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
198 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
199 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
200 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
204 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
205 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0),
206 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0),
207 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0),
208 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0),
209 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
210 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
211 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
212 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
213 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
214 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
215 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
216 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
217 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
218 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
219 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0),
220 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
221 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0),
222 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
226 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
227 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
228 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
229 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
230 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0),
231 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0),
232 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0),
233 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
234 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
235 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
236 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
237 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
238 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
239 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
240 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
242 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
246 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
247 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0),
248 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0),
249 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE),
250 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, ID_AA64PFR1_MTE_NI),
251 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
252 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI),
253 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0),
257 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
258 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
259 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0),
260 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
261 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0),
262 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
263 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0),
264 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
265 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
266 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
267 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
268 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
269 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0),
270 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
271 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
272 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
273 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
274 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
275 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
279 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
280 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0),
281 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0),
282 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0),
284 * Page size not being supported at Stage-2 is not fatal. You
285 * just give up KVM if PAGE_SIZE isn't supported there. Go fix
286 * your favourite nesting hypervisor.
288 * There is a small corner case where the hypervisor explicitly
289 * advertises a given granule size at Stage-2 (value 2) on some
290 * vCPUs, and uses the fallback to Stage-1 (value 0) for other
291 * vCPUs. Although this is not forbidden by the architecture, it
292 * indicates that the hypervisor is being silly (or buggy).
294 * We make no effort to cope with this and pretend that if these
295 * fields are inconsistent across vCPUs, then it isn't worth
296 * trying to bring KVM up.
298 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1),
299 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1),
300 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1),
302 * We already refuse to boot CPUs that don't support our configured
303 * page size, so we can only detect mismatches for a page size other
304 * than the one we're currently using. Unfortunately, SoCs like this
305 * exist in the wild so, even though we don't like it, we'll have to go
306 * along with it and treat them as non-strict.
308 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
309 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
310 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
312 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
313 /* Linux shouldn't care about secure memory */
314 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
315 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
316 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
318 * Differing PARange is fine as long as all peripherals and memory are mapped
319 * within the minimum PARange of all CPUs
321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
325 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
326 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0),
327 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0),
328 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0),
329 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0),
330 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
331 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
332 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
333 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
334 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
335 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
339 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
340 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0),
341 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EVT_SHIFT, 4, 0),
342 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_BBM_SHIFT, 4, 0),
343 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0),
344 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
345 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IDS_SHIFT, 4, 0),
346 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
347 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_ST_SHIFT, 4, 0),
348 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_NV_SHIFT, 4, 0),
349 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CCIDX_SHIFT, 4, 0),
350 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
351 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
352 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
353 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
354 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
358 static const struct arm64_ftr_bits ftr_ctr[] = {
359 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
360 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
361 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
362 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
363 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
364 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
366 * Linux can handle differing I-cache policies. Userspace JITs will
367 * make use of *minLine.
368 * If we have differing I-cache policies, report it as the weakest - VIPT.
370 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT), /* L1Ip */
371 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
375 static struct arm64_ftr_override __ro_after_init no_override = { };
377 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
378 .name = "SYS_CTR_EL0",
380 .override = &no_override,
383 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
384 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf),
385 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0),
386 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0),
387 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0),
388 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0),
389 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf),
390 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0),
391 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0),
395 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
396 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_DOUBLELOCK_SHIFT, 4, 0),
397 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
398 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
399 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
400 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
402 * We can instantiate multiple PMU instances with different levels
405 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
406 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
410 static const struct arm64_ftr_bits ftr_mvfr2[] = {
411 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0),
412 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0),
416 static const struct arm64_ftr_bits ftr_dczid[] = {
417 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1),
418 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0),
422 static const struct arm64_ftr_bits ftr_gmid[] = {
423 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, SYS_GMID_EL1_BS_SHIFT, 4, 0),
427 static const struct arm64_ftr_bits ftr_id_isar0[] = {
428 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),
429 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),
430 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0),
431 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0),
432 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0),
433 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0),
434 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0),
438 static const struct arm64_ftr_bits ftr_id_isar5[] = {
439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
440 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
441 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
442 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
448 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
449 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0),
450 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0),
451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0),
452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0),
453 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0),
454 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0),
455 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0),
458 * SpecSEI = 1 indicates that the PE might generate an SError on an
459 * external abort on speculative read. It is safe to assume that an
460 * SError might be generated than it will not be. Hence it has been
461 * classified as FTR_HIGHER_SAFE.
463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0),
467 static const struct arm64_ftr_bits ftr_id_isar4[] = {
468 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0),
469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0),
470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0),
471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0),
472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0),
473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0),
474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0),
475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0),
479 static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
480 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0),
484 static const struct arm64_ftr_bits ftr_id_isar6[] = {
485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),
486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),
488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),
490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0),
491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0),
495 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
496 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0),
497 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0),
498 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0),
499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0),
500 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0),
501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0),
505 static const struct arm64_ftr_bits ftr_id_pfr1[] = {
506 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0),
507 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0),
508 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0),
509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0),
510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0),
511 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0),
512 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0),
513 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0),
517 static const struct arm64_ftr_bits ftr_id_pfr2[] = {
518 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0),
519 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0),
523 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
524 /* [31:28] TraceFilt */
525 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_PERFMON_SHIFT, 4, 0xf),
526 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0),
527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0),
528 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0),
529 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0),
530 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0),
531 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0),
535 static const struct arm64_ftr_bits ftr_id_dfr1[] = {
536 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0),
540 static const struct arm64_ftr_bits ftr_zcr[] = {
541 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
542 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */
547 * Common ftr bits for a 32bit register with all hidden, strict
548 * attributes, with 4bit feature fields and a default safe value of
549 * 0. Covers the following 32bit registers:
550 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
552 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
553 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
554 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
555 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
556 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
557 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
558 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
559 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
560 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
564 /* Table for a single 32bit feature value */
565 static const struct arm64_ftr_bits ftr_single32[] = {
566 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
570 static const struct arm64_ftr_bits ftr_raz[] = {
574 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) { \
576 .reg = &(struct arm64_ftr_reg){ \
579 .ftr_bits = &((table)[0]), \
582 #define ARM64_FTR_REG(id, table) ARM64_FTR_REG_OVERRIDE(id, table, &no_override)
584 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override;
585 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override;
586 struct arm64_ftr_override __ro_after_init id_aa64isar1_override;
588 static const struct __ftr_reg_entry {
590 struct arm64_ftr_reg *reg;
591 } arm64_ftr_regs[] = {
593 /* Op1 = 0, CRn = 0, CRm = 1 */
594 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
595 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1),
596 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
597 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
598 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
599 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
600 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
602 /* Op1 = 0, CRn = 0, CRm = 2 */
603 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0),
604 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
605 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
606 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
607 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4),
608 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
609 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
610 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
612 /* Op1 = 0, CRn = 0, CRm = 3 */
613 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
614 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
615 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
616 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
617 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),
618 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5),
620 /* Op1 = 0, CRn = 0, CRm = 4 */
621 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
622 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1,
623 &id_aa64pfr1_override),
624 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
626 /* Op1 = 0, CRn = 0, CRm = 5 */
627 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
628 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
630 /* Op1 = 0, CRn = 0, CRm = 6 */
631 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
632 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1,
633 &id_aa64isar1_override),
635 /* Op1 = 0, CRn = 0, CRm = 7 */
636 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
637 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1,
638 &id_aa64mmfr1_override),
639 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
641 /* Op1 = 0, CRn = 1, CRm = 2 */
642 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
644 /* Op1 = 1, CRn = 0, CRm = 0 */
645 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid),
647 /* Op1 = 3, CRn = 0, CRm = 0 */
648 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
649 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
651 /* Op1 = 3, CRn = 14, CRm = 0 */
652 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
655 static int search_cmp_ftr_reg(const void *id, const void *regp)
657 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
661 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using
662 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the
663 * ascending order of sys_id, we use binary search to find a matching
666 * returns - Upon success, matching ftr_reg entry for id.
667 * - NULL on failure. It is upto the caller to decide
668 * the impact of a failure.
670 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id)
672 const struct __ftr_reg_entry *ret;
674 ret = bsearch((const void *)(unsigned long)sys_id,
676 ARRAY_SIZE(arm64_ftr_regs),
677 sizeof(arm64_ftr_regs[0]),
685 * get_arm64_ftr_reg - Looks up a feature register entry using
686 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn().
688 * returns - Upon success, matching ftr_reg entry for id.
689 * - NULL on failure but with an WARN_ON().
691 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
693 struct arm64_ftr_reg *reg;
695 reg = get_arm64_ftr_reg_nowarn(sys_id);
698 * Requesting a non-existent register search is an error. Warn
699 * and let the caller handle it.
705 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
708 u64 mask = arm64_ftr_mask(ftrp);
711 reg |= (ftr_val << ftrp->shift) & mask;
715 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
720 switch (ftrp->type) {
722 ret = ftrp->safe_val;
727 case FTR_HIGHER_OR_ZERO_SAFE:
731 case FTR_HIGHER_SAFE:
741 static void __init sort_ftr_regs(void)
745 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) {
746 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg;
747 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits;
751 * Features here must be sorted in descending order with respect
752 * to their shift values and should not overlap with each other.
754 for (; ftr_bits->width != 0; ftr_bits++, j++) {
755 unsigned int width = ftr_reg->ftr_bits[j].width;
756 unsigned int shift = ftr_reg->ftr_bits[j].shift;
757 unsigned int prev_shift;
759 WARN((shift + width) > 64,
760 "%s has invalid feature at shift %d\n",
761 ftr_reg->name, shift);
764 * Skip the first feature. There is nothing to
765 * compare against for now.
770 prev_shift = ftr_reg->ftr_bits[j - 1].shift;
771 WARN((shift + width) > prev_shift,
772 "%s has feature overlap at shift %d\n",
773 ftr_reg->name, shift);
777 * Skip the first register. There is nothing to
778 * compare against for now.
783 * Registers here must be sorted in ascending order with respect
784 * to sys_id for subsequent binary search in get_arm64_ftr_reg()
787 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
792 * Initialise the CPU feature register from Boot CPU values.
793 * Also initiliases the strict_mask for the register.
794 * Any bits that are not covered by an arm64_ftr_bits entry are considered
795 * RES0 for the system-wide value, and must strictly match.
797 static void init_cpu_ftr_reg(u32 sys_reg, u64 new)
800 u64 strict_mask = ~0x0ULL;
804 const struct arm64_ftr_bits *ftrp;
805 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
810 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
811 u64 ftr_mask = arm64_ftr_mask(ftrp);
812 s64 ftr_new = arm64_ftr_value(ftrp, new);
813 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val);
815 if ((ftr_mask & reg->override->mask) == ftr_mask) {
816 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new);
819 if (ftr_ovr != tmp) {
820 /* Unsafe, remove the override */
821 reg->override->mask &= ~ftr_mask;
822 reg->override->val &= ~ftr_mask;
824 str = "ignoring override";
825 } else if (ftr_new != tmp) {
826 /* Override was valid */
829 } else if (ftr_ovr == tmp) {
830 /* Override was the safe value */
835 pr_warn("%s[%d:%d]: %s to %llx\n",
837 ftrp->shift + ftrp->width - 1,
838 ftrp->shift, str, tmp);
839 } else if ((ftr_mask & reg->override->val) == ftr_mask) {
840 reg->override->val &= ~ftr_mask;
841 pr_warn("%s[%d:%d]: impossible override, ignored\n",
843 ftrp->shift + ftrp->width - 1,
847 val = arm64_ftr_set_value(ftrp, val, ftr_new);
849 valid_mask |= ftr_mask;
851 strict_mask &= ~ftr_mask;
853 user_mask |= ftr_mask;
855 reg->user_val = arm64_ftr_set_value(ftrp,
863 reg->strict_mask = strict_mask;
864 reg->user_mask = user_mask;
867 extern const struct arm64_cpu_capabilities arm64_errata[];
868 static const struct arm64_cpu_capabilities arm64_features[];
871 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
873 for (; caps->matches; caps++) {
874 if (WARN(caps->capability >= ARM64_NCAPS,
875 "Invalid capability %d\n", caps->capability))
877 if (WARN(cpu_hwcaps_ptrs[caps->capability],
878 "Duplicate entry for capability %d\n",
881 cpu_hwcaps_ptrs[caps->capability] = caps;
885 static void __init init_cpu_hwcaps_indirect_list(void)
887 init_cpu_hwcaps_indirect_list_from_array(arm64_features);
888 init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
891 static void __init setup_boot_cpu_capabilities(void);
893 static void init_32bit_cpu_features(struct cpuinfo_32bit *info)
895 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
896 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1);
897 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
898 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
899 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
900 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
901 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
902 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
903 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6);
904 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
905 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
906 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
907 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
908 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4);
909 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5);
910 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
911 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
912 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2);
913 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
914 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
915 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
918 void __init init_cpu_features(struct cpuinfo_arm64 *info)
920 /* Before we start using the tables, make sure it is sorted */
923 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
924 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
925 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
926 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
927 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
928 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
929 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
930 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
931 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
932 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
933 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
934 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
935 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
937 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
938 init_32bit_cpu_features(&info->aarch32);
940 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
941 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
945 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
946 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid);
949 * Initialize the indirect array of CPU hwcaps capabilities pointers
950 * before we handle the boot CPU below.
952 init_cpu_hwcaps_indirect_list();
955 * Detect and enable early CPU capabilities based on the boot CPU,
956 * after we have initialised the CPU feature infrastructure.
958 setup_boot_cpu_capabilities();
961 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
963 const struct arm64_ftr_bits *ftrp;
965 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
966 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
967 s64 ftr_new = arm64_ftr_value(ftrp, new);
969 if (ftr_cur == ftr_new)
971 /* Find a safe value */
972 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
973 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
978 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
980 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
985 update_cpu_ftr_reg(regp, val);
986 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
988 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
989 regp->name, boot, cpu, val);
993 static void relax_cpu_ftr_reg(u32 sys_id, int field)
995 const struct arm64_ftr_bits *ftrp;
996 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
1001 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) {
1002 if (ftrp->shift == field) {
1003 regp->strict_mask &= ~arm64_ftr_mask(ftrp);
1009 WARN_ON(!ftrp->width);
1012 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info,
1013 struct cpuinfo_arm64 *boot)
1015 static bool boot_cpu_32bit_regs_overridden = false;
1017 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden)
1020 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0))
1023 boot->aarch32 = info->aarch32;
1024 init_32bit_cpu_features(&boot->aarch32);
1025 boot_cpu_32bit_regs_overridden = true;
1028 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info,
1029 struct cpuinfo_32bit *boot)
1032 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1035 * If we don't have AArch32 at EL1, then relax the strictness of
1036 * EL1-dependent register fields to avoid spurious sanity check fails.
1038 if (!id_aa64pfr0_32bit_el1(pfr0)) {
1039 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT);
1040 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT);
1041 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT);
1042 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT);
1043 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT);
1044 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT);
1047 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
1048 info->reg_id_dfr0, boot->reg_id_dfr0);
1049 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu,
1050 info->reg_id_dfr1, boot->reg_id_dfr1);
1051 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
1052 info->reg_id_isar0, boot->reg_id_isar0);
1053 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
1054 info->reg_id_isar1, boot->reg_id_isar1);
1055 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
1056 info->reg_id_isar2, boot->reg_id_isar2);
1057 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
1058 info->reg_id_isar3, boot->reg_id_isar3);
1059 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
1060 info->reg_id_isar4, boot->reg_id_isar4);
1061 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
1062 info->reg_id_isar5, boot->reg_id_isar5);
1063 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu,
1064 info->reg_id_isar6, boot->reg_id_isar6);
1067 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
1068 * ACTLR formats could differ across CPUs and therefore would have to
1069 * be trapped for virtualization anyway.
1071 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
1072 info->reg_id_mmfr0, boot->reg_id_mmfr0);
1073 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
1074 info->reg_id_mmfr1, boot->reg_id_mmfr1);
1075 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
1076 info->reg_id_mmfr2, boot->reg_id_mmfr2);
1077 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
1078 info->reg_id_mmfr3, boot->reg_id_mmfr3);
1079 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu,
1080 info->reg_id_mmfr4, boot->reg_id_mmfr4);
1081 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu,
1082 info->reg_id_mmfr5, boot->reg_id_mmfr5);
1083 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
1084 info->reg_id_pfr0, boot->reg_id_pfr0);
1085 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
1086 info->reg_id_pfr1, boot->reg_id_pfr1);
1087 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu,
1088 info->reg_id_pfr2, boot->reg_id_pfr2);
1089 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
1090 info->reg_mvfr0, boot->reg_mvfr0);
1091 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
1092 info->reg_mvfr1, boot->reg_mvfr1);
1093 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
1094 info->reg_mvfr2, boot->reg_mvfr2);
1100 * Update system wide CPU feature registers with the values from a
1101 * non-boot CPU. Also performs SANITY checks to make sure that there
1102 * aren't any insane variations from that of the boot CPU.
1104 void update_cpu_features(int cpu,
1105 struct cpuinfo_arm64 *info,
1106 struct cpuinfo_arm64 *boot)
1111 * The kernel can handle differing I-cache policies, but otherwise
1112 * caches should look identical. Userspace JITs will make use of
1115 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
1116 info->reg_ctr, boot->reg_ctr);
1119 * Userspace may perform DC ZVA instructions. Mismatched block sizes
1120 * could result in too much or too little memory being zeroed if a
1121 * process is preempted and migrated between CPUs.
1123 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
1124 info->reg_dczid, boot->reg_dczid);
1126 /* If different, timekeeping will be broken (especially with KVM) */
1127 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
1128 info->reg_cntfrq, boot->reg_cntfrq);
1131 * The kernel uses self-hosted debug features and expects CPUs to
1132 * support identical debug features. We presently need CTX_CMPs, WRPs,
1133 * and BRPs to be identical.
1134 * ID_AA64DFR1 is currently RES0.
1136 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
1137 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
1138 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
1139 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
1141 * Even in big.LITTLE, processors should be identical instruction-set
1144 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
1145 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
1146 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
1147 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
1150 * Differing PARange support is fine as long as all peripherals and
1151 * memory are mapped within the minimum PARange of all CPUs.
1152 * Linux should not care about secure memory.
1154 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
1155 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
1156 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
1157 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
1158 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
1159 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
1161 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
1162 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
1163 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
1164 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
1166 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
1167 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
1169 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
1170 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
1171 info->reg_zcr, boot->reg_zcr);
1173 /* Probe vector lengths, unless we already gave up on SVE */
1174 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
1175 !system_capabilities_finalized())
1176 sve_update_vq_map();
1180 * The kernel uses the LDGM/STGM instructions and the number of tags
1181 * they read/write depends on the GMID_EL1.BS field. Check that the
1182 * value is the same on all CPUs.
1184 if (IS_ENABLED(CONFIG_ARM64_MTE) &&
1185 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) {
1186 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu,
1187 info->reg_gmid, boot->reg_gmid);
1191 * If we don't have AArch32 at all then skip the checks entirely
1192 * as the register values may be UNKNOWN and we're not going to be
1193 * using them for anything.
1195 * This relies on a sanitised view of the AArch64 ID registers
1196 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last.
1198 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
1199 lazy_init_32bit_cpu_features(info, boot);
1200 taint |= update_32bit_cpu_features(cpu, &info->aarch32,
1205 * Mismatched CPU features are a recipe for disaster. Don't even
1206 * pretend to support them.
1209 pr_warn_once("Unsupported CPU feature variation detected.\n");
1210 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1214 u64 read_sanitised_ftr_reg(u32 id)
1216 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
1220 return regp->sys_val;
1222 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg);
1224 #define read_sysreg_case(r) \
1225 case r: val = read_sysreg_s(r); break;
1228 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
1229 * Read the system register on the current CPU
1231 u64 __read_sysreg_by_encoding(u32 sys_id)
1233 struct arm64_ftr_reg *regp;
1237 read_sysreg_case(SYS_ID_PFR0_EL1);
1238 read_sysreg_case(SYS_ID_PFR1_EL1);
1239 read_sysreg_case(SYS_ID_PFR2_EL1);
1240 read_sysreg_case(SYS_ID_DFR0_EL1);
1241 read_sysreg_case(SYS_ID_DFR1_EL1);
1242 read_sysreg_case(SYS_ID_MMFR0_EL1);
1243 read_sysreg_case(SYS_ID_MMFR1_EL1);
1244 read_sysreg_case(SYS_ID_MMFR2_EL1);
1245 read_sysreg_case(SYS_ID_MMFR3_EL1);
1246 read_sysreg_case(SYS_ID_MMFR4_EL1);
1247 read_sysreg_case(SYS_ID_MMFR5_EL1);
1248 read_sysreg_case(SYS_ID_ISAR0_EL1);
1249 read_sysreg_case(SYS_ID_ISAR1_EL1);
1250 read_sysreg_case(SYS_ID_ISAR2_EL1);
1251 read_sysreg_case(SYS_ID_ISAR3_EL1);
1252 read_sysreg_case(SYS_ID_ISAR4_EL1);
1253 read_sysreg_case(SYS_ID_ISAR5_EL1);
1254 read_sysreg_case(SYS_ID_ISAR6_EL1);
1255 read_sysreg_case(SYS_MVFR0_EL1);
1256 read_sysreg_case(SYS_MVFR1_EL1);
1257 read_sysreg_case(SYS_MVFR2_EL1);
1259 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
1260 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
1261 read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
1262 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
1263 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
1264 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
1265 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
1266 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
1267 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
1268 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
1270 read_sysreg_case(SYS_CNTFRQ_EL0);
1271 read_sysreg_case(SYS_CTR_EL0);
1272 read_sysreg_case(SYS_DCZID_EL0);
1279 regp = get_arm64_ftr_reg(sys_id);
1281 val &= ~regp->override->mask;
1282 val |= (regp->override->val & regp->override->mask);
1288 #include <linux/irqchip/arm-gic-v3.h>
1291 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
1293 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
1295 return val >= entry->min_field_value;
1299 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
1303 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1304 if (scope == SCOPE_SYSTEM)
1305 val = read_sanitised_ftr_reg(entry->sys_reg);
1307 val = __read_sysreg_by_encoding(entry->sys_reg);
1309 return feature_matches(val, entry);
1312 const struct cpumask *system_32bit_el0_cpumask(void)
1314 if (!system_supports_32bit_el0())
1315 return cpu_none_mask;
1317 if (static_branch_unlikely(&arm64_mismatched_32bit_el0))
1318 return cpu_32bit_el0_mask;
1320 return cpu_possible_mask;
1323 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope)
1325 if (!has_cpuid_feature(entry, scope))
1326 return allow_mismatched_32bit_el0;
1328 if (scope == SCOPE_SYSTEM)
1329 pr_info("detected: 32-bit EL0 Support\n");
1334 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
1338 if (!has_cpuid_feature(entry, scope))
1341 has_sre = gic_enable_sre();
1343 pr_warn_once("%s present but disabled by higher exception level\n",
1349 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
1351 u32 midr = read_cpuid_id();
1353 /* Cavium ThunderX pass 1.x and 2.x */
1354 return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
1355 MIDR_CPU_VAR_REV(0, 0),
1356 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
1359 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
1361 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1363 return cpuid_feature_extract_signed_field(pfr0,
1364 ID_AA64PFR0_FP_SHIFT) < 0;
1367 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
1372 if (scope == SCOPE_SYSTEM)
1373 ctr = arm64_ftr_reg_ctrel0.sys_val;
1375 ctr = read_cpuid_effective_cachetype();
1377 return ctr & BIT(CTR_IDC_SHIFT);
1380 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
1383 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
1384 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
1385 * to the CTR_EL0 on this CPU and emulate it with the real/safe
1388 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
1389 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
1392 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
1397 if (scope == SCOPE_SYSTEM)
1398 ctr = arm64_ftr_reg_ctrel0.sys_val;
1400 ctr = read_cpuid_cachetype();
1402 return ctr & BIT(CTR_DIC_SHIFT);
1405 static bool __maybe_unused
1406 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
1409 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
1410 * may share TLB entries with a CPU stuck in the crashed
1413 if (is_kdump_kernel())
1416 if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP))
1419 return has_cpuid_feature(entry, scope);
1423 * This check is triggered during the early boot before the cpufeature
1424 * is initialised. Checking the status on the local CPU allows the boot
1425 * CPU to detect the need for non-global mappings and thus avoiding a
1426 * pagetable re-write after all the CPUs are booted. This check will be
1427 * anyway run on individual CPUs, allowing us to get the consistent
1428 * state once the SMP CPUs are up and thus make the switch to non-global
1429 * mappings if required.
1431 bool kaslr_requires_kpti(void)
1433 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE))
1437 * E0PD does a similar job to KPTI so can be used instead
1440 if (IS_ENABLED(CONFIG_ARM64_E0PD)) {
1441 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1);
1442 if (cpuid_feature_extract_unsigned_field(mmfr2,
1443 ID_AA64MMFR2_E0PD_SHIFT))
1448 * Systems affected by Cavium erratum 24756 are incompatible
1451 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) {
1452 extern const struct midr_range cavium_erratum_27456_cpus[];
1454 if (is_midr_in_range_list(read_cpuid_id(),
1455 cavium_erratum_27456_cpus))
1459 return kaslr_offset() > 0;
1462 static bool __meltdown_safe = true;
1463 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
1465 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
1468 /* List of CPUs that are not vulnerable and don't need KPTI */
1469 static const struct midr_range kpti_safe_list[] = {
1470 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
1471 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
1472 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
1473 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
1474 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
1475 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1476 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
1477 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
1478 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
1479 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
1480 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
1481 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD),
1482 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER),
1483 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
1484 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
1487 char const *str = "kpti command line option";
1490 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
1492 /* Defer to CPU feature registers */
1493 if (has_cpuid_feature(entry, scope))
1494 meltdown_safe = true;
1497 __meltdown_safe = false;
1500 * For reasons that aren't entirely clear, enabling KPTI on Cavium
1501 * ThunderX leads to apparent I-cache corruption of kernel text, which
1502 * ends as well as you might imagine. Don't even try.
1504 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1505 str = "ARM64_WORKAROUND_CAVIUM_27456";
1509 /* Useful for KASLR robustness */
1510 if (kaslr_requires_kpti()) {
1511 if (!__kpti_forced) {
1517 if (cpu_mitigations_off() && !__kpti_forced) {
1518 str = "mitigations=off";
1522 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1523 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1528 if (__kpti_forced) {
1529 pr_info_once("kernel page table isolation forced %s by %s\n",
1530 __kpti_forced > 0 ? "ON" : "OFF", str);
1531 return __kpti_forced > 0;
1534 return !meltdown_safe;
1537 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1539 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1541 typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1542 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1543 kpti_remap_fn *remap_fn;
1545 int cpu = smp_processor_id();
1548 * We don't need to rewrite the page-tables if either we've done
1549 * it already or we have KASLR enabled and therefore have not
1550 * created any global mappings at all.
1552 if (arm64_use_ng_mappings)
1555 remap_fn = (void *)__pa_symbol(function_nocfi(idmap_kpti_install_ng_mappings));
1557 cpu_install_idmap();
1558 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1559 cpu_uninstall_idmap();
1562 arm64_use_ng_mappings = true;
1568 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1571 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1573 static int __init parse_kpti(char *str)
1576 int ret = strtobool(str, &enabled);
1581 __kpti_forced = enabled ? 1 : -1;
1584 early_param("kpti", parse_kpti);
1586 #ifdef CONFIG_ARM64_HW_AFDBM
1587 static inline void __cpu_enable_hw_dbm(void)
1589 u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1591 write_sysreg(tcr, tcr_el1);
1593 local_flush_tlb_all();
1596 static bool cpu_has_broken_dbm(void)
1598 /* List of CPUs which have broken DBM support. */
1599 static const struct midr_range cpus[] = {
1600 #ifdef CONFIG_ARM64_ERRATUM_1024718
1601 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1602 /* Kryo4xx Silver (rdpe => r1p0) */
1603 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
1608 return is_midr_in_range_list(read_cpuid_id(), cpus);
1611 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1613 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1614 !cpu_has_broken_dbm();
1617 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1619 if (cpu_can_use_dbm(cap))
1620 __cpu_enable_hw_dbm();
1623 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1626 static bool detected = false;
1628 * DBM is a non-conflicting feature. i.e, the kernel can safely
1629 * run a mix of CPUs with and without the feature. So, we
1630 * unconditionally enable the capability to allow any late CPU
1631 * to use the feature. We only enable the control bits on the
1632 * CPU, if it actually supports.
1634 * We have to make sure we print the "feature" detection only
1635 * when at least one CPU actually uses it. So check if this CPU
1636 * can actually use it and print the message exactly once.
1638 * This is safe as all CPUs (including secondary CPUs - due to the
1639 * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1640 * goes through the "matches" check exactly once. Also if a CPU
1641 * matches the criteria, it is guaranteed that the CPU will turn
1642 * the DBM on, as the capability is unconditionally enabled.
1644 if (!detected && cpu_can_use_dbm(cap)) {
1646 pr_info("detected: Hardware dirty bit management\n");
1654 #ifdef CONFIG_ARM64_AMU_EXTN
1657 * The "amu_cpus" cpumask only signals that the CPU implementation for the
1658 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide
1659 * information regarding all the events that it supports. When a CPU bit is
1660 * set in the cpumask, the user of this feature can only rely on the presence
1661 * of the 4 fixed counters for that CPU. But this does not guarantee that the
1662 * counters are enabled or access to these counters is enabled by code
1663 * executed at higher exception levels (firmware).
1665 static struct cpumask amu_cpus __read_mostly;
1667 bool cpu_has_amu_feat(int cpu)
1669 return cpumask_test_cpu(cpu, &amu_cpus);
1672 int get_cpu_with_amu_feat(void)
1674 return cpumask_any(&amu_cpus);
1677 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
1679 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) {
1680 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n",
1681 smp_processor_id());
1682 cpumask_set_cpu(smp_processor_id(), &amu_cpus);
1683 update_freq_counters_refs();
1687 static bool has_amu(const struct arm64_cpu_capabilities *cap,
1691 * The AMU extension is a non-conflicting feature: the kernel can
1692 * safely run a mix of CPUs with and without support for the
1693 * activity monitors extension. Therefore, unconditionally enable
1694 * the capability to allow any late CPU to use the feature.
1696 * With this feature unconditionally enabled, the cpu_enable
1697 * function will be called for all CPUs that match the criteria,
1698 * including secondary and hotplugged, marking this feature as
1699 * present on that respective CPU. The enable function will also
1700 * print a detection message.
1706 int get_cpu_with_amu_feat(void)
1712 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1714 return is_kernel_in_hyp_mode();
1717 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1720 * Copy register values that aren't redirected by hardware.
1722 * Before code patching, we only set tpidr_el1, all CPUs need to copy
1723 * this value to tpidr_el2 before we patch the code. Once we've done
1724 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1727 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1728 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1731 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1733 u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1735 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1736 WARN_ON(val & (7 << 27 | 7 << 21));
1739 #ifdef CONFIG_ARM64_PAN
1740 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1743 * We modify PSTATE. This won't work from irq context as the PSTATE
1744 * is discarded once we return from the exception.
1746 WARN_ON_ONCE(in_interrupt());
1748 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1751 #endif /* CONFIG_ARM64_PAN */
1753 #ifdef CONFIG_ARM64_RAS_EXTN
1754 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1756 /* Firmware may have left a deferred SError in this register. */
1757 write_sysreg_s(0, SYS_DISR_EL1);
1759 #endif /* CONFIG_ARM64_RAS_EXTN */
1761 #ifdef CONFIG_ARM64_PTR_AUTH
1762 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope)
1764 int boot_val, sec_val;
1766 /* We don't expect to be called with SCOPE_SYSTEM */
1767 WARN_ON(scope == SCOPE_SYSTEM);
1769 * The ptr-auth feature levels are not intercompatible with lower
1770 * levels. Hence we must match ptr-auth feature level of the secondary
1771 * CPUs with that of the boot CPU. The level of boot cpu is fetched
1772 * from the sanitised register whereas direct register read is done for
1773 * the secondary CPUs.
1774 * The sanitised feature state is guaranteed to match that of the
1775 * boot CPU as a mismatched secondary CPU is parked before it gets
1776 * a chance to update the state, with the capability.
1778 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg),
1779 entry->field_pos, entry->sign);
1780 if (scope & SCOPE_BOOT_CPU)
1781 return boot_val >= entry->min_field_value;
1782 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */
1783 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg),
1784 entry->field_pos, entry->sign);
1785 return sec_val == boot_val;
1788 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry,
1791 return has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH], scope) ||
1792 has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope);
1795 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,
1798 return __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH) ||
1799 __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF);
1801 #endif /* CONFIG_ARM64_PTR_AUTH */
1803 #ifdef CONFIG_ARM64_E0PD
1804 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
1806 if (this_cpu_has_cap(ARM64_HAS_E0PD))
1807 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
1809 #endif /* CONFIG_ARM64_E0PD */
1811 #ifdef CONFIG_ARM64_PSEUDO_NMI
1812 static bool enable_pseudo_nmi;
1814 static int __init early_enable_pseudo_nmi(char *p)
1816 return strtobool(p, &enable_pseudo_nmi);
1818 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1820 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1823 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
1827 #ifdef CONFIG_ARM64_BTI
1828 static void bti_enable(const struct arm64_cpu_capabilities *__unused)
1831 * Use of X16/X17 for tail-calls and trampolines that jump to
1832 * function entry points using BR is a requirement for
1833 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI.
1834 * So, be strict and forbid other BRs using other registers to
1835 * jump onto a PACIxSP instruction:
1837 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1);
1840 #endif /* CONFIG_ARM64_BTI */
1842 #ifdef CONFIG_ARM64_MTE
1843 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap)
1846 * Clear the tags in the zero page. This needs to be done via the
1847 * linear map which has the Tagged attribute.
1849 if (!test_and_set_bit(PG_mte_tagged, &ZERO_PAGE(0)->flags))
1850 mte_clear_page_tags(lm_alias(empty_zero_page));
1852 kasan_init_hw_tags_cpu();
1854 #endif /* CONFIG_ARM64_MTE */
1857 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused)
1859 if (kvm_get_mode() != KVM_MODE_PROTECTED)
1862 if (is_kernel_in_hyp_mode()) {
1863 pr_warn("Protected KVM not available with VHE\n");
1869 #endif /* CONFIG_KVM */
1871 /* Internal helper functions to match cpu capability type */
1873 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
1875 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);
1879 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap)
1881 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);
1885 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap)
1887 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT);
1890 static const struct arm64_cpu_capabilities arm64_features[] = {
1892 .desc = "GIC system register CPU interface",
1893 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1894 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1895 .matches = has_useable_gicv3_cpuif,
1896 .sys_reg = SYS_ID_AA64PFR0_EL1,
1897 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1898 .sign = FTR_UNSIGNED,
1899 .min_field_value = 1,
1901 #ifdef CONFIG_ARM64_PAN
1903 .desc = "Privileged Access Never",
1904 .capability = ARM64_HAS_PAN,
1905 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1906 .matches = has_cpuid_feature,
1907 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1908 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1909 .sign = FTR_UNSIGNED,
1910 .min_field_value = 1,
1911 .cpu_enable = cpu_enable_pan,
1913 #endif /* CONFIG_ARM64_PAN */
1914 #ifdef CONFIG_ARM64_EPAN
1916 .desc = "Enhanced Privileged Access Never",
1917 .capability = ARM64_HAS_EPAN,
1918 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1919 .matches = has_cpuid_feature,
1920 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1921 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1922 .sign = FTR_UNSIGNED,
1923 .min_field_value = 3,
1925 #endif /* CONFIG_ARM64_EPAN */
1926 #ifdef CONFIG_ARM64_LSE_ATOMICS
1928 .desc = "LSE atomic instructions",
1929 .capability = ARM64_HAS_LSE_ATOMICS,
1930 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1931 .matches = has_cpuid_feature,
1932 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1933 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1934 .sign = FTR_UNSIGNED,
1935 .min_field_value = 2,
1937 #endif /* CONFIG_ARM64_LSE_ATOMICS */
1939 .desc = "Software prefetching using PRFM",
1940 .capability = ARM64_HAS_NO_HW_PREFETCH,
1941 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1942 .matches = has_no_hw_prefetch,
1945 .desc = "Virtualization Host Extensions",
1946 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1947 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1948 .matches = runs_at_el2,
1949 .cpu_enable = cpu_copy_el2regs,
1952 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE,
1953 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1954 .matches = has_32bit_el0,
1955 .sys_reg = SYS_ID_AA64PFR0_EL1,
1956 .sign = FTR_UNSIGNED,
1957 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1958 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1962 .desc = "32-bit EL1 Support",
1963 .capability = ARM64_HAS_32BIT_EL1,
1964 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1965 .matches = has_cpuid_feature,
1966 .sys_reg = SYS_ID_AA64PFR0_EL1,
1967 .sign = FTR_UNSIGNED,
1968 .field_pos = ID_AA64PFR0_EL1_SHIFT,
1969 .min_field_value = ID_AA64PFR0_EL1_32BIT_64BIT,
1972 .desc = "Protected KVM",
1973 .capability = ARM64_KVM_PROTECTED_MODE,
1974 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1975 .matches = is_kvm_protected_mode,
1979 .desc = "Kernel page table isolation (KPTI)",
1980 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1981 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1983 * The ID feature fields below are used to indicate that
1984 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1987 .sys_reg = SYS_ID_AA64PFR0_EL1,
1988 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1989 .min_field_value = 1,
1990 .matches = unmap_kernel_at_el0,
1991 .cpu_enable = kpti_install_ng_mappings,
1994 /* FP/SIMD is not implemented */
1995 .capability = ARM64_HAS_NO_FPSIMD,
1996 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1997 .min_field_value = 0,
1998 .matches = has_no_fpsimd,
2000 #ifdef CONFIG_ARM64_PMEM
2002 .desc = "Data cache clean to Point of Persistence",
2003 .capability = ARM64_HAS_DCPOP,
2004 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2005 .matches = has_cpuid_feature,
2006 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2007 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
2008 .min_field_value = 1,
2011 .desc = "Data cache clean to Point of Deep Persistence",
2012 .capability = ARM64_HAS_DCPODP,
2013 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2014 .matches = has_cpuid_feature,
2015 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2016 .sign = FTR_UNSIGNED,
2017 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
2018 .min_field_value = 2,
2021 #ifdef CONFIG_ARM64_SVE
2023 .desc = "Scalable Vector Extension",
2024 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2025 .capability = ARM64_SVE,
2026 .sys_reg = SYS_ID_AA64PFR0_EL1,
2027 .sign = FTR_UNSIGNED,
2028 .field_pos = ID_AA64PFR0_SVE_SHIFT,
2029 .min_field_value = ID_AA64PFR0_SVE,
2030 .matches = has_cpuid_feature,
2031 .cpu_enable = sve_kernel_enable,
2033 #endif /* CONFIG_ARM64_SVE */
2034 #ifdef CONFIG_ARM64_RAS_EXTN
2036 .desc = "RAS Extension Support",
2037 .capability = ARM64_HAS_RAS_EXTN,
2038 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2039 .matches = has_cpuid_feature,
2040 .sys_reg = SYS_ID_AA64PFR0_EL1,
2041 .sign = FTR_UNSIGNED,
2042 .field_pos = ID_AA64PFR0_RAS_SHIFT,
2043 .min_field_value = ID_AA64PFR0_RAS_V1,
2044 .cpu_enable = cpu_clear_disr,
2046 #endif /* CONFIG_ARM64_RAS_EXTN */
2047 #ifdef CONFIG_ARM64_AMU_EXTN
2050 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y.
2051 * Therefore, don't provide .desc as we don't want the detection
2052 * message to be shown until at least one CPU is detected to
2053 * support the feature.
2055 .capability = ARM64_HAS_AMU_EXTN,
2056 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2058 .sys_reg = SYS_ID_AA64PFR0_EL1,
2059 .sign = FTR_UNSIGNED,
2060 .field_pos = ID_AA64PFR0_AMU_SHIFT,
2061 .min_field_value = ID_AA64PFR0_AMU,
2062 .cpu_enable = cpu_amu_enable,
2064 #endif /* CONFIG_ARM64_AMU_EXTN */
2066 .desc = "Data cache clean to the PoU not required for I/D coherence",
2067 .capability = ARM64_HAS_CACHE_IDC,
2068 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2069 .matches = has_cache_idc,
2070 .cpu_enable = cpu_emulate_effective_ctr,
2073 .desc = "Instruction cache invalidation not required for I/D coherence",
2074 .capability = ARM64_HAS_CACHE_DIC,
2075 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2076 .matches = has_cache_dic,
2079 .desc = "Stage-2 Force Write-Back",
2080 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2081 .capability = ARM64_HAS_STAGE2_FWB,
2082 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2083 .sign = FTR_UNSIGNED,
2084 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
2085 .min_field_value = 1,
2086 .matches = has_cpuid_feature,
2087 .cpu_enable = cpu_has_fwb,
2090 .desc = "ARMv8.4 Translation Table Level",
2091 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2092 .capability = ARM64_HAS_ARMv8_4_TTL,
2093 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2094 .sign = FTR_UNSIGNED,
2095 .field_pos = ID_AA64MMFR2_TTL_SHIFT,
2096 .min_field_value = 1,
2097 .matches = has_cpuid_feature,
2100 .desc = "TLB range maintenance instructions",
2101 .capability = ARM64_HAS_TLB_RANGE,
2102 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2103 .matches = has_cpuid_feature,
2104 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2105 .field_pos = ID_AA64ISAR0_TLB_SHIFT,
2106 .sign = FTR_UNSIGNED,
2107 .min_field_value = ID_AA64ISAR0_TLB_RANGE,
2109 #ifdef CONFIG_ARM64_HW_AFDBM
2112 * Since we turn this on always, we don't want the user to
2113 * think that the feature is available when it may not be.
2114 * So hide the description.
2116 * .desc = "Hardware pagetable Dirty Bit Management",
2119 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2120 .capability = ARM64_HW_DBM,
2121 .sys_reg = SYS_ID_AA64MMFR1_EL1,
2122 .sign = FTR_UNSIGNED,
2123 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
2124 .min_field_value = 2,
2125 .matches = has_hw_dbm,
2126 .cpu_enable = cpu_enable_hw_dbm,
2130 .desc = "CRC32 instructions",
2131 .capability = ARM64_HAS_CRC32,
2132 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2133 .matches = has_cpuid_feature,
2134 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2135 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
2136 .min_field_value = 1,
2139 .desc = "Speculative Store Bypassing Safe (SSBS)",
2140 .capability = ARM64_SSBS,
2141 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2142 .matches = has_cpuid_feature,
2143 .sys_reg = SYS_ID_AA64PFR1_EL1,
2144 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
2145 .sign = FTR_UNSIGNED,
2146 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
2148 #ifdef CONFIG_ARM64_CNP
2150 .desc = "Common not Private translations",
2151 .capability = ARM64_HAS_CNP,
2152 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2153 .matches = has_useable_cnp,
2154 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2155 .sign = FTR_UNSIGNED,
2156 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
2157 .min_field_value = 1,
2158 .cpu_enable = cpu_enable_cnp,
2162 .desc = "Speculation barrier (SB)",
2163 .capability = ARM64_HAS_SB,
2164 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2165 .matches = has_cpuid_feature,
2166 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2167 .field_pos = ID_AA64ISAR1_SB_SHIFT,
2168 .sign = FTR_UNSIGNED,
2169 .min_field_value = 1,
2171 #ifdef CONFIG_ARM64_PTR_AUTH
2173 .desc = "Address authentication (architected algorithm)",
2174 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
2175 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2176 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2177 .sign = FTR_UNSIGNED,
2178 .field_pos = ID_AA64ISAR1_APA_SHIFT,
2179 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
2180 .matches = has_address_auth_cpucap,
2183 .desc = "Address authentication (IMP DEF algorithm)",
2184 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
2185 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2186 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2187 .sign = FTR_UNSIGNED,
2188 .field_pos = ID_AA64ISAR1_API_SHIFT,
2189 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
2190 .matches = has_address_auth_cpucap,
2193 .capability = ARM64_HAS_ADDRESS_AUTH,
2194 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2195 .matches = has_address_auth_metacap,
2198 .desc = "Generic authentication (architected algorithm)",
2199 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
2200 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2201 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2202 .sign = FTR_UNSIGNED,
2203 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
2204 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
2205 .matches = has_cpuid_feature,
2208 .desc = "Generic authentication (IMP DEF algorithm)",
2209 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
2210 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2211 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2212 .sign = FTR_UNSIGNED,
2213 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
2214 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
2215 .matches = has_cpuid_feature,
2218 .capability = ARM64_HAS_GENERIC_AUTH,
2219 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2220 .matches = has_generic_auth,
2222 #endif /* CONFIG_ARM64_PTR_AUTH */
2223 #ifdef CONFIG_ARM64_PSEUDO_NMI
2226 * Depends on having GICv3
2228 .desc = "IRQ priority masking",
2229 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
2230 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2231 .matches = can_use_gic_priorities,
2232 .sys_reg = SYS_ID_AA64PFR0_EL1,
2233 .field_pos = ID_AA64PFR0_GIC_SHIFT,
2234 .sign = FTR_UNSIGNED,
2235 .min_field_value = 1,
2238 #ifdef CONFIG_ARM64_E0PD
2241 .capability = ARM64_HAS_E0PD,
2242 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2243 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2244 .sign = FTR_UNSIGNED,
2245 .field_pos = ID_AA64MMFR2_E0PD_SHIFT,
2246 .matches = has_cpuid_feature,
2247 .min_field_value = 1,
2248 .cpu_enable = cpu_enable_e0pd,
2251 #ifdef CONFIG_ARCH_RANDOM
2253 .desc = "Random Number Generator",
2254 .capability = ARM64_HAS_RNG,
2255 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2256 .matches = has_cpuid_feature,
2257 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2258 .field_pos = ID_AA64ISAR0_RNDR_SHIFT,
2259 .sign = FTR_UNSIGNED,
2260 .min_field_value = 1,
2263 #ifdef CONFIG_ARM64_BTI
2265 .desc = "Branch Target Identification",
2266 .capability = ARM64_BTI,
2267 #ifdef CONFIG_ARM64_BTI_KERNEL
2268 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2270 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2272 .matches = has_cpuid_feature,
2273 .cpu_enable = bti_enable,
2274 .sys_reg = SYS_ID_AA64PFR1_EL1,
2275 .field_pos = ID_AA64PFR1_BT_SHIFT,
2276 .min_field_value = ID_AA64PFR1_BT_BTI,
2277 .sign = FTR_UNSIGNED,
2280 #ifdef CONFIG_ARM64_MTE
2282 .desc = "Memory Tagging Extension",
2283 .capability = ARM64_MTE,
2284 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2285 .matches = has_cpuid_feature,
2286 .sys_reg = SYS_ID_AA64PFR1_EL1,
2287 .field_pos = ID_AA64PFR1_MTE_SHIFT,
2288 .min_field_value = ID_AA64PFR1_MTE,
2289 .sign = FTR_UNSIGNED,
2290 .cpu_enable = cpu_enable_mte,
2292 #endif /* CONFIG_ARM64_MTE */
2294 .desc = "RCpc load-acquire (LDAPR)",
2295 .capability = ARM64_HAS_LDAPR,
2296 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2297 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2298 .sign = FTR_UNSIGNED,
2299 .field_pos = ID_AA64ISAR1_LRCPC_SHIFT,
2300 .matches = has_cpuid_feature,
2301 .min_field_value = 1,
2306 #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \
2307 .matches = has_cpuid_feature, \
2309 .field_pos = field, \
2311 .min_field_value = min_value,
2313 #define __HWCAP_CAP(name, cap_type, cap) \
2315 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
2316 .hwcap_type = cap_type, \
2319 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \
2321 __HWCAP_CAP(#cap, cap_type, cap) \
2322 HWCAP_CPUID_MATCH(reg, field, s, min_value) \
2325 #define HWCAP_MULTI_CAP(list, cap_type, cap) \
2327 __HWCAP_CAP(#cap, cap_type, cap) \
2328 .matches = cpucap_multi_entry_cap_matches, \
2329 .match_list = list, \
2332 #define HWCAP_CAP_MATCH(match, cap_type, cap) \
2334 __HWCAP_CAP(#cap, cap_type, cap) \
2338 #ifdef CONFIG_ARM64_PTR_AUTH
2339 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
2341 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
2342 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
2345 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
2346 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
2351 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
2353 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
2354 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
2357 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
2358 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
2364 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
2365 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
2366 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
2367 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
2368 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
2369 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
2370 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
2371 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
2372 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
2373 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
2374 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
2375 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
2376 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
2377 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
2378 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
2379 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
2380 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG),
2381 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
2382 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
2383 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
2384 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
2385 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
2386 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
2387 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
2388 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
2389 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
2390 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
2391 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
2392 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
2393 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
2394 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16),
2395 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH),
2396 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM),
2397 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
2398 #ifdef CONFIG_ARM64_SVE
2399 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
2400 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
2401 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
2402 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
2403 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
2404 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
2405 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
2406 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
2407 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
2408 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
2409 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
2411 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
2412 #ifdef CONFIG_ARM64_BTI
2413 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_BT_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI),
2415 #ifdef CONFIG_ARM64_PTR_AUTH
2416 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
2417 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
2419 #ifdef CONFIG_ARM64_MTE
2420 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE),
2421 #endif /* CONFIG_ARM64_MTE */
2425 #ifdef CONFIG_COMPAT
2426 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
2429 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
2430 * in line with that of arm32 as in vfp_init(). We make sure that the
2431 * check is future proof, by making sure value is non-zero.
2435 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
2436 if (scope == SCOPE_SYSTEM)
2437 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
2439 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
2441 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
2442 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
2443 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
2447 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
2448 #ifdef CONFIG_COMPAT
2449 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
2450 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
2451 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
2452 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
2453 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
2454 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
2455 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
2456 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
2457 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
2458 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
2463 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2465 switch (cap->hwcap_type) {
2467 cpu_set_feature(cap->hwcap);
2469 #ifdef CONFIG_COMPAT
2470 case CAP_COMPAT_HWCAP:
2471 compat_elf_hwcap |= (u32)cap->hwcap;
2473 case CAP_COMPAT_HWCAP2:
2474 compat_elf_hwcap2 |= (u32)cap->hwcap;
2483 /* Check if we have a particular HWCAP enabled */
2484 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2488 switch (cap->hwcap_type) {
2490 rc = cpu_have_feature(cap->hwcap);
2492 #ifdef CONFIG_COMPAT
2493 case CAP_COMPAT_HWCAP:
2494 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
2496 case CAP_COMPAT_HWCAP2:
2497 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
2508 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
2510 /* We support emulation of accesses to CPU ID feature registers */
2511 cpu_set_named_feature(CPUID);
2512 for (; hwcaps->matches; hwcaps++)
2513 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
2514 cap_set_elf_hwcap(hwcaps);
2517 static void update_cpu_capabilities(u16 scope_mask)
2520 const struct arm64_cpu_capabilities *caps;
2522 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2523 for (i = 0; i < ARM64_NCAPS; i++) {
2524 caps = cpu_hwcaps_ptrs[i];
2525 if (!caps || !(caps->type & scope_mask) ||
2526 cpus_have_cap(caps->capability) ||
2527 !caps->matches(caps, cpucap_default_scope(caps)))
2531 pr_info("detected: %s\n", caps->desc);
2532 cpus_set_cap(caps->capability);
2534 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
2535 set_bit(caps->capability, boot_capabilities);
2540 * Enable all the available capabilities on this CPU. The capabilities
2541 * with BOOT_CPU scope are handled separately and hence skipped here.
2543 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
2546 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
2548 for_each_available_cap(i) {
2549 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
2554 if (!(cap->type & non_boot_scope))
2557 if (cap->cpu_enable)
2558 cap->cpu_enable(cap);
2564 * Run through the enabled capabilities and enable() it on all active
2567 static void __init enable_cpu_capabilities(u16 scope_mask)
2570 const struct arm64_cpu_capabilities *caps;
2573 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2574 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
2576 for (i = 0; i < ARM64_NCAPS; i++) {
2579 caps = cpu_hwcaps_ptrs[i];
2580 if (!caps || !(caps->type & scope_mask))
2582 num = caps->capability;
2583 if (!cpus_have_cap(num))
2586 /* Ensure cpus_have_const_cap(num) works */
2587 static_branch_enable(&cpu_hwcap_keys[num]);
2589 if (boot_scope && caps->cpu_enable)
2591 * Capabilities with SCOPE_BOOT_CPU scope are finalised
2592 * before any secondary CPU boots. Thus, each secondary
2593 * will enable the capability as appropriate via
2594 * check_local_cpu_capabilities(). The only exception is
2595 * the boot CPU, for which the capability must be
2596 * enabled here. This approach avoids costly
2597 * stop_machine() calls for this case.
2599 caps->cpu_enable(caps);
2603 * For all non-boot scope capabilities, use stop_machine()
2604 * as it schedules the work allowing us to modify PSTATE,
2605 * instead of on_each_cpu() which uses an IPI, giving us a
2606 * PSTATE that disappears when we return.
2609 stop_machine(cpu_enable_non_boot_scope_capabilities,
2610 NULL, cpu_online_mask);
2614 * Run through the list of capabilities to check for conflicts.
2615 * If the system has already detected a capability, take necessary
2616 * action on this CPU.
2618 static void verify_local_cpu_caps(u16 scope_mask)
2621 bool cpu_has_cap, system_has_cap;
2622 const struct arm64_cpu_capabilities *caps;
2624 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2626 for (i = 0; i < ARM64_NCAPS; i++) {
2627 caps = cpu_hwcaps_ptrs[i];
2628 if (!caps || !(caps->type & scope_mask))
2631 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
2632 system_has_cap = cpus_have_cap(caps->capability);
2634 if (system_has_cap) {
2636 * Check if the new CPU misses an advertised feature,
2637 * which is not safe to miss.
2639 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
2642 * We have to issue cpu_enable() irrespective of
2643 * whether the CPU has it or not, as it is enabeld
2644 * system wide. It is upto the call back to take
2645 * appropriate action on this CPU.
2647 if (caps->cpu_enable)
2648 caps->cpu_enable(caps);
2651 * Check if the CPU has this capability if it isn't
2652 * safe to have when the system doesn't.
2654 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
2659 if (i < ARM64_NCAPS) {
2660 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
2661 smp_processor_id(), caps->capability,
2662 caps->desc, system_has_cap, cpu_has_cap);
2664 if (cpucap_panic_on_conflict(caps))
2672 * Check for CPU features that are used in early boot
2673 * based on the Boot CPU value.
2675 static void check_early_cpu_features(void)
2677 verify_cpu_asid_bits();
2679 verify_local_cpu_caps(SCOPE_BOOT_CPU);
2683 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
2686 for (; caps->matches; caps++)
2687 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
2688 pr_crit("CPU%d: missing HWCAP: %s\n",
2689 smp_processor_id(), caps->desc);
2694 static void verify_local_elf_hwcaps(void)
2696 __verify_local_elf_hwcaps(arm64_elf_hwcaps);
2698 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1)))
2699 __verify_local_elf_hwcaps(compat_elf_hwcaps);
2702 static void verify_sve_features(void)
2704 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
2705 u64 zcr = read_zcr_features();
2707 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
2708 unsigned int len = zcr & ZCR_ELx_LEN_MASK;
2710 if (len < safe_len || sve_verify_vq_map()) {
2711 pr_crit("CPU%d: SVE: vector length support mismatch\n",
2712 smp_processor_id());
2716 /* Add checks on other ZCR bits here if necessary */
2719 static void verify_hyp_capabilities(void)
2721 u64 safe_mmfr1, mmfr0, mmfr1;
2722 int parange, ipa_max;
2723 unsigned int safe_vmid_bits, vmid_bits;
2725 if (!IS_ENABLED(CONFIG_KVM))
2728 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
2729 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
2730 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
2732 /* Verify VMID bits */
2733 safe_vmid_bits = get_vmid_bits(safe_mmfr1);
2734 vmid_bits = get_vmid_bits(mmfr1);
2735 if (vmid_bits < safe_vmid_bits) {
2736 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id());
2740 /* Verify IPA range */
2741 parange = cpuid_feature_extract_unsigned_field(mmfr0,
2742 ID_AA64MMFR0_PARANGE_SHIFT);
2743 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange);
2744 if (ipa_max < get_kvm_ipa_limit()) {
2745 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id());
2751 * Run through the enabled system capabilities and enable() it on this CPU.
2752 * The capabilities were decided based on the available CPUs at the boot time.
2753 * Any new CPU should match the system wide status of the capability. If the
2754 * new CPU doesn't have a capability which the system now has enabled, we
2755 * cannot do anything to fix it up and could cause unexpected failures. So
2758 static void verify_local_cpu_capabilities(void)
2761 * The capabilities with SCOPE_BOOT_CPU are checked from
2762 * check_early_cpu_features(), as they need to be verified
2763 * on all secondary CPUs.
2765 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2766 verify_local_elf_hwcaps();
2768 if (system_supports_sve())
2769 verify_sve_features();
2771 if (is_hyp_mode_available())
2772 verify_hyp_capabilities();
2775 void check_local_cpu_capabilities(void)
2778 * All secondary CPUs should conform to the early CPU features
2779 * in use by the kernel based on boot CPU.
2781 check_early_cpu_features();
2784 * If we haven't finalised the system capabilities, this CPU gets
2785 * a chance to update the errata work arounds and local features.
2786 * Otherwise, this CPU should verify that it has all the system
2787 * advertised capabilities.
2789 if (!system_capabilities_finalized())
2790 update_cpu_capabilities(SCOPE_LOCAL_CPU);
2792 verify_local_cpu_capabilities();
2795 static void __init setup_boot_cpu_capabilities(void)
2797 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
2798 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
2799 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
2800 enable_cpu_capabilities(SCOPE_BOOT_CPU);
2803 bool this_cpu_has_cap(unsigned int n)
2805 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
2806 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2809 return cap->matches(cap, SCOPE_LOCAL_CPU);
2816 * This helper function is used in a narrow window when,
2817 * - The system wide safe registers are set with all the SMP CPUs and,
2818 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set.
2819 * In all other cases cpus_have_{const_}cap() should be used.
2821 static bool __maybe_unused __system_matches_cap(unsigned int n)
2823 if (n < ARM64_NCAPS) {
2824 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2827 return cap->matches(cap, SCOPE_SYSTEM);
2832 void cpu_set_feature(unsigned int num)
2834 WARN_ON(num >= MAX_CPU_FEATURES);
2835 elf_hwcap |= BIT(num);
2837 EXPORT_SYMBOL_GPL(cpu_set_feature);
2839 bool cpu_have_feature(unsigned int num)
2841 WARN_ON(num >= MAX_CPU_FEATURES);
2842 return elf_hwcap & BIT(num);
2844 EXPORT_SYMBOL_GPL(cpu_have_feature);
2846 unsigned long cpu_get_elf_hwcap(void)
2849 * We currently only populate the first 32 bits of AT_HWCAP. Please
2850 * note that for userspace compatibility we guarantee that bits 62
2851 * and 63 will always be returned as 0.
2853 return lower_32_bits(elf_hwcap);
2856 unsigned long cpu_get_elf_hwcap2(void)
2858 return upper_32_bits(elf_hwcap);
2861 static void __init setup_system_capabilities(void)
2864 * We have finalised the system-wide safe feature
2865 * registers, finalise the capabilities that depend
2866 * on it. Also enable all the available capabilities,
2867 * that are not enabled already.
2869 update_cpu_capabilities(SCOPE_SYSTEM);
2870 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2873 void __init setup_cpu_features(void)
2877 setup_system_capabilities();
2878 setup_elf_hwcaps(arm64_elf_hwcaps);
2880 if (system_supports_32bit_el0())
2881 setup_elf_hwcaps(compat_elf_hwcaps);
2883 if (system_uses_ttbr0_pan())
2884 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
2887 minsigstksz_setup();
2889 /* Advertise that we have computed the system capabilities */
2890 finalize_system_capabilities();
2893 * Check for sane CTR_EL0.CWG value.
2895 cwg = cache_type_cwg();
2897 pr_warn("No Cache Writeback Granule information, assuming %d\n",
2901 static int enable_mismatched_32bit_el0(unsigned int cpu)
2903 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
2904 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0);
2907 cpumask_set_cpu(cpu, cpu_32bit_el0_mask);
2908 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0);
2909 setup_elf_hwcaps(compat_elf_hwcaps);
2915 static int __init init_32bit_el0_mask(void)
2917 if (!allow_mismatched_32bit_el0)
2920 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL))
2923 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
2924 "arm64/mismatched_32bit_el0:online",
2925 enable_mismatched_32bit_el0, NULL);
2927 subsys_initcall_sync(init_32bit_el0_mask);
2929 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
2931 cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
2935 * We emulate only the following system register space.
2936 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
2937 * See Table C5-6 System instruction encodings for System register accesses,
2938 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
2940 static inline bool __attribute_const__ is_emulated(u32 id)
2942 return (sys_reg_Op0(id) == 0x3 &&
2943 sys_reg_CRn(id) == 0x0 &&
2944 sys_reg_Op1(id) == 0x0 &&
2945 (sys_reg_CRm(id) == 0 ||
2946 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
2950 * With CRm == 0, reg should be one of :
2951 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
2953 static inline int emulate_id_reg(u32 id, u64 *valp)
2957 *valp = read_cpuid_id();
2960 *valp = SYS_MPIDR_SAFE_VAL;
2962 case SYS_REVIDR_EL1:
2963 /* IMPLEMENTATION DEFINED values are emulated with 0 */
2973 static int emulate_sys_reg(u32 id, u64 *valp)
2975 struct arm64_ftr_reg *regp;
2977 if (!is_emulated(id))
2980 if (sys_reg_CRm(id) == 0)
2981 return emulate_id_reg(id, valp);
2983 regp = get_arm64_ftr_reg_nowarn(id);
2985 *valp = arm64_ftr_reg_user_value(regp);
2988 * The untracked registers are either IMPLEMENTATION DEFINED
2989 * (e.g, ID_AFR0_EL1) or reserved RAZ.
2995 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
3000 rc = emulate_sys_reg(sys_reg, &val);
3002 pt_regs_write_reg(regs, rt, val);
3003 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
3008 static int emulate_mrs(struct pt_regs *regs, u32 insn)
3013 * sys_reg values are defined as used in mrs/msr instruction.
3014 * shift the imm value to get the encoding.
3016 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
3017 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
3018 return do_emulate_mrs(regs, sys_reg, rt);
3021 static struct undef_hook mrs_hook = {
3022 .instr_mask = 0xffff0000,
3023 .instr_val = 0xd5380000,
3024 .pstate_mask = PSR_AA32_MODE_MASK,
3025 .pstate_val = PSR_MODE_EL0t,
3029 static int __init enable_mrs_emulation(void)
3031 register_undef_hook(&mrs_hook);
3035 core_initcall(enable_mrs_emulation);
3037 enum mitigation_state arm64_get_meltdown_state(void)
3039 if (__meltdown_safe)
3040 return SPECTRE_UNAFFECTED;
3042 if (arm64_kernel_unmapped_at_el0())
3043 return SPECTRE_MITIGATED;
3045 return SPECTRE_VULNERABLE;
3048 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
3051 switch (arm64_get_meltdown_state()) {
3052 case SPECTRE_UNAFFECTED:
3053 return sprintf(buf, "Not affected\n");
3055 case SPECTRE_MITIGATED:
3056 return sprintf(buf, "Mitigation: PTI\n");
3059 return sprintf(buf, "Vulnerable\n");