arch/arm64/kernel/cpufeature.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Contains CPU feature definitions
   4  *
   5  * Copyright (C) 2015 ARM Ltd.
   6  *
   7  * A note for the weary kernel hacker: the code here is confusing and hard to
   8  * follow! That's partly because it's solving a nasty problem, but also because
   9  * there's a little bit of over-abstraction that tends to obscure what's going
  10  * on behind a maze of helper functions and macros.
  11  *
  12  * The basic problem is that hardware folks have started gluing together CPUs
  13  * with distinct architectural features; in some cases even creating SoCs where
  14  * user-visible instructions are available only on a subset of the available
  15  * cores. We try to address this by snapshotting the feature registers of the
  16  * boot CPU and comparing these with the feature registers of each secondary
  17  * CPU when bringing them up. If there is a mismatch, then we update the
  18  * snapshot state to indicate the lowest-common denominator of the feature,
  19  * known as the "safe" value. This snapshot state can be queried to view the
  20  * "sanitised" value of a feature register.
  21  *
  22  * The sanitised register values are used to decide which capabilities we
  23  * have in the system. These may be in the form of traditional "hwcaps"
  24  * advertised to userspace or internal "cpucaps" which are used to configure
  25  * things like alternative patching and static keys. While a feature mismatch
  26  * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch
  27  * may prevent a CPU from being onlined at all.
  28  *
  29  * Some implementation details worth remembering:
  30  *
  31  * - Mismatched features are *always* sanitised to a "safe" value, which
  32  *   usually indicates that the feature is not supported.
  33  *
  34  * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
  35  *   warning when onlining an offending CPU and the kernel will be tainted
  36  *   with TAINT_CPU_OUT_OF_SPEC.
  37  *
  38  * - Features marked as FTR_VISIBLE have their sanitised value visible to
  39  *   userspace. FTR_VISIBLE features in registers that are only visible
  40  *   to EL0 by trapping *must* have a corresponding HWCAP so that late
  41  *   onlining of CPUs cannot lead to features disappearing at runtime.
  42  *
  43  * - A "feature" is typically a 4-bit register field. A "capability" is the
  44  *   high-level description derived from the sanitised field value.
  45  *
  46  * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID
  47  *   scheme for fields in ID registers") to understand when feature fields
  48  *   may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly).
  49  *
  50  * - KVM exposes its own view of the feature registers to guest operating
  51  *   systems regardless of FTR_VISIBLE. This is typically driven from the
  52  *   sanitised register values to allow virtual CPUs to be migrated between
  53  *   arbitrary physical CPUs, but some features not present on the host are
  54  *   also advertised and emulated. Look at sys_reg_descs[] for the gory
  55  *   details.
  56  *
  57  * - If the arm64_ftr_bits[] for a register has a missing field, then this
  58  *   field is treated as STRICT RES0, including for read_sanitised_ftr_reg().
  59  *   This is stronger than FTR_HIDDEN and can be used to hide features from
  60  *   KVM guests.
  61  */
  62
  63 #define pr_fmt(fmt) "CPU features: " fmt
  64
  65 #include <linux/bsearch.h>
  66 #include <linux/cpumask.h>
  67 #include <linux/crash_dump.h>
  68 #include <linux/kstrtox.h>
  69 #include <linux/sort.h>
  70 #include <linux/stop_machine.h>
  71 #include <linux/sysfs.h>
  72 #include <linux/types.h>
  73 #include <linux/minmax.h>
  74 #include <linux/mm.h>
  75 #include <linux/cpu.h>
  76 #include <linux/kasan.h>
  77 #include <linux/percpu.h>
  78
  79 #include <asm/cpu.h>
  80 #include <asm/cpufeature.h>
  81 #include <asm/cpu_ops.h>
  82 #include <asm/fpsimd.h>
  83 #include <asm/hwcap.h>
  84 #include <asm/insn.h>
  85 #include <asm/kvm_host.h>
  86 #include <asm/mmu_context.h>
  87 #include <asm/mte.h>
  88 #include <asm/processor.h>
  89 #include <asm/smp.h>
  90 #include <asm/sysreg.h>
  91 #include <asm/traps.h>
  92 #include <asm/vectors.h>
  93 #include <asm/virt.h>
  94
  95 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
  96 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly;
  97
  98 #ifdef CONFIG_COMPAT
  99 #define COMPAT_ELF_HWCAP_DEFAULT        \
 100                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
 101                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
 102                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
 103                                  COMPAT_HWCAP_LPAE)
 104 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
 105 unsigned int compat_elf_hwcap2 __read_mostly;
 106 #endif
 107
 108 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS);
 109 EXPORT_SYMBOL(system_cpucaps);
 110 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS];
 111
 112 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS);
 113
 114 bool arm64_use_ng_mappings = false;
 115 EXPORT_SYMBOL(arm64_use_ng_mappings);
 116
 117 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors;
 118
 119 /*
 120  * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs
 121  * support it?
 122  */
 123 static bool __read_mostly allow_mismatched_32bit_el0;
 124
 125 /*
 126  * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have
 127  * seen at least one CPU capable of 32-bit EL0.
 128  */
 129 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0);
 130
 131 /*
 132  * Mask of CPUs supporting 32-bit EL0.
 133  * Only valid if arm64_mismatched_32bit_el0 is enabled.
 134  */
 135 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly;
 136
 137 void dump_cpu_features(void)
 138 {
 139         /* file-wide pr_fmt adds "CPU features: " prefix */
 140         pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps);
 141 }
 142
 143 #define ARM64_CPUID_FIELDS(reg, field, min_value)                       \
 144                 .sys_reg = SYS_##reg,                                                   \
 145                 .field_pos = reg##_##field##_SHIFT,                                             \
 146                 .field_width = reg##_##field##_WIDTH,                                           \
 147                 .sign = reg##_##field##_SIGNED,                                                 \
 148                 .min_field_value = reg##_##field##_##min_value,
 149
 150 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 151         {                                               \
 152                 .sign = SIGNED,                         \
 153                 .visible = VISIBLE,                     \
 154                 .strict = STRICT,                       \
 155                 .type = TYPE,                           \
 156                 .shift = SHIFT,                         \
 157                 .width = WIDTH,                         \
 158                 .safe_val = SAFE_VAL,                   \
 159         }
 160
 161 /* Define a feature with unsigned values */
 162 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 163         __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 164
 165 /* Define a feature with a signed value */
 166 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 167         __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 168
 169 #define ARM64_FTR_END                                   \
 170         {                                               \
 171                 .width = 0,                             \
 172         }
 173
 174 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
 175
 176 static bool __system_matches_cap(unsigned int n);
 177
 178 /*
 179  * NOTE: Any changes to the visibility of features should be kept in
 180  * sync with the documentation of the CPU feature register ABI.
 181  */
 182 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
 183         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0),
 184         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0),
 185         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0),
 186         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0),
 187         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0),
 188         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0),
 189         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0),
 190         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0),
 191         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0),
 192         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0),
 193         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0),
 194         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0),
 195         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0),
 196         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0),
 197         ARM64_FTR_END,
 198 };
 199
 200 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
 201         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0),
 202         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0),
 203         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0),
 204         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0),
 205         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0),
 206         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0),
 207         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 208                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0),
 209         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 210                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0),
 211         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0),
 212         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0),
 213         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0),
 214         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 215                        FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0),
 216         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 217                        FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0),
 218         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0),
 219         ARM64_FTR_END,
 220 };
 221
 222 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
 223         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0),
 224         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0),
 225         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0),
 226         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0),
 227         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 228                        FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0),
 229         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 230                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0),
 231         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0),
 232         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0),
 233         ARM64_FTR_END,
 234 };
 235
 236 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
 237         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0),
 238         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0),
 239         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0),
 240         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0),
 241         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0),
 242         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0),
 243         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 244                                    FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0),
 245         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0),
 246         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0),
 247         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI),
 248         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI),
 249         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0),
 250         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0),
 251         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_ELx_64BIT_ONLY),
 252         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_ELx_64BIT_ONLY),
 253         ARM64_FTR_END,
 254 };
 255
 256 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
 257         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
 258                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0),
 259         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0),
 260         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0),
 261         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE),
 262                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI),
 263         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI),
 264         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI),
 265                                     FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0),
 266         ARM64_FTR_END,
 267 };
 268
 269 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
 270         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 271                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0),
 272         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 273                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0),
 274         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 275                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0),
 276         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 277                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0),
 278         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 279                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0),
 280         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 281                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0),
 282         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 283                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0),
 284         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 285                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0),
 286         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 287                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0),
 288         ARM64_FTR_END,
 289 };
 290
 291 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = {
 292         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
 293                        FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0),
 294         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
 295                        FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0),
 296         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
 297                        FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0),
 298         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
 299                        FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0),
 300         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
 301                        FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0),
 302         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
 303                        FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0),
 304         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
 305                        FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0),
 306         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
 307                        FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0),
 308         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
 309                        FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0),
 310         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
 311                        FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0),
 312         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
 313                        FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0),
 314         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
 315                        FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0),
 316         ARM64_FTR_END,
 317 };
 318
 319 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 320         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0),
 321         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0),
 322         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0),
 323         /*
 324          * Page size not being supported at Stage-2 is not fatal. You
 325          * just give up KVM if PAGE_SIZE isn't supported there. Go fix
 326          * your favourite nesting hypervisor.
 327          *
 328          * There is a small corner case where the hypervisor explicitly
 329          * advertises a given granule size at Stage-2 (value 2) on some
 330          * vCPUs, and uses the fallback to Stage-1 (value 0) for other
 331          * vCPUs. Although this is not forbidden by the architecture, it
 332          * indicates that the hypervisor is being silly (or buggy).
 333          *
 334          * We make no effort to cope with this and pretend that if these
 335          * fields are inconsistent across vCPUs, then it isn't worth
 336          * trying to bring KVM up.
 337          */
 338         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1),
 339         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1),
 340         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1),
 341         /*
 342          * We already refuse to boot CPUs that don't support our configured
 343          * page size, so we can only detect mismatches for a page size other
 344          * than the one we're currently using. Unfortunately, SoCs like this
 345          * exist in the wild so, even though we don't like it, we'll have to go
 346          * along with it and treat them as non-strict.
 347          */
 348         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI),
 349         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI),
 350         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI),
 351
 352         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0),
 353         /* Linux shouldn't care about secure memory */
 354         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0),
 355         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0),
 356         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0),
 357         /*
 358          * Differing PARange is fine as long as all peripherals and memory are mapped
 359          * within the minimum PARange of all CPUs
 360          */
 361         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0),
 362         ARM64_FTR_END,
 363 };
 364
 365 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 366         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0),
 367         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0),
 368         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0),
 369         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0),
 370         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0),
 371         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0),
 372         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0),
 373         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0),
 374         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0),
 375         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0),
 376         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0),
 377         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0),
 378         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0),
 379         ARM64_FTR_END,
 380 };
 381
 382 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 383         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0),
 384         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0),
 385         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0),
 386         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0),
 387         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0),
 388         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0),
 389         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0),
 390         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0),
 391         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0),
 392         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0),
 393         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0),
 394         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0),
 395         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0),
 396         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0),
 397         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0),
 398         ARM64_FTR_END,
 399 };
 400
 401 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = {
 402         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0),
 403         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0),
 404         ARM64_FTR_END,
 405 };
 406
 407 static const struct arm64_ftr_bits ftr_ctr[] = {
 408         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
 409         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1),
 410         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1),
 411         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0),
 412         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0),
 413         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1),
 414         /*
 415          * Linux can handle differing I-cache policies. Userspace JITs will
 416          * make use of *minLine.
 417          * If we have differing I-cache policies, report it as the weakest - VIPT.
 418          */
 419         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT),        /* L1Ip */
 420         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0),
 421         ARM64_FTR_END,
 422 };
 423
 424 static struct arm64_ftr_override __ro_after_init no_override = { };
 425
 426 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
 427         .name           = "SYS_CTR_EL0",
 428         .ftr_bits       = ftr_ctr,
 429         .override       = &no_override,
 430 };
 431
 432 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
 433         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf),
 434         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0),
 435         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0),
 436         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0),
 437         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0),
 438         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf),
 439         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0),
 440         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0),
 441         ARM64_FTR_END,
 442 };
 443
 444 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 445         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0),
 446         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0),
 447         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0),
 448         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0),
 449         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0),
 450         /*
 451          * We can instantiate multiple PMU instances with different levels
 452          * of support.
 453          */
 454         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0),
 455         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6),
 456         ARM64_FTR_END,
 457 };
 458
 459 static const struct arm64_ftr_bits ftr_mvfr0[] = {
 460         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0),
 461         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0),
 462         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0),
 463         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0),
 464         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0),
 465         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0),
 466         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0),
 467         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0),
 468         ARM64_FTR_END,
 469 };
 470
 471 static const struct arm64_ftr_bits ftr_mvfr1[] = {
 472         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0),
 473         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0),
 474         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0),
 475         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0),
 476         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0),
 477         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0),
 478         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0),
 479         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0),
 480         ARM64_FTR_END,
 481 };
 482
 483 static const struct arm64_ftr_bits ftr_mvfr2[] = {
 484         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0),
 485         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0),
 486         ARM64_FTR_END,
 487 };
 488
 489 static const struct arm64_ftr_bits ftr_dczid[] = {
 490         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1),
 491         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0),
 492         ARM64_FTR_END,
 493 };
 494
 495 static const struct arm64_ftr_bits ftr_gmid[] = {
 496         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0),
 497         ARM64_FTR_END,
 498 };
 499
 500 static const struct arm64_ftr_bits ftr_id_isar0[] = {
 501         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0),
 502         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0),
 503         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0),
 504         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0),
 505         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0),
 506         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0),
 507         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0),
 508         ARM64_FTR_END,
 509 };
 510
 511 static const struct arm64_ftr_bits ftr_id_isar5[] = {
 512         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0),
 513         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0),
 514         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0),
 515         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0),
 516         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0),
 517         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0),
 518         ARM64_FTR_END,
 519 };
 520
 521 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
 522         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0),
 523         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0),
 524         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0),
 525         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0),
 526         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0),
 527         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0),
 528         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0),
 529
 530         /*
 531          * SpecSEI = 1 indicates that the PE might generate an SError on an
 532          * external abort on speculative read. It is safe to assume that an
 533          * SError might be generated than it will not be. Hence it has been
 534          * classified as FTR_HIGHER_SAFE.
 535          */
 536         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0),
 537         ARM64_FTR_END,
 538 };
 539
 540 static const struct arm64_ftr_bits ftr_id_isar4[] = {
 541         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0),
 542         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0),
 543         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0),
 544         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0),
 545         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0),
 546         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0),
 547         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0),
 548         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0),
 549         ARM64_FTR_END,
 550 };
 551
 552 static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
 553         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0),
 554         ARM64_FTR_END,
 555 };
 556
 557 static const struct arm64_ftr_bits ftr_id_isar6[] = {
 558         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0),
 559         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0),
 560         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0),
 561         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0),
 562         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0),
 563         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0),
 564         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0),
 565         ARM64_FTR_END,
 566 };
 567
 568 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
 569         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0),
 570         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0),
 571         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0),
 572         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0),
 573         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0),
 574         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0),
 575         ARM64_FTR_END,
 576 };
 577
 578 static const struct arm64_ftr_bits ftr_id_pfr1[] = {
 579         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0),
 580         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0),
 581         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0),
 582         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0),
 583         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0),
 584         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0),
 585         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0),
 586         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0),
 587         ARM64_FTR_END,
 588 };
 589
 590 static const struct arm64_ftr_bits ftr_id_pfr2[] = {
 591         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0),
 592         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0),
 593         ARM64_FTR_END,
 594 };
 595
 596 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
 597         /* [31:28] TraceFilt */
 598         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0),
 599         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0),
 600         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0),
 601         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0),
 602         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0),
 603         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0),
 604         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0),
 605         ARM64_FTR_END,
 606 };
 607
 608 static const struct arm64_ftr_bits ftr_id_dfr1[] = {
 609         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0),
 610         ARM64_FTR_END,
 611 };
 612
 613 static const struct arm64_ftr_bits ftr_zcr[] = {
 614         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
 615                 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_WIDTH, 0),       /* LEN */
 616         ARM64_FTR_END,
 617 };
 618
 619 static const struct arm64_ftr_bits ftr_smcr[] = {
 620         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
 621                 SMCR_ELx_LEN_SHIFT, SMCR_ELx_LEN_WIDTH, 0),     /* LEN */
 622         ARM64_FTR_END,
 623 };
 624
 625 /*
 626  * Common ftr bits for a 32bit register with all hidden, strict
 627  * attributes, with 4bit feature fields and a default safe value of
 628  * 0. Covers the following 32bit registers:
 629  * id_isar[1-3], id_mmfr[1-3]
 630  */
 631 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
 632         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 633         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 634         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 635         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 636         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 637         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 638         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 639         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 640         ARM64_FTR_END,
 641 };
 642
 643 /* Table for a single 32bit feature value */
 644 static const struct arm64_ftr_bits ftr_single32[] = {
 645         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
 646         ARM64_FTR_END,
 647 };
 648
 649 static const struct arm64_ftr_bits ftr_raz[] = {
 650         ARM64_FTR_END,
 651 };
 652
 653 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) {      \
 654                 .sys_id = id,                                   \
 655                 .reg =  &(struct arm64_ftr_reg){                \
 656                         .name = id_str,                         \
 657                         .override = (ovr),                      \
 658                         .ftr_bits = &((table)[0]),              \
 659         }}
 660
 661 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr)  \
 662         __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr)
 663
 664 #define ARM64_FTR_REG(id, table)                \
 665         __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override)
 666
 667 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override;
 668 struct arm64_ftr_override __ro_after_init id_aa64pfr0_override;
 669 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override;
 670 struct arm64_ftr_override __ro_after_init id_aa64zfr0_override;
 671 struct arm64_ftr_override __ro_after_init id_aa64smfr0_override;
 672 struct arm64_ftr_override __ro_after_init id_aa64isar1_override;
 673 struct arm64_ftr_override __ro_after_init id_aa64isar2_override;
 674
 675 struct arm64_ftr_override arm64_sw_feature_override;
 676
 677 static const struct __ftr_reg_entry {
 678         u32                     sys_id;
 679         struct arm64_ftr_reg    *reg;
 680 } arm64_ftr_regs[] = {
 681
 682         /* Op1 = 0, CRn = 0, CRm = 1 */
 683         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 684         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1),
 685         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
 686         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 687         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 688         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 689         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 690
 691         /* Op1 = 0, CRn = 0, CRm = 2 */
 692         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0),
 693         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 694         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 695         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 696         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4),
 697         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 698         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 699         ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
 700
 701         /* Op1 = 0, CRn = 0, CRm = 3 */
 702         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0),
 703         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1),
 704         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 705         ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
 706         ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),
 707         ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5),
 708
 709         /* Op1 = 0, CRn = 0, CRm = 4 */
 710         ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0,
 711                                &id_aa64pfr0_override),
 712         ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1,
 713                                &id_aa64pfr1_override),
 714         ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0,
 715                                &id_aa64zfr0_override),
 716         ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0,
 717                                &id_aa64smfr0_override),
 718
 719         /* Op1 = 0, CRn = 0, CRm = 5 */
 720         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 721         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
 722
 723         /* Op1 = 0, CRn = 0, CRm = 6 */
 724         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 725         ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1,
 726                                &id_aa64isar1_override),
 727         ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2,
 728                                &id_aa64isar2_override),
 729
 730         /* Op1 = 0, CRn = 0, CRm = 7 */
 731         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 732         ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1,
 733                                &id_aa64mmfr1_override),
 734         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
 735         ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3),
 736
 737         /* Op1 = 0, CRn = 1, CRm = 2 */
 738         ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
 739         ARM64_FTR_REG(SYS_SMCR_EL1, ftr_smcr),
 740
 741         /* Op1 = 1, CRn = 0, CRm = 0 */
 742         ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid),
 743
 744         /* Op1 = 3, CRn = 0, CRm = 0 */
 745         { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
 746         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 747
 748         /* Op1 = 3, CRn = 14, CRm = 0 */
 749         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
 750 };
 751
 752 static int search_cmp_ftr_reg(const void *id, const void *regp)
 753 {
 754         return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
 755 }
 756
 757 /*
 758  * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using
 759  * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 760  * ascending order of sys_id, we use binary search to find a matching
 761  * entry.
 762  *
 763  * returns - Upon success,  matching ftr_reg entry for id.
 764  *         - NULL on failure. It is upto the caller to decide
 765  *           the impact of a failure.
 766  */
 767 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id)
 768 {
 769         const struct __ftr_reg_entry *ret;
 770
 771         ret = bsearch((const void *)(unsigned long)sys_id,
 772                         arm64_ftr_regs,
 773                         ARRAY_SIZE(arm64_ftr_regs),
 774                         sizeof(arm64_ftr_regs[0]),
 775                         search_cmp_ftr_reg);
 776         if (ret)
 777                 return ret->reg;
 778         return NULL;
 779 }
 780
 781 /*
 782  * get_arm64_ftr_reg - Looks up a feature register entry using
 783  * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn().
 784  *
 785  * returns - Upon success,  matching ftr_reg entry for id.
 786  *         - NULL on failure but with an WARN_ON().
 787  */
 788 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 789 {
 790         struct arm64_ftr_reg *reg;
 791
 792         reg = get_arm64_ftr_reg_nowarn(sys_id);
 793
 794         /*
 795          * Requesting a non-existent register search is an error. Warn
 796          * and let the caller handle it.
 797          */
 798         WARN_ON(!reg);
 799         return reg;
 800 }
 801
 802 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
 803                                s64 ftr_val)
 804 {
 805         u64 mask = arm64_ftr_mask(ftrp);
 806
 807         reg &= ~mask;
 808         reg |= (ftr_val << ftrp->shift) & mask;
 809         return reg;
 810 }
 811
 812 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
 813                                 s64 cur)
 814 {
 815         s64 ret = 0;
 816
 817         switch (ftrp->type) {
 818         case FTR_EXACT:
 819                 ret = ftrp->safe_val;
 820                 break;
 821         case FTR_LOWER_SAFE:
 822                 ret = min(new, cur);
 823                 break;
 824         case FTR_HIGHER_OR_ZERO_SAFE:
 825                 if (!cur || !new)
 826                         break;
 827                 fallthrough;
 828         case FTR_HIGHER_SAFE:
 829                 ret = max(new, cur);
 830                 break;
 831         default:
 832                 BUG();
 833         }
 834
 835         return ret;
 836 }
 837
 838 static void __init sort_ftr_regs(void)
 839 {
 840         unsigned int i;
 841
 842         for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) {
 843                 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg;
 844                 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits;
 845                 unsigned int j = 0;
 846
 847                 /*
 848                  * Features here must be sorted in descending order with respect
 849                  * to their shift values and should not overlap with each other.
 850                  */
 851                 for (; ftr_bits->width != 0; ftr_bits++, j++) {
 852                         unsigned int width = ftr_reg->ftr_bits[j].width;
 853                         unsigned int shift = ftr_reg->ftr_bits[j].shift;
 854                         unsigned int prev_shift;
 855
 856                         WARN((shift  + width) > 64,
 857                                 "%s has invalid feature at shift %d\n",
 858                                 ftr_reg->name, shift);
 859
 860                         /*
 861                          * Skip the first feature. There is nothing to
 862                          * compare against for now.
 863                          */
 864                         if (j == 0)
 865                                 continue;
 866
 867                         prev_shift = ftr_reg->ftr_bits[j - 1].shift;
 868                         WARN((shift + width) > prev_shift,
 869                                 "%s has feature overlap at shift %d\n",
 870                                 ftr_reg->name, shift);
 871                 }
 872
 873                 /*
 874                  * Skip the first register. There is nothing to
 875                  * compare against for now.
 876                  */
 877                 if (i == 0)
 878                         continue;
 879                 /*
 880                  * Registers here must be sorted in ascending order with respect
 881                  * to sys_id for subsequent binary search in get_arm64_ftr_reg()
 882                  * to work correctly.
 883                  */
 884                 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id);
 885         }
 886 }
 887
 888 /*
 889  * Initialise the CPU feature register from Boot CPU values.
 890  * Also initiliases the strict_mask for the register.
 891  * Any bits that are not covered by an arm64_ftr_bits entry are considered
 892  * RES0 for the system-wide value, and must strictly match.
 893  */
 894 static void init_cpu_ftr_reg(u32 sys_reg, u64 new)
 895 {
 896         u64 val = 0;
 897         u64 strict_mask = ~0x0ULL;
 898         u64 user_mask = 0;
 899         u64 valid_mask = 0;
 900
 901         const struct arm64_ftr_bits *ftrp;
 902         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 903
 904         if (!reg)
 905                 return;
 906
 907         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 908                 u64 ftr_mask = arm64_ftr_mask(ftrp);
 909                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 910                 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val);
 911
 912                 if ((ftr_mask & reg->override->mask) == ftr_mask) {
 913                         s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new);
 914                         char *str = NULL;
 915
 916                         if (ftr_ovr != tmp) {
 917                                 /* Unsafe, remove the override */
 918                                 reg->override->mask &= ~ftr_mask;
 919                                 reg->override->val &= ~ftr_mask;
 920                                 tmp = ftr_ovr;
 921                                 str = "ignoring override";
 922                         } else if (ftr_new != tmp) {
 923                                 /* Override was valid */
 924                                 ftr_new = tmp;
 925                                 str = "forced";
 926                         } else if (ftr_ovr == tmp) {
 927                                 /* Override was the safe value */
 928                                 str = "already set";
 929                         }
 930
 931                         if (str)
 932                                 pr_warn("%s[%d:%d]: %s to %llx\n",
 933                                         reg->name,
 934                                         ftrp->shift + ftrp->width - 1,
 935                                         ftrp->shift, str, tmp);
 936                 } else if ((ftr_mask & reg->override->val) == ftr_mask) {
 937                         reg->override->val &= ~ftr_mask;
 938                         pr_warn("%s[%d:%d]: impossible override, ignored\n",
 939                                 reg->name,
 940                                 ftrp->shift + ftrp->width - 1,
 941                                 ftrp->shift);
 942                 }
 943
 944                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 945
 946                 valid_mask |= ftr_mask;
 947                 if (!ftrp->strict)
 948                         strict_mask &= ~ftr_mask;
 949                 if (ftrp->visible)
 950                         user_mask |= ftr_mask;
 951                 else
 952                         reg->user_val = arm64_ftr_set_value(ftrp,
 953                                                             reg->user_val,
 954                                                             ftrp->safe_val);
 955         }
 956
 957         val &= valid_mask;
 958
 959         reg->sys_val = val;
 960         reg->strict_mask = strict_mask;
 961         reg->user_mask = user_mask;
 962 }
 963
 964 extern const struct arm64_cpu_capabilities arm64_errata[];
 965 static const struct arm64_cpu_capabilities arm64_features[];
 966
 967 static void __init
 968 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
 969 {
 970         for (; caps->matches; caps++) {
 971                 if (WARN(caps->capability >= ARM64_NCAPS,
 972                         "Invalid capability %d\n", caps->capability))
 973                         continue;
 974                 if (WARN(cpucap_ptrs[caps->capability],
 975                         "Duplicate entry for capability %d\n",
 976                         caps->capability))
 977                         continue;
 978                 cpucap_ptrs[caps->capability] = caps;
 979         }
 980 }
 981
 982 static void __init init_cpucap_indirect_list(void)
 983 {
 984         init_cpucap_indirect_list_from_array(arm64_features);
 985         init_cpucap_indirect_list_from_array(arm64_errata);
 986 }
 987
 988 static void __init setup_boot_cpu_capabilities(void);
 989
 990 static void init_32bit_cpu_features(struct cpuinfo_32bit *info)
 991 {
 992         init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 993         init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1);
 994         init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 995         init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 996         init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 997         init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 998         init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 999         init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
1000         init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6);
1001         init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
1002         init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
1003         init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
1004         init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
1005         init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4);
1006         init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5);
1007         init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
1008         init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
1009         init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2);
1010         init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
1011         init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
1012         init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
1013 }
1014
1015 void __init init_cpu_features(struct cpuinfo_arm64 *info)
1016 {
1017         /* Before we start using the tables, make sure it is sorted */
1018         sort_ftr_regs();
1019
1020         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
1021         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
1022         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
1023         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
1024         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
1025         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
1026         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
1027         init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2);
1028         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
1029         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
1030         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
1031         init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3);
1032         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
1033         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
1034         init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
1035         init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0);
1036
1037         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
1038                 init_32bit_cpu_features(&info->aarch32);
1039
1040         if (IS_ENABLED(CONFIG_ARM64_SVE) &&
1041             id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) {
1042                 info->reg_zcr = read_zcr_features();
1043                 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
1044                 vec_init_vq_map(ARM64_VEC_SVE);
1045         }
1046
1047         if (IS_ENABLED(CONFIG_ARM64_SME) &&
1048             id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) {
1049                 info->reg_smcr = read_smcr_features();
1050                 /*
1051                  * We mask out SMPS since even if the hardware
1052                  * supports priorities the kernel does not at present
1053                  * and we block access to them.
1054                  */
1055                 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS;
1056                 init_cpu_ftr_reg(SYS_SMCR_EL1, info->reg_smcr);
1057                 vec_init_vq_map(ARM64_VEC_SME);
1058         }
1059
1060         if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
1061                 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid);
1062
1063         /*
1064          * Initialize the indirect array of CPU capabilities pointers before we
1065          * handle the boot CPU below.
1066          */
1067         init_cpucap_indirect_list();
1068
1069         /*
1070          * Detect and enable early CPU capabilities based on the boot CPU,
1071          * after we have initialised the CPU feature infrastructure.
1072          */
1073         setup_boot_cpu_capabilities();
1074 }
1075
1076 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
1077 {
1078         const struct arm64_ftr_bits *ftrp;
1079
1080         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
1081                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
1082                 s64 ftr_new = arm64_ftr_value(ftrp, new);
1083
1084                 if (ftr_cur == ftr_new)
1085                         continue;
1086                 /* Find a safe value */
1087                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
1088                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
1089         }
1090
1091 }
1092
1093 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
1094 {
1095         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
1096
1097         if (!regp)
1098                 return 0;
1099
1100         update_cpu_ftr_reg(regp, val);
1101         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
1102                 return 0;
1103         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
1104                         regp->name, boot, cpu, val);
1105         return 1;
1106 }
1107
1108 static void relax_cpu_ftr_reg(u32 sys_id, int field)
1109 {
1110         const struct arm64_ftr_bits *ftrp;
1111         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
1112
1113         if (!regp)
1114                 return;
1115
1116         for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) {
1117                 if (ftrp->shift == field) {
1118                         regp->strict_mask &= ~arm64_ftr_mask(ftrp);
1119                         break;
1120                 }
1121         }
1122
1123         /* Bogus field? */
1124         WARN_ON(!ftrp->width);
1125 }
1126
1127 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info,
1128                                          struct cpuinfo_arm64 *boot)
1129 {
1130         static bool boot_cpu_32bit_regs_overridden = false;
1131
1132         if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden)
1133                 return;
1134
1135         if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0))
1136                 return;
1137
1138         boot->aarch32 = info->aarch32;
1139         init_32bit_cpu_features(&boot->aarch32);
1140         boot_cpu_32bit_regs_overridden = true;
1141 }
1142
1143 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info,
1144                                      struct cpuinfo_32bit *boot)
1145 {
1146         int taint = 0;
1147         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1148
1149         /*
1150          * If we don't have AArch32 at EL1, then relax the strictness of
1151          * EL1-dependent register fields to avoid spurious sanity check fails.
1152          */
1153         if (!id_aa64pfr0_32bit_el1(pfr0)) {
1154                 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT);
1155                 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT);
1156                 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT);
1157                 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT);
1158                 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT);
1159                 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT);
1160         }
1161
1162         taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
1163                                       info->reg_id_dfr0, boot->reg_id_dfr0);
1164         taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu,
1165                                       info->reg_id_dfr1, boot->reg_id_dfr1);
1166         taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
1167                                       info->reg_id_isar0, boot->reg_id_isar0);
1168         taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
1169                                       info->reg_id_isar1, boot->reg_id_isar1);
1170         taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
1171                                       info->reg_id_isar2, boot->reg_id_isar2);
1172         taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
1173                                       info->reg_id_isar3, boot->reg_id_isar3);
1174         taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
1175                                       info->reg_id_isar4, boot->reg_id_isar4);
1176         taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
1177                                       info->reg_id_isar5, boot->reg_id_isar5);
1178         taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu,
1179                                       info->reg_id_isar6, boot->reg_id_isar6);
1180
1181         /*
1182          * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
1183          * ACTLR formats could differ across CPUs and therefore would have to
1184          * be trapped for virtualization anyway.
1185          */
1186         taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
1187                                       info->reg_id_mmfr0, boot->reg_id_mmfr0);
1188         taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
1189                                       info->reg_id_mmfr1, boot->reg_id_mmfr1);
1190         taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
1191                                       info->reg_id_mmfr2, boot->reg_id_mmfr2);
1192         taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
1193                                       info->reg_id_mmfr3, boot->reg_id_mmfr3);
1194         taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu,
1195                                       info->reg_id_mmfr4, boot->reg_id_mmfr4);
1196         taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu,
1197                                       info->reg_id_mmfr5, boot->reg_id_mmfr5);
1198         taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
1199                                       info->reg_id_pfr0, boot->reg_id_pfr0);
1200         taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
1201                                       info->reg_id_pfr1, boot->reg_id_pfr1);
1202         taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu,
1203                                       info->reg_id_pfr2, boot->reg_id_pfr2);
1204         taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
1205                                       info->reg_mvfr0, boot->reg_mvfr0);
1206         taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
1207                                       info->reg_mvfr1, boot->reg_mvfr1);
1208         taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
1209                                       info->reg_mvfr2, boot->reg_mvfr2);
1210
1211         return taint;
1212 }
1213
1214 /*
1215  * Update system wide CPU feature registers with the values from a
1216  * non-boot CPU. Also performs SANITY checks to make sure that there
1217  * aren't any insane variations from that of the boot CPU.
1218  */
1219 void update_cpu_features(int cpu,
1220                          struct cpuinfo_arm64 *info,
1221                          struct cpuinfo_arm64 *boot)
1222 {
1223         int taint = 0;
1224
1225         /*
1226          * The kernel can handle differing I-cache policies, but otherwise
1227          * caches should look identical. Userspace JITs will make use of
1228          * *minLine.
1229          */
1230         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
1231                                       info->reg_ctr, boot->reg_ctr);
1232
1233         /*
1234          * Userspace may perform DC ZVA instructions. Mismatched block sizes
1235          * could result in too much or too little memory being zeroed if a
1236          * process is preempted and migrated between CPUs.
1237          */
1238         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
1239                                       info->reg_dczid, boot->reg_dczid);
1240
1241         /* If different, timekeeping will be broken (especially with KVM) */
1242         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
1243                                       info->reg_cntfrq, boot->reg_cntfrq);
1244
1245         /*
1246          * The kernel uses self-hosted debug features and expects CPUs to
1247          * support identical debug features. We presently need CTX_CMPs, WRPs,
1248          * and BRPs to be identical.
1249          * ID_AA64DFR1 is currently RES0.
1250          */
1251         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
1252                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
1253         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
1254                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
1255         /*
1256          * Even in big.LITTLE, processors should be identical instruction-set
1257          * wise.
1258          */
1259         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
1260                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
1261         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
1262                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
1263         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu,
1264                                       info->reg_id_aa64isar2, boot->reg_id_aa64isar2);
1265
1266         /*
1267          * Differing PARange support is fine as long as all peripherals and
1268          * memory are mapped within the minimum PARange of all CPUs.
1269          * Linux should not care about secure memory.
1270          */
1271         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
1272                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
1273         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
1274                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
1275         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
1276                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
1277         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu,
1278                                       info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3);
1279
1280         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
1281                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
1282         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
1283                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
1284
1285         taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
1286                                       info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
1287
1288         taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu,
1289                                       info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0);
1290
1291         if (IS_ENABLED(CONFIG_ARM64_SVE) &&
1292             id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) {
1293                 info->reg_zcr = read_zcr_features();
1294                 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
1295                                         info->reg_zcr, boot->reg_zcr);
1296
1297                 /* Probe vector lengths */
1298                 if (!system_capabilities_finalized())
1299                         vec_update_vq_map(ARM64_VEC_SVE);
1300         }
1301
1302         if (IS_ENABLED(CONFIG_ARM64_SME) &&
1303             id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) {
1304                 info->reg_smcr = read_smcr_features();
1305                 /*
1306                  * We mask out SMPS since even if the hardware
1307                  * supports priorities the kernel does not at present
1308                  * and we block access to them.
1309                  */
1310                 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS;
1311                 taint |= check_update_ftr_reg(SYS_SMCR_EL1, cpu,
1312                                         info->reg_smcr, boot->reg_smcr);
1313
1314                 /* Probe vector lengths */
1315                 if (!system_capabilities_finalized())
1316                         vec_update_vq_map(ARM64_VEC_SME);
1317         }
1318
1319         /*
1320          * The kernel uses the LDGM/STGM instructions and the number of tags
1321          * they read/write depends on the GMID_EL1.BS field. Check that the
1322          * value is the same on all CPUs.
1323          */
1324         if (IS_ENABLED(CONFIG_ARM64_MTE) &&
1325             id_aa64pfr1_mte(info->reg_id_aa64pfr1)) {
1326                 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu,
1327                                               info->reg_gmid, boot->reg_gmid);
1328         }
1329
1330         /*
1331          * If we don't have AArch32 at all then skip the checks entirely
1332          * as the register values may be UNKNOWN and we're not going to be
1333          * using them for anything.
1334          *
1335          * This relies on a sanitised view of the AArch64 ID registers
1336          * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last.
1337          */
1338         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
1339                 lazy_init_32bit_cpu_features(info, boot);
1340                 taint |= update_32bit_cpu_features(cpu, &info->aarch32,
1341                                                    &boot->aarch32);
1342         }
1343
1344         /*
1345          * Mismatched CPU features are a recipe for disaster. Don't even
1346          * pretend to support them.
1347          */
1348         if (taint) {
1349                 pr_warn_once("Unsupported CPU feature variation detected.\n");
1350                 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1351         }
1352 }
1353
1354 u64 read_sanitised_ftr_reg(u32 id)
1355 {
1356         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
1357
1358         if (!regp)
1359                 return 0;
1360         return regp->sys_val;
1361 }
1362 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg);
1363
1364 #define read_sysreg_case(r)     \
1365         case r:         val = read_sysreg_s(r); break;
1366
1367 /*
1368  * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
1369  * Read the system register on the current CPU
1370  */
1371 u64 __read_sysreg_by_encoding(u32 sys_id)
1372 {
1373         struct arm64_ftr_reg *regp;
1374         u64 val;
1375
1376         switch (sys_id) {
1377         read_sysreg_case(SYS_ID_PFR0_EL1);
1378         read_sysreg_case(SYS_ID_PFR1_EL1);
1379         read_sysreg_case(SYS_ID_PFR2_EL1);
1380         read_sysreg_case(SYS_ID_DFR0_EL1);
1381         read_sysreg_case(SYS_ID_DFR1_EL1);
1382         read_sysreg_case(SYS_ID_MMFR0_EL1);
1383         read_sysreg_case(SYS_ID_MMFR1_EL1);
1384         read_sysreg_case(SYS_ID_MMFR2_EL1);
1385         read_sysreg_case(SYS_ID_MMFR3_EL1);
1386         read_sysreg_case(SYS_ID_MMFR4_EL1);
1387         read_sysreg_case(SYS_ID_MMFR5_EL1);
1388         read_sysreg_case(SYS_ID_ISAR0_EL1);
1389         read_sysreg_case(SYS_ID_ISAR1_EL1);
1390         read_sysreg_case(SYS_ID_ISAR2_EL1);
1391         read_sysreg_case(SYS_ID_ISAR3_EL1);
1392         read_sysreg_case(SYS_ID_ISAR4_EL1);
1393         read_sysreg_case(SYS_ID_ISAR5_EL1);
1394         read_sysreg_case(SYS_ID_ISAR6_EL1);
1395         read_sysreg_case(SYS_MVFR0_EL1);
1396         read_sysreg_case(SYS_MVFR1_EL1);
1397         read_sysreg_case(SYS_MVFR2_EL1);
1398
1399         read_sysreg_case(SYS_ID_AA64PFR0_EL1);
1400         read_sysreg_case(SYS_ID_AA64PFR1_EL1);
1401         read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
1402         read_sysreg_case(SYS_ID_AA64SMFR0_EL1);
1403         read_sysreg_case(SYS_ID_AA64DFR0_EL1);
1404         read_sysreg_case(SYS_ID_AA64DFR1_EL1);
1405         read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
1406         read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
1407         read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
1408         read_sysreg_case(SYS_ID_AA64MMFR3_EL1);
1409         read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
1410         read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
1411         read_sysreg_case(SYS_ID_AA64ISAR2_EL1);
1412
1413         read_sysreg_case(SYS_CNTFRQ_EL0);
1414         read_sysreg_case(SYS_CTR_EL0);
1415         read_sysreg_case(SYS_DCZID_EL0);
1416
1417         default:
1418                 BUG();
1419                 return 0;
1420         }
1421
1422         regp  = get_arm64_ftr_reg(sys_id);
1423         if (regp) {
1424                 val &= ~regp->override->mask;
1425                 val |= (regp->override->val & regp->override->mask);
1426         }
1427
1428         return val;
1429 }
1430
1431 #include <linux/irqchip/arm-gic-v3.h>
1432
1433 static bool
1434 has_always(const struct arm64_cpu_capabilities *entry, int scope)
1435 {
1436         return true;
1437 }
1438
1439 static bool
1440 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
1441 {
1442         int val = cpuid_feature_extract_field_width(reg, entry->field_pos,
1443                                                     entry->field_width,
1444                                                     entry->sign);
1445
1446         return val >= entry->min_field_value;
1447 }
1448
1449 static u64
1450 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope)
1451 {
1452         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1453         if (scope == SCOPE_SYSTEM)
1454                 return read_sanitised_ftr_reg(entry->sys_reg);
1455         else
1456                 return __read_sysreg_by_encoding(entry->sys_reg);
1457 }
1458
1459 static bool
1460 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
1461 {
1462         int mask;
1463         struct arm64_ftr_reg *regp;
1464         u64 val = read_scoped_sysreg(entry, scope);
1465
1466         regp = get_arm64_ftr_reg(entry->sys_reg);
1467         if (!regp)
1468                 return false;
1469
1470         mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask,
1471                                                           entry->field_pos,
1472                                                           entry->field_width);
1473         if (!mask)
1474                 return false;
1475
1476         return feature_matches(val, entry);
1477 }
1478
1479 static bool
1480 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
1481 {
1482         u64 val = read_scoped_sysreg(entry, scope);
1483         return feature_matches(val, entry);
1484 }
1485
1486 const struct cpumask *system_32bit_el0_cpumask(void)
1487 {
1488         if (!system_supports_32bit_el0())
1489                 return cpu_none_mask;
1490
1491         if (static_branch_unlikely(&arm64_mismatched_32bit_el0))
1492                 return cpu_32bit_el0_mask;
1493
1494         return cpu_possible_mask;
1495 }
1496
1497 static int __init parse_32bit_el0_param(char *str)
1498 {
1499         allow_mismatched_32bit_el0 = true;
1500         return 0;
1501 }
1502 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param);
1503
1504 static ssize_t aarch32_el0_show(struct device *dev,
1505                                 struct device_attribute *attr, char *buf)
1506 {
1507         const struct cpumask *mask = system_32bit_el0_cpumask();
1508
1509         return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask));
1510 }
1511 static const DEVICE_ATTR_RO(aarch32_el0);
1512
1513 static int __init aarch32_el0_sysfs_init(void)
1514 {
1515         struct device *dev_root;
1516         int ret = 0;
1517
1518         if (!allow_mismatched_32bit_el0)
1519                 return 0;
1520
1521         dev_root = bus_get_dev_root(&cpu_subsys);
1522         if (dev_root) {
1523                 ret = device_create_file(dev_root, &dev_attr_aarch32_el0);
1524                 put_device(dev_root);
1525         }
1526         return ret;
1527 }
1528 device_initcall(aarch32_el0_sysfs_init);
1529
1530 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope)
1531 {
1532         if (!has_cpuid_feature(entry, scope))
1533                 return allow_mismatched_32bit_el0;
1534
1535         if (scope == SCOPE_SYSTEM)
1536                 pr_info("detected: 32-bit EL0 Support\n");
1537
1538         return true;
1539 }
1540
1541 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
1542 {
1543         bool has_sre;
1544
1545         if (!has_cpuid_feature(entry, scope))
1546                 return false;
1547
1548         has_sre = gic_enable_sre();
1549         if (!has_sre)
1550                 pr_warn_once("%s present but disabled by higher exception level\n",
1551                              entry->desc);
1552
1553         return has_sre;
1554 }
1555
1556 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
1557 {
1558         u32 midr = read_cpuid_id();
1559
1560         /* Cavium ThunderX pass 1.x and 2.x */
1561         return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
1562                 MIDR_CPU_VAR_REV(0, 0),
1563                 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
1564 }
1565
1566 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
1567 {
1568         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1569
1570         return cpuid_feature_extract_signed_field(pfr0,
1571                                         ID_AA64PFR0_EL1_FP_SHIFT) < 0;
1572 }
1573
1574 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
1575                           int scope)
1576 {
1577         u64 ctr;
1578
1579         if (scope == SCOPE_SYSTEM)
1580                 ctr = arm64_ftr_reg_ctrel0.sys_val;
1581         else
1582                 ctr = read_cpuid_effective_cachetype();
1583
1584         return ctr & BIT(CTR_EL0_IDC_SHIFT);
1585 }
1586
1587 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
1588 {
1589         /*
1590          * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
1591          * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
1592          * to the CTR_EL0 on this CPU and emulate it with the real/safe
1593          * value.
1594          */
1595         if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT)))
1596                 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
1597 }
1598
1599 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
1600                           int scope)
1601 {
1602         u64 ctr;
1603
1604         if (scope == SCOPE_SYSTEM)
1605                 ctr = arm64_ftr_reg_ctrel0.sys_val;
1606         else
1607                 ctr = read_cpuid_cachetype();
1608
1609         return ctr & BIT(CTR_EL0_DIC_SHIFT);
1610 }
1611
1612 static bool __maybe_unused
1613 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
1614 {
1615         /*
1616          * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
1617          * may share TLB entries with a CPU stuck in the crashed
1618          * kernel.
1619          */
1620         if (is_kdump_kernel())
1621                 return false;
1622
1623         if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP))
1624                 return false;
1625
1626         return has_cpuid_feature(entry, scope);
1627 }
1628
1629 /*
1630  * This check is triggered during the early boot before the cpufeature
1631  * is initialised. Checking the status on the local CPU allows the boot
1632  * CPU to detect the need for non-global mappings and thus avoiding a
1633  * pagetable re-write after all the CPUs are booted. This check will be
1634  * anyway run on individual CPUs, allowing us to get the consistent
1635  * state once the SMP CPUs are up and thus make the switch to non-global
1636  * mappings if required.
1637  */
1638 bool kaslr_requires_kpti(void)
1639 {
1640         if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE))
1641                 return false;
1642
1643         /*
1644          * E0PD does a similar job to KPTI so can be used instead
1645          * where available.
1646          */
1647         if (IS_ENABLED(CONFIG_ARM64_E0PD)) {
1648                 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1);
1649                 if (cpuid_feature_extract_unsigned_field(mmfr2,
1650                                                 ID_AA64MMFR2_EL1_E0PD_SHIFT))
1651                         return false;
1652         }
1653
1654         /*
1655          * Systems affected by Cavium erratum 24756 are incompatible
1656          * with KPTI.
1657          */
1658         if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) {
1659                 extern const struct midr_range cavium_erratum_27456_cpus[];
1660
1661                 if (is_midr_in_range_list(read_cpuid_id(),
1662                                           cavium_erratum_27456_cpus))
1663                         return false;
1664         }
1665
1666         return kaslr_enabled();
1667 }
1668
1669 static bool __meltdown_safe = true;
1670 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
1671
1672 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
1673                                 int scope)
1674 {
1675         /* List of CPUs that are not vulnerable and don't need KPTI */
1676         static const struct midr_range kpti_safe_list[] = {
1677                 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
1678                 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
1679                 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
1680                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
1681                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
1682                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1683                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
1684                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
1685                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
1686                 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
1687                 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
1688                 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD),
1689                 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER),
1690                 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
1691                 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
1692                 { /* sentinel */ }
1693         };
1694         char const *str = "kpti command line option";
1695         bool meltdown_safe;
1696
1697         meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
1698
1699         /* Defer to CPU feature registers */
1700         if (has_cpuid_feature(entry, scope))
1701                 meltdown_safe = true;
1702
1703         if (!meltdown_safe)
1704                 __meltdown_safe = false;
1705
1706         /*
1707          * For reasons that aren't entirely clear, enabling KPTI on Cavium
1708          * ThunderX leads to apparent I-cache corruption of kernel text, which
1709          * ends as well as you might imagine. Don't even try. We cannot rely
1710          * on the cpus_have_*cap() helpers here to detect the CPU erratum
1711          * because cpucap detection order may change. However, since we know
1712          * affected CPUs are always in a homogeneous configuration, it is
1713          * safe to rely on this_cpu_has_cap() here.
1714          */
1715         if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1716                 str = "ARM64_WORKAROUND_CAVIUM_27456";
1717                 __kpti_forced = -1;
1718         }
1719
1720         /* Useful for KASLR robustness */
1721         if (kaslr_requires_kpti()) {
1722                 if (!__kpti_forced) {
1723                         str = "KASLR";
1724                         __kpti_forced = 1;
1725                 }
1726         }
1727
1728         if (cpu_mitigations_off() && !__kpti_forced) {
1729                 str = "mitigations=off";
1730                 __kpti_forced = -1;
1731         }
1732
1733         if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1734                 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1735                 return false;
1736         }
1737
1738         /* Forced? */
1739         if (__kpti_forced) {
1740                 pr_info_once("kernel page table isolation forced %s by %s\n",
1741                              __kpti_forced > 0 ? "ON" : "OFF", str);
1742                 return __kpti_forced > 0;
1743         }
1744
1745         return !meltdown_safe;
1746 }
1747
1748 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1749 #define KPTI_NG_TEMP_VA         (-(1UL << PMD_SHIFT))
1750
1751 extern
1752 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt,
1753                              phys_addr_t size, pgprot_t prot,
1754                              phys_addr_t (*pgtable_alloc)(int), int flags);
1755
1756 static phys_addr_t kpti_ng_temp_alloc;
1757
1758 static phys_addr_t kpti_ng_pgd_alloc(int shift)
1759 {
1760         kpti_ng_temp_alloc -= PAGE_SIZE;
1761         return kpti_ng_temp_alloc;
1762 }
1763
1764 static void
1765 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1766 {
1767         typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long);
1768         extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1769         kpti_remap_fn *remap_fn;
1770
1771         int cpu = smp_processor_id();
1772         int levels = CONFIG_PGTABLE_LEVELS;
1773         int order = order_base_2(levels);
1774         u64 kpti_ng_temp_pgd_pa = 0;
1775         pgd_t *kpti_ng_temp_pgd;
1776         u64 alloc = 0;
1777
1778         if (__this_cpu_read(this_cpu_vector) == vectors) {
1779                 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI);
1780
1781                 __this_cpu_write(this_cpu_vector, v);
1782         }
1783
1784         /*
1785          * We don't need to rewrite the page-tables if either we've done
1786          * it already or we have KASLR enabled and therefore have not
1787          * created any global mappings at all.
1788          */
1789         if (arm64_use_ng_mappings)
1790                 return;
1791
1792         remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
1793
1794         if (!cpu) {
1795                 alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order);
1796                 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE);
1797                 kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd);
1798
1799                 //
1800                 // Create a minimal page table hierarchy that permits us to map
1801                 // the swapper page tables temporarily as we traverse them.
1802                 //
1803                 // The physical pages are laid out as follows:
1804                 //
1805                 // +--------+-/-------+-/------ +-\\--------+
1806                 // :  PTE[] : | PMD[] : | PUD[] : || PGD[]  :
1807                 // +--------+-\-------+-\------ +-//--------+
1808                 //      ^
1809                 // The first page is mapped into this hierarchy at a PMD_SHIFT
1810                 // aligned virtual address, so that we can manipulate the PTE
1811                 // level entries while the mapping is active. The first entry
1812                 // covers the PTE[] page itself, the remaining entries are free
1813                 // to be used as a ad-hoc fixmap.
1814                 //
1815                 create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc),
1816                                         KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL,
1817                                         kpti_ng_pgd_alloc, 0);
1818         }
1819
1820         cpu_install_idmap();
1821         remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA);
1822         cpu_uninstall_idmap();
1823
1824         if (!cpu) {
1825                 free_pages(alloc, order);
1826                 arm64_use_ng_mappings = true;
1827         }
1828 }
1829 #else
1830 static void
1831 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1832 {
1833 }
1834 #endif  /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1835
1836 static int __init parse_kpti(char *str)
1837 {
1838         bool enabled;
1839         int ret = kstrtobool(str, &enabled);
1840
1841         if (ret)
1842                 return ret;
1843
1844         __kpti_forced = enabled ? 1 : -1;
1845         return 0;
1846 }
1847 early_param("kpti", parse_kpti);
1848
1849 #ifdef CONFIG_ARM64_HW_AFDBM
1850 static inline void __cpu_enable_hw_dbm(void)
1851 {
1852         u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1853
1854         write_sysreg(tcr, tcr_el1);
1855         isb();
1856         local_flush_tlb_all();
1857 }
1858
1859 static bool cpu_has_broken_dbm(void)
1860 {
1861         /* List of CPUs which have broken DBM support. */
1862         static const struct midr_range cpus[] = {
1863 #ifdef CONFIG_ARM64_ERRATUM_1024718
1864                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1865                 /* Kryo4xx Silver (rdpe => r1p0) */
1866                 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
1867 #endif
1868 #ifdef CONFIG_ARM64_ERRATUM_2051678
1869                 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2),
1870 #endif
1871                 {},
1872         };
1873
1874         return is_midr_in_range_list(read_cpuid_id(), cpus);
1875 }
1876
1877 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1878 {
1879         return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1880                !cpu_has_broken_dbm();
1881 }
1882
1883 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1884 {
1885         if (cpu_can_use_dbm(cap))
1886                 __cpu_enable_hw_dbm();
1887 }
1888
1889 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1890                        int __unused)
1891 {
1892         static bool detected = false;
1893         /*
1894          * DBM is a non-conflicting feature. i.e, the kernel can safely
1895          * run a mix of CPUs with and without the feature. So, we
1896          * unconditionally enable the capability to allow any late CPU
1897          * to use the feature. We only enable the control bits on the
1898          * CPU, if it actually supports.
1899          *
1900          * We have to make sure we print the "feature" detection only
1901          * when at least one CPU actually uses it. So check if this CPU
1902          * can actually use it and print the message exactly once.
1903          *
1904          * This is safe as all CPUs (including secondary CPUs - due to the
1905          * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1906          * goes through the "matches" check exactly once. Also if a CPU
1907          * matches the criteria, it is guaranteed that the CPU will turn
1908          * the DBM on, as the capability is unconditionally enabled.
1909          */
1910         if (!detected && cpu_can_use_dbm(cap)) {
1911                 detected = true;
1912                 pr_info("detected: Hardware dirty bit management\n");
1913         }
1914
1915         return true;
1916 }
1917
1918 #endif
1919
1920 #ifdef CONFIG_ARM64_AMU_EXTN
1921
1922 /*
1923  * The "amu_cpus" cpumask only signals that the CPU implementation for the
1924  * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide
1925  * information regarding all the events that it supports. When a CPU bit is
1926  * set in the cpumask, the user of this feature can only rely on the presence
1927  * of the 4 fixed counters for that CPU. But this does not guarantee that the
1928  * counters are enabled or access to these counters is enabled by code
1929  * executed at higher exception levels (firmware).
1930  */
1931 static struct cpumask amu_cpus __read_mostly;
1932
1933 bool cpu_has_amu_feat(int cpu)
1934 {
1935         return cpumask_test_cpu(cpu, &amu_cpus);
1936 }
1937
1938 int get_cpu_with_amu_feat(void)
1939 {
1940         return cpumask_any(&amu_cpus);
1941 }
1942
1943 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
1944 {
1945         if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) {
1946                 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n",
1947                         smp_processor_id());
1948                 cpumask_set_cpu(smp_processor_id(), &amu_cpus);
1949
1950                 /* 0 reference values signal broken/disabled counters */
1951                 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168))
1952                         update_freq_counters_refs();
1953         }
1954 }
1955
1956 static bool has_amu(const struct arm64_cpu_capabilities *cap,
1957                     int __unused)
1958 {
1959         /*
1960          * The AMU extension is a non-conflicting feature: the kernel can
1961          * safely run a mix of CPUs with and without support for the
1962          * activity monitors extension. Therefore, unconditionally enable
1963          * the capability to allow any late CPU to use the feature.
1964          *
1965          * With this feature unconditionally enabled, the cpu_enable
1966          * function will be called for all CPUs that match the criteria,
1967          * including secondary and hotplugged, marking this feature as
1968          * present on that respective CPU. The enable function will also
1969          * print a detection message.
1970          */
1971
1972         return true;
1973 }
1974 #else
1975 int get_cpu_with_amu_feat(void)
1976 {
1977         return nr_cpu_ids;
1978 }
1979 #endif
1980
1981 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1982 {
1983         return is_kernel_in_hyp_mode();
1984 }
1985
1986 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1987 {
1988         /*
1989          * Copy register values that aren't redirected by hardware.
1990          *
1991          * Before code patching, we only set tpidr_el1, all CPUs need to copy
1992          * this value to tpidr_el2 before we patch the code. Once we've done
1993          * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1994          * do anything here.
1995          */
1996         if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1997                 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1998 }
1999
2000 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap,
2001                                     int scope)
2002 {
2003         if (kvm_get_mode() != KVM_MODE_NV)
2004                 return false;
2005
2006         if (!has_cpuid_feature(cap, scope)) {
2007                 pr_warn("unavailable: %s\n", cap->desc);
2008                 return false;
2009         }
2010
2011         return true;
2012 }
2013
2014 static bool hvhe_possible(const struct arm64_cpu_capabilities *entry,
2015                           int __unused)
2016 {
2017         u64 val;
2018
2019         val = read_sysreg(id_aa64mmfr1_el1);
2020         if (!cpuid_feature_extract_unsigned_field(val, ID_AA64MMFR1_EL1_VH_SHIFT))
2021                 return false;
2022
2023         val = arm64_sw_feature_override.val & arm64_sw_feature_override.mask;
2024         return cpuid_feature_extract_unsigned_field(val, ARM64_SW_FEATURE_OVERRIDE_HVHE);
2025 }
2026
2027 #ifdef CONFIG_ARM64_PAN
2028 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
2029 {
2030         /*
2031          * We modify PSTATE. This won't work from irq context as the PSTATE
2032          * is discarded once we return from the exception.
2033          */
2034         WARN_ON_ONCE(in_interrupt());
2035
2036         sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
2037         set_pstate_pan(1);
2038 }
2039 #endif /* CONFIG_ARM64_PAN */
2040
2041 #ifdef CONFIG_ARM64_RAS_EXTN
2042 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
2043 {
2044         /* Firmware may have left a deferred SError in this register. */
2045         write_sysreg_s(0, SYS_DISR_EL1);
2046 }
2047 #endif /* CONFIG_ARM64_RAS_EXTN */
2048
2049 #ifdef CONFIG_ARM64_PTR_AUTH
2050 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope)
2051 {
2052         int boot_val, sec_val;
2053
2054         /* We don't expect to be called with SCOPE_SYSTEM */
2055         WARN_ON(scope == SCOPE_SYSTEM);
2056         /*
2057          * The ptr-auth feature levels are not intercompatible with lower
2058          * levels. Hence we must match ptr-auth feature level of the secondary
2059          * CPUs with that of the boot CPU. The level of boot cpu is fetched
2060          * from the sanitised register whereas direct register read is done for
2061          * the secondary CPUs.
2062          * The sanitised feature state is guaranteed to match that of the
2063          * boot CPU as a mismatched secondary CPU is parked before it gets
2064          * a chance to update the state, with the capability.
2065          */
2066         boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg),
2067                                                entry->field_pos, entry->sign);
2068         if (scope & SCOPE_BOOT_CPU)
2069                 return boot_val >= entry->min_field_value;
2070         /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */
2071         sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg),
2072                                               entry->field_pos, entry->sign);
2073         return (sec_val >= entry->min_field_value) && (sec_val == boot_val);
2074 }
2075
2076 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry,
2077                                      int scope)
2078 {
2079         bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope);
2080         bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope);
2081         bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope);
2082
2083         return apa || apa3 || api;
2084 }
2085
2086 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,
2087                              int __unused)
2088 {
2089         bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF);
2090         bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5);
2091         bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3);
2092
2093         return gpa || gpa3 || gpi;
2094 }
2095 #endif /* CONFIG_ARM64_PTR_AUTH */
2096
2097 #ifdef CONFIG_ARM64_E0PD
2098 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
2099 {
2100         if (this_cpu_has_cap(ARM64_HAS_E0PD))
2101                 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
2102 }
2103 #endif /* CONFIG_ARM64_E0PD */
2104
2105 #ifdef CONFIG_ARM64_PSEUDO_NMI
2106 static bool enable_pseudo_nmi;
2107
2108 static int __init early_enable_pseudo_nmi(char *p)
2109 {
2110         return kstrtobool(p, &enable_pseudo_nmi);
2111 }
2112 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
2113
2114 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
2115                                    int scope)
2116 {
2117         /*
2118          * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU
2119          * feature, so will be detected earlier.
2120          */
2121         BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GIC_CPUIF_SYSREGS);
2122         if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS))
2123                 return false;
2124
2125         return enable_pseudo_nmi;
2126 }
2127
2128 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry,
2129                                       int scope)
2130 {
2131         /*
2132          * If we're not using priority masking then we won't be poking PMR_EL1,
2133          * and there's no need to relax synchronization of writes to it, and
2134          * ICC_CTLR_EL1 might not be accessible and we must avoid reads from
2135          * that.
2136          *
2137          * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU
2138          * feature, so will be detected earlier.
2139          */
2140         BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING);
2141         if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING))
2142                 return false;
2143
2144         /*
2145          * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a
2146          * hint for interrupt distribution, a DSB is not necessary when
2147          * unmasking IRQs via PMR, and we can relax the barrier to a NOP.
2148          *
2149          * Linux itself doesn't use 1:N distribution, so has no need to
2150          * set PMHE. The only reason to have it set is if EL3 requires it
2151          * (and we can't change it).
2152          */
2153         return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0;
2154 }
2155 #endif
2156
2157 #ifdef CONFIG_ARM64_BTI
2158 static void bti_enable(const struct arm64_cpu_capabilities *__unused)
2159 {
2160         /*
2161          * Use of X16/X17 for tail-calls and trampolines that jump to
2162          * function entry points using BR is a requirement for
2163          * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI.
2164          * So, be strict and forbid other BRs using other registers to
2165          * jump onto a PACIxSP instruction:
2166          */
2167         sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1);
2168         isb();
2169 }
2170 #endif /* CONFIG_ARM64_BTI */
2171
2172 #ifdef CONFIG_ARM64_MTE
2173 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap)
2174 {
2175         sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0);
2176
2177         mte_cpu_setup();
2178
2179         /*
2180          * Clear the tags in the zero page. This needs to be done via the
2181          * linear map which has the Tagged attribute.
2182          */
2183         if (try_page_mte_tagging(ZERO_PAGE(0))) {
2184                 mte_clear_page_tags(lm_alias(empty_zero_page));
2185                 set_page_mte_tagged(ZERO_PAGE(0));
2186         }
2187
2188         kasan_init_hw_tags_cpu();
2189 }
2190 #endif /* CONFIG_ARM64_MTE */
2191
2192 static void elf_hwcap_fixup(void)
2193 {
2194 #ifdef CONFIG_ARM64_ERRATUM_1742098
2195         if (cpus_have_const_cap(ARM64_WORKAROUND_1742098))
2196                 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES;
2197 #endif /* ARM64_ERRATUM_1742098 */
2198 }
2199
2200 #ifdef CONFIG_KVM
2201 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused)
2202 {
2203         return kvm_get_mode() == KVM_MODE_PROTECTED;
2204 }
2205 #endif /* CONFIG_KVM */
2206
2207 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused)
2208 {
2209         sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP);
2210 }
2211
2212 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused)
2213 {
2214         set_pstate_dit(1);
2215 }
2216
2217 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused)
2218 {
2219         sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn);
2220 }
2221
2222 /* Internal helper functions to match cpu capability type */
2223 static bool
2224 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
2225 {
2226         return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);
2227 }
2228
2229 static bool
2230 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap)
2231 {
2232         return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);
2233 }
2234
2235 static bool
2236 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap)
2237 {
2238         return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT);
2239 }
2240
2241 static const struct arm64_cpu_capabilities arm64_features[] = {
2242         {
2243                 .capability = ARM64_ALWAYS_BOOT,
2244                 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2245                 .matches = has_always,
2246         },
2247         {
2248                 .capability = ARM64_ALWAYS_SYSTEM,
2249                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2250                 .matches = has_always,
2251         },
2252         {
2253                 .desc = "GIC system register CPU interface",
2254                 .capability = ARM64_HAS_GIC_CPUIF_SYSREGS,
2255                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2256                 .matches = has_useable_gicv3_cpuif,
2257                 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP)
2258         },
2259         {
2260                 .desc = "Enhanced Counter Virtualization",
2261                 .capability = ARM64_HAS_ECV,
2262                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2263                 .matches = has_cpuid_feature,
2264                 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP)
2265         },
2266         {
2267                 .desc = "Enhanced Counter Virtualization (CNTPOFF)",
2268                 .capability = ARM64_HAS_ECV_CNTPOFF,
2269                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2270                 .matches = has_cpuid_feature,
2271                 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF)
2272         },
2273 #ifdef CONFIG_ARM64_PAN
2274         {
2275                 .desc = "Privileged Access Never",
2276                 .capability = ARM64_HAS_PAN,
2277                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2278                 .matches = has_cpuid_feature,
2279                 .cpu_enable = cpu_enable_pan,
2280                 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP)
2281         },
2282 #endif /* CONFIG_ARM64_PAN */
2283 #ifdef CONFIG_ARM64_EPAN
2284         {
2285                 .desc = "Enhanced Privileged Access Never",
2286                 .capability = ARM64_HAS_EPAN,
2287                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2288                 .matches = has_cpuid_feature,
2289                 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3)
2290         },
2291 #endif /* CONFIG_ARM64_EPAN */
2292 #ifdef CONFIG_ARM64_LSE_ATOMICS
2293         {
2294                 .desc = "LSE atomic instructions",
2295                 .capability = ARM64_HAS_LSE_ATOMICS,
2296                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2297                 .matches = has_cpuid_feature,
2298                 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP)
2299         },
2300 #endif /* CONFIG_ARM64_LSE_ATOMICS */
2301         {
2302                 .desc = "Software prefetching using PRFM",
2303                 .capability = ARM64_HAS_NO_HW_PREFETCH,
2304                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2305                 .matches = has_no_hw_prefetch,
2306         },
2307         {
2308                 .desc = "Virtualization Host Extensions",
2309                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
2310                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2311                 .matches = runs_at_el2,
2312                 .cpu_enable = cpu_copy_el2regs,
2313         },
2314         {
2315                 .desc = "Nested Virtualization Support",
2316                 .capability = ARM64_HAS_NESTED_VIRT,
2317                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2318                 .matches = has_nested_virt_support,
2319                 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, IMP)
2320         },
2321         {
2322                 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE,
2323                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2324                 .matches = has_32bit_el0,
2325                 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32)
2326         },
2327 #ifdef CONFIG_KVM
2328         {
2329                 .desc = "32-bit EL1 Support",
2330                 .capability = ARM64_HAS_32BIT_EL1,
2331                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2332                 .matches = has_cpuid_feature,
2333                 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32)
2334         },
2335         {
2336                 .desc = "Protected KVM",
2337                 .capability = ARM64_KVM_PROTECTED_MODE,
2338                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2339                 .matches = is_kvm_protected_mode,
2340         },
2341         {
2342                 .desc = "HCRX_EL2 register",
2343                 .capability = ARM64_HAS_HCX,
2344                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2345                 .matches = has_cpuid_feature,
2346                 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP)
2347         },
2348 #endif
2349         {
2350                 .desc = "Kernel page table isolation (KPTI)",
2351                 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
2352                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
2353                 .cpu_enable = kpti_install_ng_mappings,
2354                 .matches = unmap_kernel_at_el0,
2355                 /*
2356                  * The ID feature fields below are used to indicate that
2357                  * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
2358                  * more details.
2359                  */
2360                 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP)
2361         },
2362         {
2363                 /* FP/SIMD is not implemented */
2364                 .capability = ARM64_HAS_NO_FPSIMD,
2365                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
2366                 .min_field_value = 0,
2367                 .matches = has_no_fpsimd,
2368         },
2369 #ifdef CONFIG_ARM64_PMEM
2370         {
2371                 .desc = "Data cache clean to Point of Persistence",
2372                 .capability = ARM64_HAS_DCPOP,
2373                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2374                 .matches = has_cpuid_feature,
2375                 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP)
2376         },
2377         {
2378                 .desc = "Data cache clean to Point of Deep Persistence",
2379                 .capability = ARM64_HAS_DCPODP,
2380                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2381                 .matches = has_cpuid_feature,
2382                 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2)
2383         },
2384 #endif
2385 #ifdef CONFIG_ARM64_SVE
2386         {
2387                 .desc = "Scalable Vector Extension",
2388                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2389                 .capability = ARM64_SVE,
2390                 .cpu_enable = sve_kernel_enable,
2391                 .matches = has_cpuid_feature,
2392                 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP)
2393         },
2394 #endif /* CONFIG_ARM64_SVE */
2395 #ifdef CONFIG_ARM64_RAS_EXTN
2396         {
2397                 .desc = "RAS Extension Support",
2398                 .capability = ARM64_HAS_RAS_EXTN,
2399                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2400                 .matches = has_cpuid_feature,
2401                 .cpu_enable = cpu_clear_disr,
2402                 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP)
2403         },
2404 #endif /* CONFIG_ARM64_RAS_EXTN */
2405 #ifdef CONFIG_ARM64_AMU_EXTN
2406         {
2407                 /*
2408                  * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y.
2409                  * Therefore, don't provide .desc as we don't want the detection
2410                  * message to be shown until at least one CPU is detected to
2411                  * support the feature.
2412                  */
2413                 .capability = ARM64_HAS_AMU_EXTN,
2414                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2415                 .matches = has_amu,
2416                 .cpu_enable = cpu_amu_enable,
2417                 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP)
2418         },
2419 #endif /* CONFIG_ARM64_AMU_EXTN */
2420         {
2421                 .desc = "Data cache clean to the PoU not required for I/D coherence",
2422                 .capability = ARM64_HAS_CACHE_IDC,
2423                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2424                 .matches = has_cache_idc,
2425                 .cpu_enable = cpu_emulate_effective_ctr,
2426         },
2427         {
2428                 .desc = "Instruction cache invalidation not required for I/D coherence",
2429                 .capability = ARM64_HAS_CACHE_DIC,
2430                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2431                 .matches = has_cache_dic,
2432         },
2433         {
2434                 .desc = "Stage-2 Force Write-Back",
2435                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2436                 .capability = ARM64_HAS_STAGE2_FWB,
2437                 .matches = has_cpuid_feature,
2438                 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP)
2439         },
2440         {
2441                 .desc = "ARMv8.4 Translation Table Level",
2442                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2443                 .capability = ARM64_HAS_ARMv8_4_TTL,
2444                 .matches = has_cpuid_feature,
2445                 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP)
2446         },
2447         {
2448                 .desc = "TLB range maintenance instructions",
2449                 .capability = ARM64_HAS_TLB_RANGE,
2450                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2451                 .matches = has_cpuid_feature,
2452                 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE)
2453         },
2454 #ifdef CONFIG_ARM64_HW_AFDBM
2455         {
2456                 /*
2457                  * Since we turn this on always, we don't want the user to
2458                  * think that the feature is available when it may not be.
2459                  * So hide the description.
2460                  *
2461                  * .desc = "Hardware pagetable Dirty Bit Management",
2462                  *
2463                  */
2464                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2465                 .capability = ARM64_HW_DBM,
2466                 .matches = has_hw_dbm,
2467                 .cpu_enable = cpu_enable_hw_dbm,
2468                 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM)
2469         },
2470 #endif
2471         {
2472                 .desc = "CRC32 instructions",
2473                 .capability = ARM64_HAS_CRC32,
2474                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2475                 .matches = has_cpuid_feature,
2476                 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP)
2477         },
2478         {
2479                 .desc = "Speculative Store Bypassing Safe (SSBS)",
2480                 .capability = ARM64_SSBS,
2481                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2482                 .matches = has_cpuid_feature,
2483                 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP)
2484         },
2485 #ifdef CONFIG_ARM64_CNP
2486         {
2487                 .desc = "Common not Private translations",
2488                 .capability = ARM64_HAS_CNP,
2489                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2490                 .matches = has_useable_cnp,
2491                 .cpu_enable = cpu_enable_cnp,
2492                 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP)
2493         },
2494 #endif
2495         {
2496                 .desc = "Speculation barrier (SB)",
2497                 .capability = ARM64_HAS_SB,
2498                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2499                 .matches = has_cpuid_feature,
2500                 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP)
2501         },
2502 #ifdef CONFIG_ARM64_PTR_AUTH
2503         {
2504                 .desc = "Address authentication (architected QARMA5 algorithm)",
2505                 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5,
2506                 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2507                 .matches = has_address_auth_cpucap,
2508                 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth)
2509         },
2510         {
2511                 .desc = "Address authentication (architected QARMA3 algorithm)",
2512                 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3,
2513                 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2514                 .matches = has_address_auth_cpucap,
2515                 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth)
2516         },
2517         {
2518                 .desc = "Address authentication (IMP DEF algorithm)",
2519                 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
2520                 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2521                 .matches = has_address_auth_cpucap,
2522                 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth)
2523         },
2524         {
2525                 .capability = ARM64_HAS_ADDRESS_AUTH,
2526                 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2527                 .matches = has_address_auth_metacap,
2528         },
2529         {
2530                 .desc = "Generic authentication (architected QARMA5 algorithm)",
2531                 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5,
2532                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2533                 .matches = has_cpuid_feature,
2534                 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP)
2535         },
2536         {
2537                 .desc = "Generic authentication (architected QARMA3 algorithm)",
2538                 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3,
2539                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2540                 .matches = has_cpuid_feature,
2541                 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP)
2542         },
2543         {
2544                 .desc = "Generic authentication (IMP DEF algorithm)",
2545                 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
2546                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2547                 .matches = has_cpuid_feature,
2548                 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP)
2549         },
2550         {
2551                 .capability = ARM64_HAS_GENERIC_AUTH,
2552                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2553                 .matches = has_generic_auth,
2554         },
2555 #endif /* CONFIG_ARM64_PTR_AUTH */
2556 #ifdef CONFIG_ARM64_PSEUDO_NMI
2557         {
2558                 /*
2559                  * Depends on having GICv3
2560                  */
2561                 .desc = "IRQ priority masking",
2562                 .capability = ARM64_HAS_GIC_PRIO_MASKING,
2563                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2564                 .matches = can_use_gic_priorities,
2565         },
2566         {
2567                 /*
2568                  * Depends on ARM64_HAS_GIC_PRIO_MASKING
2569                  */
2570                 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC,
2571                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2572                 .matches = has_gic_prio_relaxed_sync,
2573         },
2574 #endif
2575 #ifdef CONFIG_ARM64_E0PD
2576         {
2577                 .desc = "E0PD",
2578                 .capability = ARM64_HAS_E0PD,
2579                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2580                 .cpu_enable = cpu_enable_e0pd,
2581                 .matches = has_cpuid_feature,
2582                 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP)
2583         },
2584 #endif
2585         {
2586                 .desc = "Random Number Generator",
2587                 .capability = ARM64_HAS_RNG,
2588                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2589                 .matches = has_cpuid_feature,
2590                 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP)
2591         },
2592 #ifdef CONFIG_ARM64_BTI
2593         {
2594                 .desc = "Branch Target Identification",
2595                 .capability = ARM64_BTI,
2596 #ifdef CONFIG_ARM64_BTI_KERNEL
2597                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2598 #else
2599                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2600 #endif
2601                 .matches = has_cpuid_feature,
2602                 .cpu_enable = bti_enable,
2603                 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP)
2604         },
2605 #endif
2606 #ifdef CONFIG_ARM64_MTE
2607         {
2608                 .desc = "Memory Tagging Extension",
2609                 .capability = ARM64_MTE,
2610                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2611                 .matches = has_cpuid_feature,
2612                 .cpu_enable = cpu_enable_mte,
2613                 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2)
2614         },
2615         {
2616                 .desc = "Asymmetric MTE Tag Check Fault",
2617                 .capability = ARM64_MTE_ASYMM,
2618                 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2619                 .matches = has_cpuid_feature,
2620                 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3)
2621         },
2622 #endif /* CONFIG_ARM64_MTE */
2623         {
2624                 .desc = "RCpc load-acquire (LDAPR)",
2625                 .capability = ARM64_HAS_LDAPR,
2626                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2627                 .matches = has_cpuid_feature,
2628                 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP)
2629         },
2630 #ifdef CONFIG_ARM64_SME
2631         {
2632                 .desc = "Scalable Matrix Extension",
2633                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2634                 .capability = ARM64_SME,
2635                 .matches = has_cpuid_feature,
2636                 .cpu_enable = sme_kernel_enable,
2637                 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP)
2638         },
2639         /* FA64 should be sorted after the base SME capability */
2640         {
2641                 .desc = "FA64",
2642                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2643                 .capability = ARM64_SME_FA64,
2644                 .matches = has_cpuid_feature,
2645                 .cpu_enable = fa64_kernel_enable,
2646                 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP)
2647         },
2648         {
2649                 .desc = "SME2",
2650                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2651                 .capability = ARM64_SME2,
2652                 .matches = has_cpuid_feature,
2653                 .cpu_enable = sme2_kernel_enable,
2654                 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2)
2655         },
2656 #endif /* CONFIG_ARM64_SME */
2657         {
2658                 .desc = "WFx with timeout",
2659                 .capability = ARM64_HAS_WFXT,
2660                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2661                 .matches = has_cpuid_feature,
2662                 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP)
2663         },
2664         {
2665                 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality",
2666                 .capability = ARM64_HAS_TIDCP1,
2667                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2668                 .matches = has_cpuid_feature,
2669                 .cpu_enable = cpu_trap_el0_impdef,
2670                 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP)
2671         },
2672         {
2673                 .desc = "Data independent timing control (DIT)",
2674                 .capability = ARM64_HAS_DIT,
2675                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2676                 .matches = has_cpuid_feature,
2677                 .cpu_enable = cpu_enable_dit,
2678                 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP)
2679         },
2680         {
2681                 .desc = "Memory Copy and Memory Set instructions",
2682                 .capability = ARM64_HAS_MOPS,
2683                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2684                 .matches = has_cpuid_feature,
2685                 .cpu_enable = cpu_enable_mops,
2686                 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP)
2687         },
2688         {
2689                 .capability = ARM64_HAS_TCR2,
2690                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2691                 .matches = has_cpuid_feature,
2692                 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP)
2693         },
2694         {
2695                 .desc = "Stage-1 Permission Indirection Extension (S1PIE)",
2696                 .capability = ARM64_HAS_S1PIE,
2697                 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2698                 .matches = has_cpuid_feature,
2699                 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP)
2700         },
2701         {
2702                 .desc = "VHE for hypervisor only",
2703                 .capability = ARM64_KVM_HVHE,
2704                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2705                 .matches = hvhe_possible,
2706         },
2707         {
2708                 .desc = "Enhanced Virtualization Traps",
2709                 .capability = ARM64_HAS_EVT,
2710                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2711                 .matches = has_cpuid_feature,
2712                 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP)
2713         },
2714         {},
2715 };
2716
2717 #define HWCAP_CPUID_MATCH(reg, field, min_value)                        \
2718                 .matches = has_user_cpuid_feature,                      \
2719                 ARM64_CPUID_FIELDS(reg, field, min_value)
2720
2721 #define __HWCAP_CAP(name, cap_type, cap)                                        \
2722                 .desc = name,                                                   \
2723                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,                            \
2724                 .hwcap_type = cap_type,                                         \
2725                 .hwcap = cap,                                                   \
2726
2727 #define HWCAP_CAP(reg, field, min_value, cap_type, cap)         \
2728         {                                                                       \
2729                 __HWCAP_CAP(#cap, cap_type, cap)                                \
2730                 HWCAP_CPUID_MATCH(reg, field, min_value)                \
2731         }
2732
2733 #define HWCAP_MULTI_CAP(list, cap_type, cap)                                    \
2734         {                                                                       \
2735                 __HWCAP_CAP(#cap, cap_type, cap)                                \
2736                 .matches = cpucap_multi_entry_cap_matches,                      \
2737                 .match_list = list,                                             \
2738         }
2739
2740 #define HWCAP_CAP_MATCH(match, cap_type, cap)                                   \
2741         {                                                                       \
2742                 __HWCAP_CAP(#cap, cap_type, cap)                                \
2743                 .matches = match,                                               \
2744         }
2745
2746 #ifdef CONFIG_ARM64_PTR_AUTH
2747 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
2748         {
2749                 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth)
2750         },
2751         {
2752                 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth)
2753         },
2754         {
2755                 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth)
2756         },
2757         {},
2758 };
2759
2760 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
2761         {
2762                 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP)
2763         },
2764         {
2765                 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP)
2766         },
2767         {
2768                 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP)
2769         },
2770         {},
2771 };
2772 #endif
2773
2774 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
2775         HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL),
2776         HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES),
2777         HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1),
2778         HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2),
2779         HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512),
2780         HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32),
2781         HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
2782         HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
2783         HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3),
2784         HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3),
2785         HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4),
2786         HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
2787         HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
2788         HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
2789         HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
2790         HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG),
2791         HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP),
2792         HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP),
2793         HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
2794         HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
2795         HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT),
2796         HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
2797         HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
2798         HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
2799         HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA),
2800         HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
2801         HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
2802         HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT),
2803         HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB),
2804         HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16),
2805         HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16),
2806         HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH),
2807         HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM),
2808         HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT),
2809 #ifdef CONFIG_ARM64_SVE
2810         HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE),
2811         HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1),
2812         HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
2813         HWCAP_CAP(ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
2814         HWCAP_CAP(ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
2815         HWCAP_CAP(ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
2816         HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
2817         HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16),
2818         HWCAP_CAP(ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
2819         HWCAP_CAP(ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
2820         HWCAP_CAP(ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
2821         HWCAP_CAP(ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
2822         HWCAP_CAP(ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
2823 #endif
2824         HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS),
2825 #ifdef CONFIG_ARM64_BTI
2826         HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI),
2827 #endif
2828 #ifdef CONFIG_ARM64_PTR_AUTH
2829         HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
2830         HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
2831 #endif
2832 #ifdef CONFIG_ARM64_MTE
2833         HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE),
2834         HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3),
2835 #endif /* CONFIG_ARM64_MTE */
2836         HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV),
2837         HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP),
2838         HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC),
2839         HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM),
2840         HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES),
2841         HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),
2842         HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS),
2843         HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC),
2844 #ifdef CONFIG_ARM64_SME
2845         HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME),
2846         HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64),
2847         HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1),
2848         HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2),
2849         HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64),
2850         HWCAP_CAP(ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64),
2851         HWCAP_CAP(ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32),
2852         HWCAP_CAP(ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16),
2853         HWCAP_CAP(ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16),
2854         HWCAP_CAP(ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32),
2855         HWCAP_CAP(ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32),
2856         HWCAP_CAP(ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32),
2857         HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32),
2858         HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32),
2859 #endif /* CONFIG_ARM64_SME */
2860         {},
2861 };
2862
2863 #ifdef CONFIG_COMPAT
2864 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
2865 {
2866         /*
2867          * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
2868          * in line with that of arm32 as in vfp_init(). We make sure that the
2869          * check is future proof, by making sure value is non-zero.
2870          */
2871         u32 mvfr1;
2872
2873         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
2874         if (scope == SCOPE_SYSTEM)
2875                 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
2876         else
2877                 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
2878
2879         return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) &&
2880                 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) &&
2881                 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT);
2882 }
2883 #endif
2884
2885 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
2886 #ifdef CONFIG_COMPAT
2887         HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
2888         HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
2889         /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
2890         HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
2891         HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
2892         HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP),
2893         HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP),
2894         HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
2895         HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
2896         HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
2897         HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
2898         HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
2899         HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP),
2900         HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM),
2901         HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB),
2902         HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16),
2903         HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM),
2904         HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS),
2905 #endif
2906         {},
2907 };
2908
2909 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2910 {
2911         switch (cap->hwcap_type) {
2912         case CAP_HWCAP:
2913                 cpu_set_feature(cap->hwcap);
2914                 break;
2915 #ifdef CONFIG_COMPAT
2916         case CAP_COMPAT_HWCAP:
2917                 compat_elf_hwcap |= (u32)cap->hwcap;
2918                 break;
2919         case CAP_COMPAT_HWCAP2:
2920                 compat_elf_hwcap2 |= (u32)cap->hwcap;
2921                 break;
2922 #endif
2923         default:
2924                 WARN_ON(1);
2925                 break;
2926         }
2927 }
2928
2929 /* Check if we have a particular HWCAP enabled */
2930 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2931 {
2932         bool rc;
2933
2934         switch (cap->hwcap_type) {
2935         case CAP_HWCAP:
2936                 rc = cpu_have_feature(cap->hwcap);
2937                 break;
2938 #ifdef CONFIG_COMPAT
2939         case CAP_COMPAT_HWCAP:
2940                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
2941                 break;
2942         case CAP_COMPAT_HWCAP2:
2943                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
2944                 break;
2945 #endif
2946         default:
2947                 WARN_ON(1);
2948                 rc = false;
2949         }
2950
2951         return rc;
2952 }
2953
2954 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
2955 {
2956         /* We support emulation of accesses to CPU ID feature registers */
2957         cpu_set_named_feature(CPUID);
2958         for (; hwcaps->matches; hwcaps++)
2959                 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
2960                         cap_set_elf_hwcap(hwcaps);
2961 }
2962
2963 static void update_cpu_capabilities(u16 scope_mask)
2964 {
2965         int i;
2966         const struct arm64_cpu_capabilities *caps;
2967
2968         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2969         for (i = 0; i < ARM64_NCAPS; i++) {
2970                 caps = cpucap_ptrs[i];
2971                 if (!caps || !(caps->type & scope_mask) ||
2972                     cpus_have_cap(caps->capability) ||
2973                     !caps->matches(caps, cpucap_default_scope(caps)))
2974                         continue;
2975
2976                 if (caps->desc)
2977                         pr_info("detected: %s\n", caps->desc);
2978
2979                 __set_bit(caps->capability, system_cpucaps);
2980
2981                 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
2982                         set_bit(caps->capability, boot_cpucaps);
2983         }
2984 }
2985
2986 /*
2987  * Enable all the available capabilities on this CPU. The capabilities
2988  * with BOOT_CPU scope are handled separately and hence skipped here.
2989  */
2990 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
2991 {
2992         int i;
2993         u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
2994
2995         for_each_available_cap(i) {
2996                 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i];
2997
2998                 if (WARN_ON(!cap))
2999                         continue;
3000
3001                 if (!(cap->type & non_boot_scope))
3002                         continue;
3003
3004                 if (cap->cpu_enable)
3005                         cap->cpu_enable(cap);
3006         }
3007         return 0;
3008 }
3009
3010 /*
3011  * Run through the enabled capabilities and enable() it on all active
3012  * CPUs
3013  */
3014 static void __init enable_cpu_capabilities(u16 scope_mask)
3015 {
3016         int i;
3017         const struct arm64_cpu_capabilities *caps;
3018         bool boot_scope;
3019
3020         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
3021         boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
3022
3023         for (i = 0; i < ARM64_NCAPS; i++) {
3024                 unsigned int num;
3025
3026                 caps = cpucap_ptrs[i];
3027                 if (!caps || !(caps->type & scope_mask))
3028                         continue;
3029                 num = caps->capability;
3030                 if (!cpus_have_cap(num))
3031                         continue;
3032
3033                 if (boot_scope && caps->cpu_enable)
3034                         /*
3035                          * Capabilities with SCOPE_BOOT_CPU scope are finalised
3036                          * before any secondary CPU boots. Thus, each secondary
3037                          * will enable the capability as appropriate via
3038                          * check_local_cpu_capabilities(). The only exception is
3039                          * the boot CPU, for which the capability must be
3040                          * enabled here. This approach avoids costly
3041                          * stop_machine() calls for this case.
3042                          */
3043                         caps->cpu_enable(caps);
3044         }
3045
3046         /*
3047          * For all non-boot scope capabilities, use stop_machine()
3048          * as it schedules the work allowing us to modify PSTATE,
3049          * instead of on_each_cpu() which uses an IPI, giving us a
3050          * PSTATE that disappears when we return.
3051          */
3052         if (!boot_scope)
3053                 stop_machine(cpu_enable_non_boot_scope_capabilities,
3054                              NULL, cpu_online_mask);
3055 }
3056
3057 /*
3058  * Run through the list of capabilities to check for conflicts.
3059  * If the system has already detected a capability, take necessary
3060  * action on this CPU.
3061  */
3062 static void verify_local_cpu_caps(u16 scope_mask)
3063 {
3064         int i;
3065         bool cpu_has_cap, system_has_cap;
3066         const struct arm64_cpu_capabilities *caps;
3067
3068         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
3069
3070         for (i = 0; i < ARM64_NCAPS; i++) {
3071                 caps = cpucap_ptrs[i];
3072                 if (!caps || !(caps->type & scope_mask))
3073                         continue;
3074
3075                 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
3076                 system_has_cap = cpus_have_cap(caps->capability);
3077
3078                 if (system_has_cap) {
3079                         /*
3080                          * Check if the new CPU misses an advertised feature,
3081                          * which is not safe to miss.
3082                          */
3083                         if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
3084                                 break;
3085                         /*
3086                          * We have to issue cpu_enable() irrespective of
3087                          * whether the CPU has it or not, as it is enabeld
3088                          * system wide. It is upto the call back to take
3089                          * appropriate action on this CPU.
3090                          */
3091                         if (caps->cpu_enable)
3092                                 caps->cpu_enable(caps);
3093                 } else {
3094                         /*
3095                          * Check if the CPU has this capability if it isn't
3096                          * safe to have when the system doesn't.
3097                          */
3098                         if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
3099                                 break;
3100                 }
3101         }
3102
3103         if (i < ARM64_NCAPS) {
3104                 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
3105                         smp_processor_id(), caps->capability,
3106                         caps->desc, system_has_cap, cpu_has_cap);
3107
3108                 if (cpucap_panic_on_conflict(caps))
3109                         cpu_panic_kernel();
3110                 else
3111                         cpu_die_early();
3112         }
3113 }
3114
3115 /*
3116  * Check for CPU features that are used in early boot
3117  * based on the Boot CPU value.
3118  */
3119 static void check_early_cpu_features(void)
3120 {
3121         verify_cpu_asid_bits();
3122
3123         verify_local_cpu_caps(SCOPE_BOOT_CPU);
3124 }
3125
3126 static void
3127 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
3128 {
3129
3130         for (; caps->matches; caps++)
3131                 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
3132                         pr_crit("CPU%d: missing HWCAP: %s\n",
3133                                         smp_processor_id(), caps->desc);
3134                         cpu_die_early();
3135                 }
3136 }
3137
3138 static void verify_local_elf_hwcaps(void)
3139 {
3140         __verify_local_elf_hwcaps(arm64_elf_hwcaps);
3141
3142         if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1)))
3143                 __verify_local_elf_hwcaps(compat_elf_hwcaps);
3144 }
3145
3146 static void verify_sve_features(void)
3147 {
3148         u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
3149         u64 zcr = read_zcr_features();
3150
3151         unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
3152         unsigned int len = zcr & ZCR_ELx_LEN_MASK;
3153
3154         if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SVE)) {
3155                 pr_crit("CPU%d: SVE: vector length support mismatch\n",
3156                         smp_processor_id());
3157                 cpu_die_early();
3158         }
3159
3160         /* Add checks on other ZCR bits here if necessary */
3161 }
3162
3163 static void verify_sme_features(void)
3164 {
3165         u64 safe_smcr = read_sanitised_ftr_reg(SYS_SMCR_EL1);
3166         u64 smcr = read_smcr_features();
3167
3168         unsigned int safe_len = safe_smcr & SMCR_ELx_LEN_MASK;
3169         unsigned int len = smcr & SMCR_ELx_LEN_MASK;
3170
3171         if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SME)) {
3172                 pr_crit("CPU%d: SME: vector length support mismatch\n",
3173                         smp_processor_id());
3174                 cpu_die_early();
3175         }
3176
3177         /* Add checks on other SMCR bits here if necessary */
3178 }
3179
3180 static void verify_hyp_capabilities(void)
3181 {
3182         u64 safe_mmfr1, mmfr0, mmfr1;
3183         int parange, ipa_max;
3184         unsigned int safe_vmid_bits, vmid_bits;
3185
3186         if (!IS_ENABLED(CONFIG_KVM))
3187                 return;
3188
3189         safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
3190         mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
3191         mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
3192
3193         /* Verify VMID bits */
3194         safe_vmid_bits = get_vmid_bits(safe_mmfr1);
3195         vmid_bits = get_vmid_bits(mmfr1);
3196         if (vmid_bits < safe_vmid_bits) {
3197                 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id());
3198                 cpu_die_early();
3199         }
3200
3201         /* Verify IPA range */
3202         parange = cpuid_feature_extract_unsigned_field(mmfr0,
3203                                 ID_AA64MMFR0_EL1_PARANGE_SHIFT);
3204         ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange);
3205         if (ipa_max < get_kvm_ipa_limit()) {
3206                 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id());
3207                 cpu_die_early();
3208         }
3209 }
3210
3211 /*
3212  * Run through the enabled system capabilities and enable() it on this CPU.
3213  * The capabilities were decided based on the available CPUs at the boot time.
3214  * Any new CPU should match the system wide status of the capability. If the
3215  * new CPU doesn't have a capability which the system now has enabled, we
3216  * cannot do anything to fix it up and could cause unexpected failures. So
3217  * we park the CPU.
3218  */
3219 static void verify_local_cpu_capabilities(void)
3220 {
3221         /*
3222          * The capabilities with SCOPE_BOOT_CPU are checked from
3223          * check_early_cpu_features(), as they need to be verified
3224          * on all secondary CPUs.
3225          */
3226         verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU);
3227         verify_local_elf_hwcaps();
3228
3229         if (system_supports_sve())
3230                 verify_sve_features();
3231
3232         if (system_supports_sme())
3233                 verify_sme_features();
3234
3235         if (is_hyp_mode_available())
3236                 verify_hyp_capabilities();
3237 }
3238
3239 void check_local_cpu_capabilities(void)
3240 {
3241         /*
3242          * All secondary CPUs should conform to the early CPU features
3243          * in use by the kernel based on boot CPU.
3244          */
3245         check_early_cpu_features();
3246
3247         /*
3248          * If we haven't finalised the system capabilities, this CPU gets
3249          * a chance to update the errata work arounds and local features.
3250          * Otherwise, this CPU should verify that it has all the system
3251          * advertised capabilities.
3252          */
3253         if (!system_capabilities_finalized())
3254                 update_cpu_capabilities(SCOPE_LOCAL_CPU);
3255         else
3256                 verify_local_cpu_capabilities();
3257 }
3258
3259 static void __init setup_boot_cpu_capabilities(void)
3260 {
3261         /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
3262         update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
3263         /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
3264         enable_cpu_capabilities(SCOPE_BOOT_CPU);
3265 }
3266
3267 bool this_cpu_has_cap(unsigned int n)
3268 {
3269         if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
3270                 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n];
3271
3272                 if (cap)
3273                         return cap->matches(cap, SCOPE_LOCAL_CPU);
3274         }
3275
3276         return false;
3277 }
3278 EXPORT_SYMBOL_GPL(this_cpu_has_cap);
3279
3280 /*
3281  * This helper function is used in a narrow window when,
3282  * - The system wide safe registers are set with all the SMP CPUs and,
3283  * - The SYSTEM_FEATURE system_cpucaps may not have been set.
3284  * In all other cases cpus_have_{const_}cap() should be used.
3285  */
3286 static bool __maybe_unused __system_matches_cap(unsigned int n)
3287 {
3288         if (n < ARM64_NCAPS) {
3289                 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n];
3290
3291                 if (cap)
3292                         return cap->matches(cap, SCOPE_SYSTEM);
3293         }
3294         return false;
3295 }
3296
3297 void cpu_set_feature(unsigned int num)
3298 {
3299         set_bit(num, elf_hwcap);
3300 }
3301
3302 bool cpu_have_feature(unsigned int num)
3303 {
3304         return test_bit(num, elf_hwcap);
3305 }
3306 EXPORT_SYMBOL_GPL(cpu_have_feature);
3307
3308 unsigned long cpu_get_elf_hwcap(void)
3309 {
3310         /*
3311          * We currently only populate the first 32 bits of AT_HWCAP. Please
3312          * note that for userspace compatibility we guarantee that bits 62
3313          * and 63 will always be returned as 0.
3314          */
3315         return elf_hwcap[0];
3316 }
3317
3318 unsigned long cpu_get_elf_hwcap2(void)
3319 {
3320         return elf_hwcap[1];
3321 }
3322
3323 static void __init setup_system_capabilities(void)
3324 {
3325         /*
3326          * We have finalised the system-wide safe feature
3327          * registers, finalise the capabilities that depend
3328          * on it. Also enable all the available capabilities,
3329          * that are not enabled already.
3330          */
3331         update_cpu_capabilities(SCOPE_SYSTEM);
3332         enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
3333 }
3334
3335 void __init setup_cpu_features(void)
3336 {
3337         u32 cwg;
3338
3339         setup_system_capabilities();
3340         setup_elf_hwcaps(arm64_elf_hwcaps);
3341
3342         if (system_supports_32bit_el0()) {
3343                 setup_elf_hwcaps(compat_elf_hwcaps);
3344                 elf_hwcap_fixup();
3345         }
3346
3347         if (system_uses_ttbr0_pan())
3348                 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
3349
3350         sve_setup();
3351         sme_setup();
3352         minsigstksz_setup();
3353
3354         /*
3355          * Check for sane CTR_EL0.CWG value.
3356          */
3357         cwg = cache_type_cwg();
3358         if (!cwg)
3359                 pr_warn("No Cache Writeback Granule information, assuming %d\n",
3360                         ARCH_DMA_MINALIGN);
3361 }
3362
3363 static int enable_mismatched_32bit_el0(unsigned int cpu)
3364 {
3365         /*
3366          * The first 32-bit-capable CPU we detected and so can no longer
3367          * be offlined by userspace. -1 indicates we haven't yet onlined
3368          * a 32-bit-capable CPU.
3369          */
3370         static int lucky_winner = -1;
3371
3372         struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
3373         bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0);
3374
3375         if (cpu_32bit) {
3376                 cpumask_set_cpu(cpu, cpu_32bit_el0_mask);
3377                 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0);
3378         }
3379
3380         if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit)
3381                 return 0;
3382
3383         if (lucky_winner >= 0)
3384                 return 0;
3385
3386         /*
3387          * We've detected a mismatch. We need to keep one of our CPUs with
3388          * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting
3389          * every CPU in the system for a 32-bit task.
3390          */
3391         lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask,
3392                                                          cpu_active_mask);
3393         get_cpu_device(lucky_winner)->offline_disabled = true;
3394         setup_elf_hwcaps(compat_elf_hwcaps);
3395         elf_hwcap_fixup();
3396         pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n",
3397                 cpu, lucky_winner);
3398         return 0;
3399 }
3400
3401 static int __init init_32bit_el0_mask(void)
3402 {
3403         if (!allow_mismatched_32bit_el0)
3404                 return 0;
3405
3406         if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL))
3407                 return -ENOMEM;
3408
3409         return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
3410                                  "arm64/mismatched_32bit_el0:online",
3411                                  enable_mismatched_32bit_el0, NULL);
3412 }
3413 subsys_initcall_sync(init_32bit_el0_mask);
3414
3415 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
3416 {
3417         cpu_replace_ttbr1(lm_alias(swapper_pg_dir), idmap_pg_dir);
3418 }
3419
3420 /*
3421  * We emulate only the following system register space.
3422  * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7]
3423  * See Table C5-6 System instruction encodings for System register accesses,
3424  * ARMv8 ARM(ARM DDI 0487A.f) for more details.
3425  */
3426 static inline bool __attribute_const__ is_emulated(u32 id)
3427 {
3428         return (sys_reg_Op0(id) == 0x3 &&
3429                 sys_reg_CRn(id) == 0x0 &&
3430                 sys_reg_Op1(id) == 0x0 &&
3431                 (sys_reg_CRm(id) == 0 ||
3432                  ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7))));
3433 }
3434
3435 /*
3436  * With CRm == 0, reg should be one of :
3437  * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
3438  */
3439 static inline int emulate_id_reg(u32 id, u64 *valp)
3440 {
3441         switch (id) {
3442         case SYS_MIDR_EL1:
3443                 *valp = read_cpuid_id();
3444                 break;
3445         case SYS_MPIDR_EL1:
3446                 *valp = SYS_MPIDR_SAFE_VAL;
3447                 break;
3448         case SYS_REVIDR_EL1:
3449                 /* IMPLEMENTATION DEFINED values are emulated with 0 */
3450                 *valp = 0;
3451                 break;
3452         default:
3453                 return -EINVAL;
3454         }
3455
3456         return 0;
3457 }
3458
3459 static int emulate_sys_reg(u32 id, u64 *valp)
3460 {
3461         struct arm64_ftr_reg *regp;
3462
3463         if (!is_emulated(id))
3464                 return -EINVAL;
3465
3466         if (sys_reg_CRm(id) == 0)
3467                 return emulate_id_reg(id, valp);
3468
3469         regp = get_arm64_ftr_reg_nowarn(id);
3470         if (regp)
3471                 *valp = arm64_ftr_reg_user_value(regp);
3472         else
3473                 /*
3474                  * The untracked registers are either IMPLEMENTATION DEFINED
3475                  * (e.g, ID_AFR0_EL1) or reserved RAZ.
3476                  */
3477                 *valp = 0;
3478         return 0;
3479 }
3480
3481 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
3482 {
3483         int rc;
3484         u64 val;
3485
3486         rc = emulate_sys_reg(sys_reg, &val);
3487         if (!rc) {
3488                 pt_regs_write_reg(regs, rt, val);
3489                 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
3490         }
3491         return rc;
3492 }
3493
3494 bool try_emulate_mrs(struct pt_regs *regs, u32 insn)
3495 {
3496         u32 sys_reg, rt;
3497
3498         if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn))
3499                 return false;
3500
3501         /*
3502          * sys_reg values are defined as used in mrs/msr instruction.
3503          * shift the imm value to get the encoding.
3504          */
3505         sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
3506         rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
3507         return do_emulate_mrs(regs, sys_reg, rt) == 0;
3508 }
3509
3510 enum mitigation_state arm64_get_meltdown_state(void)
3511 {
3512         if (__meltdown_safe)
3513                 return SPECTRE_UNAFFECTED;
3514
3515         if (arm64_kernel_unmapped_at_el0())
3516                 return SPECTRE_MITIGATED;
3517
3518         return SPECTRE_VULNERABLE;
3519 }
3520
3521 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
3522                           char *buf)
3523 {
3524         switch (arm64_get_meltdown_state()) {
3525         case SPECTRE_UNAFFECTED:
3526                 return sprintf(buf, "Not affected\n");
3527
3528         case SPECTRE_MITIGATED:
3529                 return sprintf(buf, "Mitigation: PTI\n");
3530
3531         default:
3532                 return sprintf(buf, "Vulnerable\n");
3533         }
3534 }