arch/arm64/kernel/cpufeature.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Contains CPU feature definitions
   4  *
   5  * Copyright (C) 2015 ARM Ltd.
   6  */
   7
   8 #define pr_fmt(fmt) "CPU features: " fmt
   9
  10 #include <linux/bsearch.h>
  11 #include <linux/cpumask.h>
  12 #include <linux/crash_dump.h>
  13 #include <linux/sort.h>
  14 #include <linux/stop_machine.h>
  15 #include <linux/types.h>
  16 #include <linux/mm.h>
  17 #include <linux/cpu.h>
  18 #include <asm/cpu.h>
  19 #include <asm/cpufeature.h>
  20 #include <asm/cpu_ops.h>
  21 #include <asm/fpsimd.h>
  22 #include <asm/mmu_context.h>
  23 #include <asm/processor.h>
  24 #include <asm/sysreg.h>
  25 #include <asm/traps.h>
  26 #include <asm/virt.h>
  27
  28 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
  29 static unsigned long elf_hwcap __read_mostly;
  30
  31 #ifdef CONFIG_COMPAT
  32 #define COMPAT_ELF_HWCAP_DEFAULT        \
  33                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  34                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  35                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
  36                                  COMPAT_HWCAP_LPAE)
  37 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  38 unsigned int compat_elf_hwcap2 __read_mostly;
  39 #endif
  40
  41 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  42 EXPORT_SYMBOL(cpu_hwcaps);
  43 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
  44
  45 /* Need also bit for ARM64_CB_PATCH */
  46 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
  47
  48 /*
  49  * Flag to indicate if we have computed the system wide
  50  * capabilities based on the boot time active CPUs. This
  51  * will be used to determine if a new booting CPU should
  52  * go through the verification process to make sure that it
  53  * supports the system capabilities, without using a hotplug
  54  * notifier. This is also used to decide if we could use
  55  * the fast path for checking constant CPU caps.
  56  */
  57 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
  58 EXPORT_SYMBOL(arm64_const_caps_ready);
  59 static inline void finalize_system_capabilities(void)
  60 {
  61         static_branch_enable(&arm64_const_caps_ready);
  62 }
  63
  64 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
  65 {
  66         /* file-wide pr_fmt adds "CPU features: " prefix */
  67         pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
  68         return 0;
  69 }
  70
  71 static struct notifier_block cpu_hwcaps_notifier = {
  72         .notifier_call = dump_cpu_hwcaps
  73 };
  74
  75 static int __init register_cpu_hwcaps_dumper(void)
  76 {
  77         atomic_notifier_chain_register(&panic_notifier_list,
  78                                        &cpu_hwcaps_notifier);
  79         return 0;
  80 }
  81 __initcall(register_cpu_hwcaps_dumper);
  82
  83 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
  84 EXPORT_SYMBOL(cpu_hwcap_keys);
  85
  86 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  87         {                                               \
  88                 .sign = SIGNED,                         \
  89                 .visible = VISIBLE,                     \
  90                 .strict = STRICT,                       \
  91                 .type = TYPE,                           \
  92                 .shift = SHIFT,                         \
  93                 .width = WIDTH,                         \
  94                 .safe_val = SAFE_VAL,                   \
  95         }
  96
  97 /* Define a feature with unsigned values */
  98 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  99         __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 100
 101 /* Define a feature with a signed value */
 102 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 103         __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 104
 105 #define ARM64_FTR_END                                   \
 106         {                                               \
 107                 .width = 0,                             \
 108         }
 109
 110 /* meta feature for alternatives */
 111 static bool __maybe_unused
 112 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
 113
 114 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
 115
 116 /*
 117  * NOTE: Any changes to the visibility of features should be kept in
 118  * sync with the documentation of the CPU feature register ABI.
 119  */
 120 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
 121         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
 122         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
 123         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
 124         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
 125         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
 126         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
 127         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
 128         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
 129         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
 130         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
 131         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
 132         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
 133         ARM64_FTR_END,
 134 };
 135
 136 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
 137         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
 138         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
 139         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 140                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
 141         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 142                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
 143         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
 144         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
 145         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
 146         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 147                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0),
 148         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 149                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0),
 150         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
 151         ARM64_FTR_END,
 152 };
 153
 154 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
 155         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
 156         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
 157         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
 158         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 159                                    FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
 160         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
 161         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
 162         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
 163         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
 164         /* Linux doesn't care about the EL3 */
 165         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
 166         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
 167         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
 168         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
 169         ARM64_FTR_END,
 170 };
 171
 172 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
 173         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
 174         ARM64_FTR_END,
 175 };
 176
 177 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
 178         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 179                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
 180         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 181                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
 182         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 183                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
 184         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 185                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
 186         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 187                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
 188         ARM64_FTR_END,
 189 };
 190
 191 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 192         /*
 193          * We already refuse to boot CPUs that don't support our configured
 194          * page size, so we can only detect mismatches for a page size other
 195          * than the one we're currently using. Unfortunately, SoCs like this
 196          * exist in the wild so, even though we don't like it, we'll have to go
 197          * along with it and treat them as non-strict.
 198          */
 199         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 200         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 201         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 202
 203         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 204         /* Linux shouldn't care about secure memory */
 205         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 206         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 207         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 208         /*
 209          * Differing PARange is fine as long as all peripherals and memory are mapped
 210          * within the minimum PARange of all CPUs
 211          */
 212         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 213         ARM64_FTR_END,
 214 };
 215
 216 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 217         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 218         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 219         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 220         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 221         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 222         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 223         ARM64_FTR_END,
 224 };
 225
 226 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 227         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
 228         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
 229         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
 230         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
 231         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
 232         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
 233         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
 234         ARM64_FTR_END,
 235 };
 236
 237 static const struct arm64_ftr_bits ftr_ctr[] = {
 238         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
 239         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
 240         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
 241         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
 242         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
 243         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
 244         /*
 245          * Linux can handle differing I-cache policies. Userspace JITs will
 246          * make use of *minLine.
 247          * If we have differing I-cache policies, report it as the weakest - VIPT.
 248          */
 249         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT),       /* L1Ip */
 250         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
 251         ARM64_FTR_END,
 252 };
 253
 254 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
 255         .name           = "SYS_CTR_EL0",
 256         .ftr_bits       = ftr_ctr
 257 };
 258
 259 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
 260         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf),   /* InnerShr */
 261         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),       /* FCSE */
 262         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),    /* AuxReg */
 263         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),       /* TCM */
 264         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),       /* ShareLvl */
 265         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf),    /* OuterShr */
 266         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* PMSA */
 267         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),        /* VMSA */
 268         ARM64_FTR_END,
 269 };
 270
 271 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 272         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
 273         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
 274         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 275         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 276         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 277         /*
 278          * We can instantiate multiple PMU instances with different levels
 279          * of support.
 280          */
 281         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 282         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
 283         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 284         ARM64_FTR_END,
 285 };
 286
 287 static const struct arm64_ftr_bits ftr_mvfr2[] = {
 288         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* FPMisc */
 289         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* SIMDMisc */
 290         ARM64_FTR_END,
 291 };
 292
 293 static const struct arm64_ftr_bits ftr_dczid[] = {
 294         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1),            /* DZP */
 295         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),       /* BS */
 296         ARM64_FTR_END,
 297 };
 298
 299
 300 static const struct arm64_ftr_bits ftr_id_isar5[] = {
 301         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
 302         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
 303         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
 304         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
 305         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
 306         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
 307         ARM64_FTR_END,
 308 };
 309
 310 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
 311         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* ac2 */
 312         ARM64_FTR_END,
 313 };
 314
 315 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
 316         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),               /* State3 */
 317         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),                /* State2 */
 318         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* State1 */
 319         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* State0 */
 320         ARM64_FTR_END,
 321 };
 322
 323 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
 324         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 325         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf),   /* PerfMon */
 326         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 327         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 328         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 329         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 330         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 331         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 332         ARM64_FTR_END,
 333 };
 334
 335 static const struct arm64_ftr_bits ftr_zcr[] = {
 336         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
 337                 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0),        /* LEN */
 338         ARM64_FTR_END,
 339 };
 340
 341 /*
 342  * Common ftr bits for a 32bit register with all hidden, strict
 343  * attributes, with 4bit feature fields and a default safe value of
 344  * 0. Covers the following 32bit registers:
 345  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 346  */
 347 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
 348         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 349         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 350         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 351         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 352         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 353         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 354         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 355         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 356         ARM64_FTR_END,
 357 };
 358
 359 /* Table for a single 32bit feature value */
 360 static const struct arm64_ftr_bits ftr_single32[] = {
 361         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
 362         ARM64_FTR_END,
 363 };
 364
 365 static const struct arm64_ftr_bits ftr_raz[] = {
 366         ARM64_FTR_END,
 367 };
 368
 369 #define ARM64_FTR_REG(id, table) {              \
 370         .sys_id = id,                           \
 371         .reg =  &(struct arm64_ftr_reg){        \
 372                 .name = #id,                    \
 373                 .ftr_bits = &((table)[0]),      \
 374         }}
 375
 376 static const struct __ftr_reg_entry {
 377         u32                     sys_id;
 378         struct arm64_ftr_reg    *reg;
 379 } arm64_ftr_regs[] = {
 380
 381         /* Op1 = 0, CRn = 0, CRm = 1 */
 382         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 383         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
 384         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
 385         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 386         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 387         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 388         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 389
 390         /* Op1 = 0, CRn = 0, CRm = 2 */
 391         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 392         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 393         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 394         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 395         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
 396         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 397         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 398
 399         /* Op1 = 0, CRn = 0, CRm = 3 */
 400         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 401         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 402         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 403
 404         /* Op1 = 0, CRn = 0, CRm = 4 */
 405         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 406         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
 407         ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
 408
 409         /* Op1 = 0, CRn = 0, CRm = 5 */
 410         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 411         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
 412
 413         /* Op1 = 0, CRn = 0, CRm = 6 */
 414         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 415         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
 416
 417         /* Op1 = 0, CRn = 0, CRm = 7 */
 418         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 419         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 420         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
 421
 422         /* Op1 = 0, CRn = 1, CRm = 2 */
 423         ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
 424
 425         /* Op1 = 3, CRn = 0, CRm = 0 */
 426         { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
 427         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 428
 429         /* Op1 = 3, CRn = 14, CRm = 0 */
 430         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
 431 };
 432
 433 static int search_cmp_ftr_reg(const void *id, const void *regp)
 434 {
 435         return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
 436 }
 437
 438 /*
 439  * get_arm64_ftr_reg - Lookup a feature register entry using its
 440  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 441  * ascending order of sys_id , we use binary search to find a matching
 442  * entry.
 443  *
 444  * returns - Upon success,  matching ftr_reg entry for id.
 445  *         - NULL on failure. It is upto the caller to decide
 446  *           the impact of a failure.
 447  */
 448 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 449 {
 450         const struct __ftr_reg_entry *ret;
 451
 452         ret = bsearch((const void *)(unsigned long)sys_id,
 453                         arm64_ftr_regs,
 454                         ARRAY_SIZE(arm64_ftr_regs),
 455                         sizeof(arm64_ftr_regs[0]),
 456                         search_cmp_ftr_reg);
 457         if (ret)
 458                 return ret->reg;
 459         return NULL;
 460 }
 461
 462 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
 463                                s64 ftr_val)
 464 {
 465         u64 mask = arm64_ftr_mask(ftrp);
 466
 467         reg &= ~mask;
 468         reg |= (ftr_val << ftrp->shift) & mask;
 469         return reg;
 470 }
 471
 472 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
 473                                 s64 cur)
 474 {
 475         s64 ret = 0;
 476
 477         switch (ftrp->type) {
 478         case FTR_EXACT:
 479                 ret = ftrp->safe_val;
 480                 break;
 481         case FTR_LOWER_SAFE:
 482                 ret = new < cur ? new : cur;
 483                 break;
 484         case FTR_HIGHER_OR_ZERO_SAFE:
 485                 if (!cur || !new)
 486                         break;
 487                 /* Fallthrough */
 488         case FTR_HIGHER_SAFE:
 489                 ret = new > cur ? new : cur;
 490                 break;
 491         default:
 492                 BUG();
 493         }
 494
 495         return ret;
 496 }
 497
 498 static void __init sort_ftr_regs(void)
 499 {
 500         int i;
 501
 502         /* Check that the array is sorted so that we can do the binary search */
 503         for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
 504                 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
 505 }
 506
 507 /*
 508  * Initialise the CPU feature register from Boot CPU values.
 509  * Also initiliases the strict_mask for the register.
 510  * Any bits that are not covered by an arm64_ftr_bits entry are considered
 511  * RES0 for the system-wide value, and must strictly match.
 512  */
 513 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 514 {
 515         u64 val = 0;
 516         u64 strict_mask = ~0x0ULL;
 517         u64 user_mask = 0;
 518         u64 valid_mask = 0;
 519
 520         const struct arm64_ftr_bits *ftrp;
 521         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 522
 523         BUG_ON(!reg);
 524
 525         for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
 526                 u64 ftr_mask = arm64_ftr_mask(ftrp);
 527                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 528
 529                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 530
 531                 valid_mask |= ftr_mask;
 532                 if (!ftrp->strict)
 533                         strict_mask &= ~ftr_mask;
 534                 if (ftrp->visible)
 535                         user_mask |= ftr_mask;
 536                 else
 537                         reg->user_val = arm64_ftr_set_value(ftrp,
 538                                                             reg->user_val,
 539                                                             ftrp->safe_val);
 540         }
 541
 542         val &= valid_mask;
 543
 544         reg->sys_val = val;
 545         reg->strict_mask = strict_mask;
 546         reg->user_mask = user_mask;
 547 }
 548
 549 extern const struct arm64_cpu_capabilities arm64_errata[];
 550 static const struct arm64_cpu_capabilities arm64_features[];
 551
 552 static void __init
 553 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
 554 {
 555         for (; caps->matches; caps++) {
 556                 if (WARN(caps->capability >= ARM64_NCAPS,
 557                         "Invalid capability %d\n", caps->capability))
 558                         continue;
 559                 if (WARN(cpu_hwcaps_ptrs[caps->capability],
 560                         "Duplicate entry for capability %d\n",
 561                         caps->capability))
 562                         continue;
 563                 cpu_hwcaps_ptrs[caps->capability] = caps;
 564         }
 565 }
 566
 567 static void __init init_cpu_hwcaps_indirect_list(void)
 568 {
 569         init_cpu_hwcaps_indirect_list_from_array(arm64_features);
 570         init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
 571 }
 572
 573 static void __init setup_boot_cpu_capabilities(void);
 574
 575 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 576 {
 577         /* Before we start using the tables, make sure it is sorted */
 578         sort_ftr_regs();
 579
 580         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 581         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 582         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 583         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 584         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 585         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 586         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 587         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 588         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 589         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
 590         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 591         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 592         init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
 593
 594         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 595                 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 596                 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 597                 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 598                 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 599                 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 600                 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 601                 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 602                 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 603                 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 604                 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 605                 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 606                 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 607                 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 608                 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 609                 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 610                 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 611         }
 612
 613         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 614                 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
 615                 sve_init_vq_map();
 616         }
 617
 618         /*
 619          * Initialize the indirect array of CPU hwcaps capabilities pointers
 620          * before we handle the boot CPU below.
 621          */
 622         init_cpu_hwcaps_indirect_list();
 623
 624         /*
 625          * Detect and enable early CPU capabilities based on the boot CPU,
 626          * after we have initialised the CPU feature infrastructure.
 627          */
 628         setup_boot_cpu_capabilities();
 629 }
 630
 631 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 632 {
 633         const struct arm64_ftr_bits *ftrp;
 634
 635         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 636                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 637                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 638
 639                 if (ftr_cur == ftr_new)
 640                         continue;
 641                 /* Find a safe value */
 642                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 643                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 644         }
 645
 646 }
 647
 648 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 649 {
 650         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 651
 652         BUG_ON(!regp);
 653         update_cpu_ftr_reg(regp, val);
 654         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 655                 return 0;
 656         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 657                         regp->name, boot, cpu, val);
 658         return 1;
 659 }
 660
 661 /*
 662  * Update system wide CPU feature registers with the values from a
 663  * non-boot CPU. Also performs SANITY checks to make sure that there
 664  * aren't any insane variations from that of the boot CPU.
 665  */
 666 void update_cpu_features(int cpu,
 667                          struct cpuinfo_arm64 *info,
 668                          struct cpuinfo_arm64 *boot)
 669 {
 670         int taint = 0;
 671
 672         /*
 673          * The kernel can handle differing I-cache policies, but otherwise
 674          * caches should look identical. Userspace JITs will make use of
 675          * *minLine.
 676          */
 677         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 678                                       info->reg_ctr, boot->reg_ctr);
 679
 680         /*
 681          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 682          * could result in too much or too little memory being zeroed if a
 683          * process is preempted and migrated between CPUs.
 684          */
 685         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 686                                       info->reg_dczid, boot->reg_dczid);
 687
 688         /* If different, timekeeping will be broken (especially with KVM) */
 689         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 690                                       info->reg_cntfrq, boot->reg_cntfrq);
 691
 692         /*
 693          * The kernel uses self-hosted debug features and expects CPUs to
 694          * support identical debug features. We presently need CTX_CMPs, WRPs,
 695          * and BRPs to be identical.
 696          * ID_AA64DFR1 is currently RES0.
 697          */
 698         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 699                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 700         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 701                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 702         /*
 703          * Even in big.LITTLE, processors should be identical instruction-set
 704          * wise.
 705          */
 706         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 707                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 708         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 709                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 710
 711         /*
 712          * Differing PARange support is fine as long as all peripherals and
 713          * memory are mapped within the minimum PARange of all CPUs.
 714          * Linux should not care about secure memory.
 715          */
 716         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 717                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 718         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 719                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 720         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
 721                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
 722
 723         /*
 724          * EL3 is not our concern.
 725          */
 726         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 727                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 728         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 729                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 730
 731         taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
 732                                       info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
 733
 734         /*
 735          * If we have AArch32, we care about 32-bit features for compat.
 736          * If the system doesn't support AArch32, don't update them.
 737          */
 738         if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 739                 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 740
 741                 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 742                                         info->reg_id_dfr0, boot->reg_id_dfr0);
 743                 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 744                                         info->reg_id_isar0, boot->reg_id_isar0);
 745                 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 746                                         info->reg_id_isar1, boot->reg_id_isar1);
 747                 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 748                                         info->reg_id_isar2, boot->reg_id_isar2);
 749                 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 750                                         info->reg_id_isar3, boot->reg_id_isar3);
 751                 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 752                                         info->reg_id_isar4, boot->reg_id_isar4);
 753                 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 754                                         info->reg_id_isar5, boot->reg_id_isar5);
 755
 756                 /*
 757                  * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 758                  * ACTLR formats could differ across CPUs and therefore would have to
 759                  * be trapped for virtualization anyway.
 760                  */
 761                 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 762                                         info->reg_id_mmfr0, boot->reg_id_mmfr0);
 763                 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 764                                         info->reg_id_mmfr1, boot->reg_id_mmfr1);
 765                 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 766                                         info->reg_id_mmfr2, boot->reg_id_mmfr2);
 767                 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 768                                         info->reg_id_mmfr3, boot->reg_id_mmfr3);
 769                 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 770                                         info->reg_id_pfr0, boot->reg_id_pfr0);
 771                 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 772                                         info->reg_id_pfr1, boot->reg_id_pfr1);
 773                 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 774                                         info->reg_mvfr0, boot->reg_mvfr0);
 775                 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 776                                         info->reg_mvfr1, boot->reg_mvfr1);
 777                 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 778                                         info->reg_mvfr2, boot->reg_mvfr2);
 779         }
 780
 781         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 782                 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
 783                                         info->reg_zcr, boot->reg_zcr);
 784
 785                 /* Probe vector lengths, unless we already gave up on SVE */
 786                 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 787                     !system_capabilities_finalized())
 788                         sve_update_vq_map();
 789         }
 790
 791         /*
 792          * Mismatched CPU features are a recipe for disaster. Don't even
 793          * pretend to support them.
 794          */
 795         if (taint) {
 796                 pr_warn_once("Unsupported CPU feature variation detected.\n");
 797                 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
 798         }
 799 }
 800
 801 u64 read_sanitised_ftr_reg(u32 id)
 802 {
 803         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 804
 805         /* We shouldn't get a request for an unsupported register */
 806         BUG_ON(!regp);
 807         return regp->sys_val;
 808 }
 809
 810 #define read_sysreg_case(r)     \
 811         case r:         return read_sysreg_s(r)
 812
 813 /*
 814  * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
 815  * Read the system register on the current CPU
 816  */
 817 static u64 __read_sysreg_by_encoding(u32 sys_id)
 818 {
 819         switch (sys_id) {
 820         read_sysreg_case(SYS_ID_PFR0_EL1);
 821         read_sysreg_case(SYS_ID_PFR1_EL1);
 822         read_sysreg_case(SYS_ID_DFR0_EL1);
 823         read_sysreg_case(SYS_ID_MMFR0_EL1);
 824         read_sysreg_case(SYS_ID_MMFR1_EL1);
 825         read_sysreg_case(SYS_ID_MMFR2_EL1);
 826         read_sysreg_case(SYS_ID_MMFR3_EL1);
 827         read_sysreg_case(SYS_ID_ISAR0_EL1);
 828         read_sysreg_case(SYS_ID_ISAR1_EL1);
 829         read_sysreg_case(SYS_ID_ISAR2_EL1);
 830         read_sysreg_case(SYS_ID_ISAR3_EL1);
 831         read_sysreg_case(SYS_ID_ISAR4_EL1);
 832         read_sysreg_case(SYS_ID_ISAR5_EL1);
 833         read_sysreg_case(SYS_MVFR0_EL1);
 834         read_sysreg_case(SYS_MVFR1_EL1);
 835         read_sysreg_case(SYS_MVFR2_EL1);
 836
 837         read_sysreg_case(SYS_ID_AA64PFR0_EL1);
 838         read_sysreg_case(SYS_ID_AA64PFR1_EL1);
 839         read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
 840         read_sysreg_case(SYS_ID_AA64DFR0_EL1);
 841         read_sysreg_case(SYS_ID_AA64DFR1_EL1);
 842         read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
 843         read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
 844         read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
 845         read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
 846         read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
 847
 848         read_sysreg_case(SYS_CNTFRQ_EL0);
 849         read_sysreg_case(SYS_CTR_EL0);
 850         read_sysreg_case(SYS_DCZID_EL0);
 851
 852         default:
 853                 BUG();
 854                 return 0;
 855         }
 856 }
 857
 858 #include <linux/irqchip/arm-gic-v3.h>
 859
 860 static bool
 861 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
 862 {
 863         int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
 864
 865         return val >= entry->min_field_value;
 866 }
 867
 868 static bool
 869 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
 870 {
 871         u64 val;
 872
 873         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
 874         if (scope == SCOPE_SYSTEM)
 875                 val = read_sanitised_ftr_reg(entry->sys_reg);
 876         else
 877                 val = __read_sysreg_by_encoding(entry->sys_reg);
 878
 879         return feature_matches(val, entry);
 880 }
 881
 882 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
 883 {
 884         bool has_sre;
 885
 886         if (!has_cpuid_feature(entry, scope))
 887                 return false;
 888
 889         has_sre = gic_enable_sre();
 890         if (!has_sre)
 891                 pr_warn_once("%s present but disabled by higher exception level\n",
 892                              entry->desc);
 893
 894         return has_sre;
 895 }
 896
 897 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
 898 {
 899         u32 midr = read_cpuid_id();
 900
 901         /* Cavium ThunderX pass 1.x and 2.x */
 902         return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
 903                 MIDR_CPU_VAR_REV(0, 0),
 904                 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
 905 }
 906
 907 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
 908 {
 909         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
 910
 911         return cpuid_feature_extract_signed_field(pfr0,
 912                                         ID_AA64PFR0_FP_SHIFT) < 0;
 913 }
 914
 915 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
 916                           int scope)
 917 {
 918         u64 ctr;
 919
 920         if (scope == SCOPE_SYSTEM)
 921                 ctr = arm64_ftr_reg_ctrel0.sys_val;
 922         else
 923                 ctr = read_cpuid_effective_cachetype();
 924
 925         return ctr & BIT(CTR_IDC_SHIFT);
 926 }
 927
 928 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
 929 {
 930         /*
 931          * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
 932          * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
 933          * to the CTR_EL0 on this CPU and emulate it with the real/safe
 934          * value.
 935          */
 936         if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
 937                 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
 938 }
 939
 940 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
 941                           int scope)
 942 {
 943         u64 ctr;
 944
 945         if (scope == SCOPE_SYSTEM)
 946                 ctr = arm64_ftr_reg_ctrel0.sys_val;
 947         else
 948                 ctr = read_cpuid_cachetype();
 949
 950         return ctr & BIT(CTR_DIC_SHIFT);
 951 }
 952
 953 static bool __maybe_unused
 954 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
 955 {
 956         /*
 957          * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
 958          * may share TLB entries with a CPU stuck in the crashed
 959          * kernel.
 960          */
 961          if (is_kdump_kernel())
 962                 return false;
 963
 964         return has_cpuid_feature(entry, scope);
 965 }
 966
 967 static bool __meltdown_safe = true;
 968 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
 969
 970 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
 971                                 int scope)
 972 {
 973         /* List of CPUs that are not vulnerable and don't need KPTI */
 974         static const struct midr_range kpti_safe_list[] = {
 975                 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
 976                 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
 977                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
 978                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
 979                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
 980                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
 981                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
 982                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
 983                 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
 984                 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
 985                 { /* sentinel */ }
 986         };
 987         char const *str = "kpti command line option";
 988         bool meltdown_safe;
 989
 990         meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
 991
 992         /* Defer to CPU feature registers */
 993         if (has_cpuid_feature(entry, scope))
 994                 meltdown_safe = true;
 995
 996         if (!meltdown_safe)
 997                 __meltdown_safe = false;
 998
 999         /*
1000          * For reasons that aren't entirely clear, enabling KPTI on Cavium
1001          * ThunderX leads to apparent I-cache corruption of kernel text, which
1002          * ends as well as you might imagine. Don't even try.
1003          */
1004         if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1005                 str = "ARM64_WORKAROUND_CAVIUM_27456";
1006                 __kpti_forced = -1;
1007         }
1008
1009         /* Useful for KASLR robustness */
1010         if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && kaslr_offset() > 0) {
1011                 if (!__kpti_forced) {
1012                         str = "KASLR";
1013                         __kpti_forced = 1;
1014                 }
1015         }
1016
1017         if (cpu_mitigations_off() && !__kpti_forced) {
1018                 str = "mitigations=off";
1019                 __kpti_forced = -1;
1020         }
1021
1022         if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1023                 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1024                 return false;
1025         }
1026
1027         /* Forced? */
1028         if (__kpti_forced) {
1029                 pr_info_once("kernel page table isolation forced %s by %s\n",
1030                              __kpti_forced > 0 ? "ON" : "OFF", str);
1031                 return __kpti_forced > 0;
1032         }
1033
1034         return !meltdown_safe;
1035 }
1036
1037 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1038 static void
1039 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1040 {
1041         typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1042         extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1043         kpti_remap_fn *remap_fn;
1044
1045         static bool kpti_applied = false;
1046         int cpu = smp_processor_id();
1047
1048         /*
1049          * We don't need to rewrite the page-tables if either we've done
1050          * it already or we have KASLR enabled and therefore have not
1051          * created any global mappings at all.
1052          */
1053         if (kpti_applied || kaslr_offset() > 0)
1054                 return;
1055
1056         remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
1057
1058         cpu_install_idmap();
1059         remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1060         cpu_uninstall_idmap();
1061
1062         if (!cpu)
1063                 kpti_applied = true;
1064
1065         return;
1066 }
1067 #else
1068 static void
1069 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1070 {
1071 }
1072 #endif  /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1073
1074 static int __init parse_kpti(char *str)
1075 {
1076         bool enabled;
1077         int ret = strtobool(str, &enabled);
1078
1079         if (ret)
1080                 return ret;
1081
1082         __kpti_forced = enabled ? 1 : -1;
1083         return 0;
1084 }
1085 early_param("kpti", parse_kpti);
1086
1087 #ifdef CONFIG_ARM64_HW_AFDBM
1088 static inline void __cpu_enable_hw_dbm(void)
1089 {
1090         u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1091
1092         write_sysreg(tcr, tcr_el1);
1093         isb();
1094 }
1095
1096 static bool cpu_has_broken_dbm(void)
1097 {
1098         /* List of CPUs which have broken DBM support. */
1099         static const struct midr_range cpus[] = {
1100 #ifdef CONFIG_ARM64_ERRATUM_1024718
1101                 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0),  // A55 r0p0 -r1p0
1102 #endif
1103                 {},
1104         };
1105
1106         return is_midr_in_range_list(read_cpuid_id(), cpus);
1107 }
1108
1109 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1110 {
1111         return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1112                !cpu_has_broken_dbm();
1113 }
1114
1115 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1116 {
1117         if (cpu_can_use_dbm(cap))
1118                 __cpu_enable_hw_dbm();
1119 }
1120
1121 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1122                        int __unused)
1123 {
1124         static bool detected = false;
1125         /*
1126          * DBM is a non-conflicting feature. i.e, the kernel can safely
1127          * run a mix of CPUs with and without the feature. So, we
1128          * unconditionally enable the capability to allow any late CPU
1129          * to use the feature. We only enable the control bits on the
1130          * CPU, if it actually supports.
1131          *
1132          * We have to make sure we print the "feature" detection only
1133          * when at least one CPU actually uses it. So check if this CPU
1134          * can actually use it and print the message exactly once.
1135          *
1136          * This is safe as all CPUs (including secondary CPUs - due to the
1137          * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1138          * goes through the "matches" check exactly once. Also if a CPU
1139          * matches the criteria, it is guaranteed that the CPU will turn
1140          * the DBM on, as the capability is unconditionally enabled.
1141          */
1142         if (!detected && cpu_can_use_dbm(cap)) {
1143                 detected = true;
1144                 pr_info("detected: Hardware dirty bit management\n");
1145         }
1146
1147         return true;
1148 }
1149
1150 #endif
1151
1152 #ifdef CONFIG_ARM64_VHE
1153 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1154 {
1155         return is_kernel_in_hyp_mode();
1156 }
1157
1158 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1159 {
1160         /*
1161          * Copy register values that aren't redirected by hardware.
1162          *
1163          * Before code patching, we only set tpidr_el1, all CPUs need to copy
1164          * this value to tpidr_el2 before we patch the code. Once we've done
1165          * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1166          * do anything here.
1167          */
1168         if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1169                 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1170 }
1171 #endif
1172
1173 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1174 {
1175         u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1176
1177         /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1178         WARN_ON(val & (7 << 27 | 7 << 21));
1179 }
1180
1181 #ifdef CONFIG_ARM64_SSBD
1182 static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
1183 {
1184         if (user_mode(regs))
1185                 return 1;
1186
1187         if (instr & BIT(PSTATE_Imm_shift))
1188                 regs->pstate |= PSR_SSBS_BIT;
1189         else
1190                 regs->pstate &= ~PSR_SSBS_BIT;
1191
1192         arm64_skip_faulting_instruction(regs, 4);
1193         return 0;
1194 }
1195
1196 static struct undef_hook ssbs_emulation_hook = {
1197         .instr_mask     = ~(1U << PSTATE_Imm_shift),
1198         .instr_val      = 0xd500401f | PSTATE_SSBS,
1199         .fn             = ssbs_emulation_handler,
1200 };
1201
1202 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
1203 {
1204         static bool undef_hook_registered = false;
1205         static DEFINE_RAW_SPINLOCK(hook_lock);
1206
1207         raw_spin_lock(&hook_lock);
1208         if (!undef_hook_registered) {
1209                 register_undef_hook(&ssbs_emulation_hook);
1210                 undef_hook_registered = true;
1211         }
1212         raw_spin_unlock(&hook_lock);
1213
1214         if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
1215                 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
1216                 arm64_set_ssbd_mitigation(false);
1217         } else {
1218                 arm64_set_ssbd_mitigation(true);
1219         }
1220 }
1221 #endif /* CONFIG_ARM64_SSBD */
1222
1223 #ifdef CONFIG_ARM64_PAN
1224 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1225 {
1226         /*
1227          * We modify PSTATE. This won't work from irq context as the PSTATE
1228          * is discarded once we return from the exception.
1229          */
1230         WARN_ON_ONCE(in_interrupt());
1231
1232         sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1233         asm(SET_PSTATE_PAN(1));
1234 }
1235 #endif /* CONFIG_ARM64_PAN */
1236
1237 #ifdef CONFIG_ARM64_RAS_EXTN
1238 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1239 {
1240         /* Firmware may have left a deferred SError in this register. */
1241         write_sysreg_s(0, SYS_DISR_EL1);
1242 }
1243 #endif /* CONFIG_ARM64_RAS_EXTN */
1244
1245 #ifdef CONFIG_ARM64_PTR_AUTH
1246 static void cpu_enable_address_auth(struct arm64_cpu_capabilities const *cap)
1247 {
1248         sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ENIA | SCTLR_ELx_ENIB |
1249                                        SCTLR_ELx_ENDA | SCTLR_ELx_ENDB);
1250 }
1251 #endif /* CONFIG_ARM64_PTR_AUTH */
1252
1253 #ifdef CONFIG_ARM64_PSEUDO_NMI
1254 static bool enable_pseudo_nmi;
1255
1256 static int __init early_enable_pseudo_nmi(char *p)
1257 {
1258         return strtobool(p, &enable_pseudo_nmi);
1259 }
1260 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1261
1262 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1263                                    int scope)
1264 {
1265         return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
1266 }
1267 #endif
1268
1269 static const struct arm64_cpu_capabilities arm64_features[] = {
1270         {
1271                 .desc = "GIC system register CPU interface",
1272                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1273                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1274                 .matches = has_useable_gicv3_cpuif,
1275                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1276                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1277                 .sign = FTR_UNSIGNED,
1278                 .min_field_value = 1,
1279         },
1280 #ifdef CONFIG_ARM64_PAN
1281         {
1282                 .desc = "Privileged Access Never",
1283                 .capability = ARM64_HAS_PAN,
1284                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1285                 .matches = has_cpuid_feature,
1286                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1287                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1288                 .sign = FTR_UNSIGNED,
1289                 .min_field_value = 1,
1290                 .cpu_enable = cpu_enable_pan,
1291         },
1292 #endif /* CONFIG_ARM64_PAN */
1293 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
1294         {
1295                 .desc = "LSE atomic instructions",
1296                 .capability = ARM64_HAS_LSE_ATOMICS,
1297                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1298                 .matches = has_cpuid_feature,
1299                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1300                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1301                 .sign = FTR_UNSIGNED,
1302                 .min_field_value = 2,
1303         },
1304 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
1305         {
1306                 .desc = "Software prefetching using PRFM",
1307                 .capability = ARM64_HAS_NO_HW_PREFETCH,
1308                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1309                 .matches = has_no_hw_prefetch,
1310         },
1311 #ifdef CONFIG_ARM64_UAO
1312         {
1313                 .desc = "User Access Override",
1314                 .capability = ARM64_HAS_UAO,
1315                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1316                 .matches = has_cpuid_feature,
1317                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1318                 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1319                 .min_field_value = 1,
1320                 /*
1321                  * We rely on stop_machine() calling uao_thread_switch() to set
1322                  * UAO immediately after patching.
1323                  */
1324         },
1325 #endif /* CONFIG_ARM64_UAO */
1326 #ifdef CONFIG_ARM64_PAN
1327         {
1328                 .capability = ARM64_ALT_PAN_NOT_UAO,
1329                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1330                 .matches = cpufeature_pan_not_uao,
1331         },
1332 #endif /* CONFIG_ARM64_PAN */
1333 #ifdef CONFIG_ARM64_VHE
1334         {
1335                 .desc = "Virtualization Host Extensions",
1336                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1337                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1338                 .matches = runs_at_el2,
1339                 .cpu_enable = cpu_copy_el2regs,
1340         },
1341 #endif  /* CONFIG_ARM64_VHE */
1342         {
1343                 .desc = "32-bit EL0 Support",
1344                 .capability = ARM64_HAS_32BIT_EL0,
1345                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1346                 .matches = has_cpuid_feature,
1347                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1348                 .sign = FTR_UNSIGNED,
1349                 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1350                 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1351         },
1352         {
1353                 .desc = "Kernel page table isolation (KPTI)",
1354                 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1355                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1356                 /*
1357                  * The ID feature fields below are used to indicate that
1358                  * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1359                  * more details.
1360                  */
1361                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1362                 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1363                 .min_field_value = 1,
1364                 .matches = unmap_kernel_at_el0,
1365                 .cpu_enable = kpti_install_ng_mappings,
1366         },
1367         {
1368                 /* FP/SIMD is not implemented */
1369                 .capability = ARM64_HAS_NO_FPSIMD,
1370                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1371                 .min_field_value = 0,
1372                 .matches = has_no_fpsimd,
1373         },
1374 #ifdef CONFIG_ARM64_PMEM
1375         {
1376                 .desc = "Data cache clean to Point of Persistence",
1377                 .capability = ARM64_HAS_DCPOP,
1378                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1379                 .matches = has_cpuid_feature,
1380                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1381                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1382                 .min_field_value = 1,
1383         },
1384         {
1385                 .desc = "Data cache clean to Point of Deep Persistence",
1386                 .capability = ARM64_HAS_DCPODP,
1387                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1388                 .matches = has_cpuid_feature,
1389                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1390                 .sign = FTR_UNSIGNED,
1391                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1392                 .min_field_value = 2,
1393         },
1394 #endif
1395 #ifdef CONFIG_ARM64_SVE
1396         {
1397                 .desc = "Scalable Vector Extension",
1398                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1399                 .capability = ARM64_SVE,
1400                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1401                 .sign = FTR_UNSIGNED,
1402                 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1403                 .min_field_value = ID_AA64PFR0_SVE,
1404                 .matches = has_cpuid_feature,
1405                 .cpu_enable = sve_kernel_enable,
1406         },
1407 #endif /* CONFIG_ARM64_SVE */
1408 #ifdef CONFIG_ARM64_RAS_EXTN
1409         {
1410                 .desc = "RAS Extension Support",
1411                 .capability = ARM64_HAS_RAS_EXTN,
1412                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1413                 .matches = has_cpuid_feature,
1414                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1415                 .sign = FTR_UNSIGNED,
1416                 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1417                 .min_field_value = ID_AA64PFR0_RAS_V1,
1418                 .cpu_enable = cpu_clear_disr,
1419         },
1420 #endif /* CONFIG_ARM64_RAS_EXTN */
1421         {
1422                 .desc = "Data cache clean to the PoU not required for I/D coherence",
1423                 .capability = ARM64_HAS_CACHE_IDC,
1424                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1425                 .matches = has_cache_idc,
1426                 .cpu_enable = cpu_emulate_effective_ctr,
1427         },
1428         {
1429                 .desc = "Instruction cache invalidation not required for I/D coherence",
1430                 .capability = ARM64_HAS_CACHE_DIC,
1431                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1432                 .matches = has_cache_dic,
1433         },
1434         {
1435                 .desc = "Stage-2 Force Write-Back",
1436                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1437                 .capability = ARM64_HAS_STAGE2_FWB,
1438                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1439                 .sign = FTR_UNSIGNED,
1440                 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
1441                 .min_field_value = 1,
1442                 .matches = has_cpuid_feature,
1443                 .cpu_enable = cpu_has_fwb,
1444         },
1445 #ifdef CONFIG_ARM64_HW_AFDBM
1446         {
1447                 /*
1448                  * Since we turn this on always, we don't want the user to
1449                  * think that the feature is available when it may not be.
1450                  * So hide the description.
1451                  *
1452                  * .desc = "Hardware pagetable Dirty Bit Management",
1453                  *
1454                  */
1455                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1456                 .capability = ARM64_HW_DBM,
1457                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1458                 .sign = FTR_UNSIGNED,
1459                 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
1460                 .min_field_value = 2,
1461                 .matches = has_hw_dbm,
1462                 .cpu_enable = cpu_enable_hw_dbm,
1463         },
1464 #endif
1465         {
1466                 .desc = "CRC32 instructions",
1467                 .capability = ARM64_HAS_CRC32,
1468                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1469                 .matches = has_cpuid_feature,
1470                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1471                 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
1472                 .min_field_value = 1,
1473         },
1474 #ifdef CONFIG_ARM64_SSBD
1475         {
1476                 .desc = "Speculative Store Bypassing Safe (SSBS)",
1477                 .capability = ARM64_SSBS,
1478                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1479                 .matches = has_cpuid_feature,
1480                 .sys_reg = SYS_ID_AA64PFR1_EL1,
1481                 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
1482                 .sign = FTR_UNSIGNED,
1483                 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
1484                 .cpu_enable = cpu_enable_ssbs,
1485         },
1486 #endif
1487 #ifdef CONFIG_ARM64_CNP
1488         {
1489                 .desc = "Common not Private translations",
1490                 .capability = ARM64_HAS_CNP,
1491                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1492                 .matches = has_useable_cnp,
1493                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1494                 .sign = FTR_UNSIGNED,
1495                 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
1496                 .min_field_value = 1,
1497                 .cpu_enable = cpu_enable_cnp,
1498         },
1499 #endif
1500         {
1501                 .desc = "Speculation barrier (SB)",
1502                 .capability = ARM64_HAS_SB,
1503                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1504                 .matches = has_cpuid_feature,
1505                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1506                 .field_pos = ID_AA64ISAR1_SB_SHIFT,
1507                 .sign = FTR_UNSIGNED,
1508                 .min_field_value = 1,
1509         },
1510 #ifdef CONFIG_ARM64_PTR_AUTH
1511         {
1512                 .desc = "Address authentication (architected algorithm)",
1513                 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
1514                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1515                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1516                 .sign = FTR_UNSIGNED,
1517                 .field_pos = ID_AA64ISAR1_APA_SHIFT,
1518                 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
1519                 .matches = has_cpuid_feature,
1520                 .cpu_enable = cpu_enable_address_auth,
1521         },
1522         {
1523                 .desc = "Address authentication (IMP DEF algorithm)",
1524                 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
1525                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1526                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1527                 .sign = FTR_UNSIGNED,
1528                 .field_pos = ID_AA64ISAR1_API_SHIFT,
1529                 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
1530                 .matches = has_cpuid_feature,
1531                 .cpu_enable = cpu_enable_address_auth,
1532         },
1533         {
1534                 .desc = "Generic authentication (architected algorithm)",
1535                 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
1536                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1537                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1538                 .sign = FTR_UNSIGNED,
1539                 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
1540                 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
1541                 .matches = has_cpuid_feature,
1542         },
1543         {
1544                 .desc = "Generic authentication (IMP DEF algorithm)",
1545                 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
1546                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1547                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1548                 .sign = FTR_UNSIGNED,
1549                 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
1550                 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
1551                 .matches = has_cpuid_feature,
1552         },
1553 #endif /* CONFIG_ARM64_PTR_AUTH */
1554 #ifdef CONFIG_ARM64_PSEUDO_NMI
1555         {
1556                 /*
1557                  * Depends on having GICv3
1558                  */
1559                 .desc = "IRQ priority masking",
1560                 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
1561                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1562                 .matches = can_use_gic_priorities,
1563                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1564                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1565                 .sign = FTR_UNSIGNED,
1566                 .min_field_value = 1,
1567         },
1568 #endif
1569         {},
1570 };
1571
1572 #define HWCAP_CPUID_MATCH(reg, field, s, min_value)                             \
1573                 .matches = has_cpuid_feature,                                   \
1574                 .sys_reg = reg,                                                 \
1575                 .field_pos = field,                                             \
1576                 .sign = s,                                                      \
1577                 .min_field_value = min_value,
1578
1579 #define __HWCAP_CAP(name, cap_type, cap)                                        \
1580                 .desc = name,                                                   \
1581                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,                            \
1582                 .hwcap_type = cap_type,                                         \
1583                 .hwcap = cap,                                                   \
1584
1585 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap)                      \
1586         {                                                                       \
1587                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1588                 HWCAP_CPUID_MATCH(reg, field, s, min_value)                     \
1589         }
1590
1591 #define HWCAP_MULTI_CAP(list, cap_type, cap)                                    \
1592         {                                                                       \
1593                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1594                 .matches = cpucap_multi_entry_cap_matches,                      \
1595                 .match_list = list,                                             \
1596         }
1597
1598 #define HWCAP_CAP_MATCH(match, cap_type, cap)                                   \
1599         {                                                                       \
1600                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1601                 .matches = match,                                               \
1602         }
1603
1604 #ifdef CONFIG_ARM64_PTR_AUTH
1605 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
1606         {
1607                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
1608                                   FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
1609         },
1610         {
1611                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
1612                                   FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
1613         },
1614         {},
1615 };
1616
1617 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
1618         {
1619                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
1620                                   FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
1621         },
1622         {
1623                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
1624                                   FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
1625         },
1626         {},
1627 };
1628 #endif
1629
1630 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
1631         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
1632         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
1633         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
1634         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
1635         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
1636         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
1637         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
1638         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
1639         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
1640         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
1641         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
1642         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
1643         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
1644         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
1645         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
1646         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
1647         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
1648         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
1649         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
1650         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
1651         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
1652         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
1653         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
1654         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
1655         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
1656         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
1657         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
1658         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
1659         HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
1660 #ifdef CONFIG_ARM64_SVE
1661         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
1662         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
1663         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
1664         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
1665         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
1666         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
1667         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
1668 #endif
1669         HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
1670 #ifdef CONFIG_ARM64_PTR_AUTH
1671         HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
1672         HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
1673 #endif
1674         {},
1675 };
1676
1677 #ifdef CONFIG_COMPAT
1678 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
1679 {
1680         /*
1681          * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
1682          * in line with that of arm32 as in vfp_init(). We make sure that the
1683          * check is future proof, by making sure value is non-zero.
1684          */
1685         u32 mvfr1;
1686
1687         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1688         if (scope == SCOPE_SYSTEM)
1689                 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
1690         else
1691                 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
1692
1693         return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
1694                 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
1695                 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
1696 }
1697 #endif
1698
1699 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
1700 #ifdef CONFIG_COMPAT
1701         HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
1702         HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
1703         /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
1704         HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
1705         HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
1706         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1707         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1708         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1709         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1710         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
1711 #endif
1712         {},
1713 };
1714
1715 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1716 {
1717         switch (cap->hwcap_type) {
1718         case CAP_HWCAP:
1719                 cpu_set_feature(cap->hwcap);
1720                 break;
1721 #ifdef CONFIG_COMPAT
1722         case CAP_COMPAT_HWCAP:
1723                 compat_elf_hwcap |= (u32)cap->hwcap;
1724                 break;
1725         case CAP_COMPAT_HWCAP2:
1726                 compat_elf_hwcap2 |= (u32)cap->hwcap;
1727                 break;
1728 #endif
1729         default:
1730                 WARN_ON(1);
1731                 break;
1732         }
1733 }
1734
1735 /* Check if we have a particular HWCAP enabled */
1736 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1737 {
1738         bool rc;
1739
1740         switch (cap->hwcap_type) {
1741         case CAP_HWCAP:
1742                 rc = cpu_have_feature(cap->hwcap);
1743                 break;
1744 #ifdef CONFIG_COMPAT
1745         case CAP_COMPAT_HWCAP:
1746                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1747                 break;
1748         case CAP_COMPAT_HWCAP2:
1749                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1750                 break;
1751 #endif
1752         default:
1753                 WARN_ON(1);
1754                 rc = false;
1755         }
1756
1757         return rc;
1758 }
1759
1760 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
1761 {
1762         /* We support emulation of accesses to CPU ID feature registers */
1763         cpu_set_named_feature(CPUID);
1764         for (; hwcaps->matches; hwcaps++)
1765                 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
1766                         cap_set_elf_hwcap(hwcaps);
1767 }
1768
1769 static void update_cpu_capabilities(u16 scope_mask)
1770 {
1771         int i;
1772         const struct arm64_cpu_capabilities *caps;
1773
1774         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1775         for (i = 0; i < ARM64_NCAPS; i++) {
1776                 caps = cpu_hwcaps_ptrs[i];
1777                 if (!caps || !(caps->type & scope_mask) ||
1778                     cpus_have_cap(caps->capability) ||
1779                     !caps->matches(caps, cpucap_default_scope(caps)))
1780                         continue;
1781
1782                 if (caps->desc)
1783                         pr_info("detected: %s\n", caps->desc);
1784                 cpus_set_cap(caps->capability);
1785
1786                 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
1787                         set_bit(caps->capability, boot_capabilities);
1788         }
1789 }
1790
1791 /*
1792  * Enable all the available capabilities on this CPU. The capabilities
1793  * with BOOT_CPU scope are handled separately and hence skipped here.
1794  */
1795 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
1796 {
1797         int i;
1798         u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
1799
1800         for_each_available_cap(i) {
1801                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
1802
1803                 if (WARN_ON(!cap))
1804                         continue;
1805
1806                 if (!(cap->type & non_boot_scope))
1807                         continue;
1808
1809                 if (cap->cpu_enable)
1810                         cap->cpu_enable(cap);
1811         }
1812         return 0;
1813 }
1814
1815 /*
1816  * Run through the enabled capabilities and enable() it on all active
1817  * CPUs
1818  */
1819 static void __init enable_cpu_capabilities(u16 scope_mask)
1820 {
1821         int i;
1822         const struct arm64_cpu_capabilities *caps;
1823         bool boot_scope;
1824
1825         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1826         boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
1827
1828         for (i = 0; i < ARM64_NCAPS; i++) {
1829                 unsigned int num;
1830
1831                 caps = cpu_hwcaps_ptrs[i];
1832                 if (!caps || !(caps->type & scope_mask))
1833                         continue;
1834                 num = caps->capability;
1835                 if (!cpus_have_cap(num))
1836                         continue;
1837
1838                 /* Ensure cpus_have_const_cap(num) works */
1839                 static_branch_enable(&cpu_hwcap_keys[num]);
1840
1841                 if (boot_scope && caps->cpu_enable)
1842                         /*
1843                          * Capabilities with SCOPE_BOOT_CPU scope are finalised
1844                          * before any secondary CPU boots. Thus, each secondary
1845                          * will enable the capability as appropriate via
1846                          * check_local_cpu_capabilities(). The only exception is
1847                          * the boot CPU, for which the capability must be
1848                          * enabled here. This approach avoids costly
1849                          * stop_machine() calls for this case.
1850                          */
1851                         caps->cpu_enable(caps);
1852         }
1853
1854         /*
1855          * For all non-boot scope capabilities, use stop_machine()
1856          * as it schedules the work allowing us to modify PSTATE,
1857          * instead of on_each_cpu() which uses an IPI, giving us a
1858          * PSTATE that disappears when we return.
1859          */
1860         if (!boot_scope)
1861                 stop_machine(cpu_enable_non_boot_scope_capabilities,
1862                              NULL, cpu_online_mask);
1863 }
1864
1865 /*
1866  * Run through the list of capabilities to check for conflicts.
1867  * If the system has already detected a capability, take necessary
1868  * action on this CPU.
1869  *
1870  * Returns "false" on conflicts.
1871  */
1872 static bool verify_local_cpu_caps(u16 scope_mask)
1873 {
1874         int i;
1875         bool cpu_has_cap, system_has_cap;
1876         const struct arm64_cpu_capabilities *caps;
1877
1878         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1879
1880         for (i = 0; i < ARM64_NCAPS; i++) {
1881                 caps = cpu_hwcaps_ptrs[i];
1882                 if (!caps || !(caps->type & scope_mask))
1883                         continue;
1884
1885                 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
1886                 system_has_cap = cpus_have_cap(caps->capability);
1887
1888                 if (system_has_cap) {
1889                         /*
1890                          * Check if the new CPU misses an advertised feature,
1891                          * which is not safe to miss.
1892                          */
1893                         if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
1894                                 break;
1895                         /*
1896                          * We have to issue cpu_enable() irrespective of
1897                          * whether the CPU has it or not, as it is enabeld
1898                          * system wide. It is upto the call back to take
1899                          * appropriate action on this CPU.
1900                          */
1901                         if (caps->cpu_enable)
1902                                 caps->cpu_enable(caps);
1903                 } else {
1904                         /*
1905                          * Check if the CPU has this capability if it isn't
1906                          * safe to have when the system doesn't.
1907                          */
1908                         if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
1909                                 break;
1910                 }
1911         }
1912
1913         if (i < ARM64_NCAPS) {
1914                 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
1915                         smp_processor_id(), caps->capability,
1916                         caps->desc, system_has_cap, cpu_has_cap);
1917                 return false;
1918         }
1919
1920         return true;
1921 }
1922
1923 /*
1924  * Check for CPU features that are used in early boot
1925  * based on the Boot CPU value.
1926  */
1927 static void check_early_cpu_features(void)
1928 {
1929         verify_cpu_asid_bits();
1930         /*
1931          * Early features are used by the kernel already. If there
1932          * is a conflict, we cannot proceed further.
1933          */
1934         if (!verify_local_cpu_caps(SCOPE_BOOT_CPU))
1935                 cpu_panic_kernel();
1936 }
1937
1938 static void
1939 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1940 {
1941
1942         for (; caps->matches; caps++)
1943                 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
1944                         pr_crit("CPU%d: missing HWCAP: %s\n",
1945                                         smp_processor_id(), caps->desc);
1946                         cpu_die_early();
1947                 }
1948 }
1949
1950 static void verify_sve_features(void)
1951 {
1952         u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
1953         u64 zcr = read_zcr_features();
1954
1955         unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
1956         unsigned int len = zcr & ZCR_ELx_LEN_MASK;
1957
1958         if (len < safe_len || sve_verify_vq_map()) {
1959                 pr_crit("CPU%d: SVE: vector length support mismatch\n",
1960                         smp_processor_id());
1961                 cpu_die_early();
1962         }
1963
1964         /* Add checks on other ZCR bits here if necessary */
1965 }
1966
1967
1968 /*
1969  * Run through the enabled system capabilities and enable() it on this CPU.
1970  * The capabilities were decided based on the available CPUs at the boot time.
1971  * Any new CPU should match the system wide status of the capability. If the
1972  * new CPU doesn't have a capability which the system now has enabled, we
1973  * cannot do anything to fix it up and could cause unexpected failures. So
1974  * we park the CPU.
1975  */
1976 static void verify_local_cpu_capabilities(void)
1977 {
1978         /*
1979          * The capabilities with SCOPE_BOOT_CPU are checked from
1980          * check_early_cpu_features(), as they need to be verified
1981          * on all secondary CPUs.
1982          */
1983         if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU))
1984                 cpu_die_early();
1985
1986         verify_local_elf_hwcaps(arm64_elf_hwcaps);
1987
1988         if (system_supports_32bit_el0())
1989                 verify_local_elf_hwcaps(compat_elf_hwcaps);
1990
1991         if (system_supports_sve())
1992                 verify_sve_features();
1993 }
1994
1995 void check_local_cpu_capabilities(void)
1996 {
1997         /*
1998          * All secondary CPUs should conform to the early CPU features
1999          * in use by the kernel based on boot CPU.
2000          */
2001         check_early_cpu_features();
2002
2003         /*
2004          * If we haven't finalised the system capabilities, this CPU gets
2005          * a chance to update the errata work arounds and local features.
2006          * Otherwise, this CPU should verify that it has all the system
2007          * advertised capabilities.
2008          */
2009         if (!system_capabilities_finalized())
2010                 update_cpu_capabilities(SCOPE_LOCAL_CPU);
2011         else
2012                 verify_local_cpu_capabilities();
2013 }
2014
2015 static void __init setup_boot_cpu_capabilities(void)
2016 {
2017         /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
2018         update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
2019         /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
2020         enable_cpu_capabilities(SCOPE_BOOT_CPU);
2021 }
2022
2023 bool this_cpu_has_cap(unsigned int n)
2024 {
2025         if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
2026                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2027
2028                 if (cap)
2029                         return cap->matches(cap, SCOPE_LOCAL_CPU);
2030         }
2031
2032         return false;
2033 }
2034
2035 void cpu_set_feature(unsigned int num)
2036 {
2037         WARN_ON(num >= MAX_CPU_FEATURES);
2038         elf_hwcap |= BIT(num);
2039 }
2040 EXPORT_SYMBOL_GPL(cpu_set_feature);
2041
2042 bool cpu_have_feature(unsigned int num)
2043 {
2044         WARN_ON(num >= MAX_CPU_FEATURES);
2045         return elf_hwcap & BIT(num);
2046 }
2047 EXPORT_SYMBOL_GPL(cpu_have_feature);
2048
2049 unsigned long cpu_get_elf_hwcap(void)
2050 {
2051         /*
2052          * We currently only populate the first 32 bits of AT_HWCAP. Please
2053          * note that for userspace compatibility we guarantee that bits 62
2054          * and 63 will always be returned as 0.
2055          */
2056         return lower_32_bits(elf_hwcap);
2057 }
2058
2059 unsigned long cpu_get_elf_hwcap2(void)
2060 {
2061         return upper_32_bits(elf_hwcap);
2062 }
2063
2064 static void __init setup_system_capabilities(void)
2065 {
2066         /*
2067          * We have finalised the system-wide safe feature
2068          * registers, finalise the capabilities that depend
2069          * on it. Also enable all the available capabilities,
2070          * that are not enabled already.
2071          */
2072         update_cpu_capabilities(SCOPE_SYSTEM);
2073         enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2074 }
2075
2076 void __init setup_cpu_features(void)
2077 {
2078         u32 cwg;
2079
2080         setup_system_capabilities();
2081         setup_elf_hwcaps(arm64_elf_hwcaps);
2082
2083         if (system_supports_32bit_el0())
2084                 setup_elf_hwcaps(compat_elf_hwcaps);
2085
2086         if (system_uses_ttbr0_pan())
2087                 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
2088
2089         sve_setup();
2090         minsigstksz_setup();
2091
2092         /* Advertise that we have computed the system capabilities */
2093         finalize_system_capabilities();
2094
2095         /*
2096          * Check for sane CTR_EL0.CWG value.
2097          */
2098         cwg = cache_type_cwg();
2099         if (!cwg)
2100                 pr_warn("No Cache Writeback Granule information, assuming %d\n",
2101                         ARCH_DMA_MINALIGN);
2102 }
2103
2104 static bool __maybe_unused
2105 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
2106 {
2107         return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
2108 }
2109
2110 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
2111 {
2112         cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
2113 }
2114
2115 /*
2116  * We emulate only the following system register space.
2117  * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
2118  * See Table C5-6 System instruction encodings for System register accesses,
2119  * ARMv8 ARM(ARM DDI 0487A.f) for more details.
2120  */
2121 static inline bool __attribute_const__ is_emulated(u32 id)
2122 {
2123         return (sys_reg_Op0(id) == 0x3 &&
2124                 sys_reg_CRn(id) == 0x0 &&
2125                 sys_reg_Op1(id) == 0x0 &&
2126                 (sys_reg_CRm(id) == 0 ||
2127                  ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
2128 }
2129
2130 /*
2131  * With CRm == 0, reg should be one of :
2132  * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
2133  */
2134 static inline int emulate_id_reg(u32 id, u64 *valp)
2135 {
2136         switch (id) {
2137         case SYS_MIDR_EL1:
2138                 *valp = read_cpuid_id();
2139                 break;
2140         case SYS_MPIDR_EL1:
2141                 *valp = SYS_MPIDR_SAFE_VAL;
2142                 break;
2143         case SYS_REVIDR_EL1:
2144                 /* IMPLEMENTATION DEFINED values are emulated with 0 */
2145                 *valp = 0;
2146                 break;
2147         default:
2148                 return -EINVAL;
2149         }
2150
2151         return 0;
2152 }
2153
2154 static int emulate_sys_reg(u32 id, u64 *valp)
2155 {
2156         struct arm64_ftr_reg *regp;
2157
2158         if (!is_emulated(id))
2159                 return -EINVAL;
2160
2161         if (sys_reg_CRm(id) == 0)
2162                 return emulate_id_reg(id, valp);
2163
2164         regp = get_arm64_ftr_reg(id);
2165         if (regp)
2166                 *valp = arm64_ftr_reg_user_value(regp);
2167         else
2168                 /*
2169                  * The untracked registers are either IMPLEMENTATION DEFINED
2170                  * (e.g, ID_AFR0_EL1) or reserved RAZ.
2171                  */
2172                 *valp = 0;
2173         return 0;
2174 }
2175
2176 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
2177 {
2178         int rc;
2179         u64 val;
2180
2181         rc = emulate_sys_reg(sys_reg, &val);
2182         if (!rc) {
2183                 pt_regs_write_reg(regs, rt, val);
2184                 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
2185         }
2186         return rc;
2187 }
2188
2189 static int emulate_mrs(struct pt_regs *regs, u32 insn)
2190 {
2191         u32 sys_reg, rt;
2192
2193         /*
2194          * sys_reg values are defined as used in mrs/msr instruction.
2195          * shift the imm value to get the encoding.
2196          */
2197         sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
2198         rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
2199         return do_emulate_mrs(regs, sys_reg, rt);
2200 }
2201
2202 static struct undef_hook mrs_hook = {
2203         .instr_mask = 0xfff00000,
2204         .instr_val  = 0xd5300000,
2205         .pstate_mask = PSR_AA32_MODE_MASK,
2206         .pstate_val = PSR_MODE_EL0t,
2207         .fn = emulate_mrs,
2208 };
2209
2210 static int __init enable_mrs_emulation(void)
2211 {
2212         register_undef_hook(&mrs_hook);
2213         return 0;
2214 }
2215
2216 core_initcall(enable_mrs_emulation);
2217
2218 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
2219                           char *buf)
2220 {
2221         if (__meltdown_safe)
2222                 return sprintf(buf, "Not affected\n");
2223
2224         if (arm64_kernel_unmapped_at_el0())
2225                 return sprintf(buf, "Mitigation: PTI\n");
2226
2227         return sprintf(buf, "Vulnerable\n");
2228 }