arch/arm64/kernel/cpufeature.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Contains CPU feature definitions
   4  *
   5  * Copyright (C) 2015 ARM Ltd.
   6  *
   7  * A note for the weary kernel hacker: the code here is confusing and hard to
   8  * follow! That's partly because it's solving a nasty problem, but also because
   9  * there's a little bit of over-abstraction that tends to obscure what's going
  10  * on behind a maze of helper functions and macros.
  11  *
  12  * The basic problem is that hardware folks have started gluing together CPUs
  13  * with distinct architectural features; in some cases even creating SoCs where
  14  * user-visible instructions are available only on a subset of the available
  15  * cores. We try to address this by snapshotting the feature registers of the
  16  * boot CPU and comparing these with the feature registers of each secondary
  17  * CPU when bringing them up. If there is a mismatch, then we update the
  18  * snapshot state to indicate the lowest-common denominator of the feature,
  19  * known as the "safe" value. This snapshot state can be queried to view the
  20  * "sanitised" value of a feature register.
  21  *
  22  * The sanitised register values are used to decide which capabilities we
  23  * have in the system. These may be in the form of traditional "hwcaps"
  24  * advertised to userspace or internal "cpucaps" which are used to configure
  25  * things like alternative patching and static keys. While a feature mismatch
  26  * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch
  27  * may prevent a CPU from being onlined at all.
  28  *
  29  * Some implementation details worth remembering:
  30  *
  31  * - Mismatched features are *always* sanitised to a "safe" value, which
  32  *   usually indicates that the feature is not supported.
  33  *
  34  * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
  35  *   warning when onlining an offending CPU and the kernel will be tainted
  36  *   with TAINT_CPU_OUT_OF_SPEC.
  37  *
  38  * - Features marked as FTR_VISIBLE have their sanitised value visible to
  39  *   userspace. FTR_VISIBLE features in registers that are only visible
  40  *   to EL0 by trapping *must* have a corresponding HWCAP so that late
  41  *   onlining of CPUs cannot lead to features disappearing at runtime.
  42  *
  43  * - A "feature" is typically a 4-bit register field. A "capability" is the
  44  *   high-level description derived from the sanitised field value.
  45  *
  46  * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID
  47  *   scheme for fields in ID registers") to understand when feature fields
  48  *   may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly).
  49  *
  50  * - KVM exposes its own view of the feature registers to guest operating
  51  *   systems regardless of FTR_VISIBLE. This is typically driven from the
  52  *   sanitised register values to allow virtual CPUs to be migrated between
  53  *   arbitrary physical CPUs, but some features not present on the host are
  54  *   also advertised and emulated. Look at sys_reg_descs[] for the gory
  55  *   details.
  56  *
  57  * - If the arm64_ftr_bits[] for a register has a missing field, then this
  58  *   field is treated as STRICT RES0, including for read_sanitised_ftr_reg().
  59  *   This is stronger than FTR_HIDDEN and can be used to hide features from
  60  *   KVM guests.
  61  */
  62
  63 #define pr_fmt(fmt) "CPU features: " fmt
  64
  65 #include <linux/bsearch.h>
  66 #include <linux/cpumask.h>
  67 #include <linux/crash_dump.h>
  68 #include <linux/sort.h>
  69 #include <linux/stop_machine.h>
  70 #include <linux/types.h>
  71 #include <linux/mm.h>
  72 #include <linux/cpu.h>
  73 #include <asm/cpu.h>
  74 #include <asm/cpufeature.h>
  75 #include <asm/cpu_ops.h>
  76 #include <asm/fpsimd.h>
  77 #include <asm/mmu_context.h>
  78 #include <asm/processor.h>
  79 #include <asm/sysreg.h>
  80 #include <asm/traps.h>
  81 #include <asm/virt.h>
  82
  83 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
  84 static unsigned long elf_hwcap __read_mostly;
  85
  86 #ifdef CONFIG_COMPAT
  87 #define COMPAT_ELF_HWCAP_DEFAULT        \
  88                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  89                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  90                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
  91                                  COMPAT_HWCAP_LPAE)
  92 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  93 unsigned int compat_elf_hwcap2 __read_mostly;
  94 #endif
  95
  96 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  97 EXPORT_SYMBOL(cpu_hwcaps);
  98 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
  99
 100 /* Need also bit for ARM64_CB_PATCH */
 101 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
 102
 103 bool arm64_use_ng_mappings = false;
 104 EXPORT_SYMBOL(arm64_use_ng_mappings);
 105
 106 /*
 107  * Flag to indicate if we have computed the system wide
 108  * capabilities based on the boot time active CPUs. This
 109  * will be used to determine if a new booting CPU should
 110  * go through the verification process to make sure that it
 111  * supports the system capabilities, without using a hotplug
 112  * notifier. This is also used to decide if we could use
 113  * the fast path for checking constant CPU caps.
 114  */
 115 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
 116 EXPORT_SYMBOL(arm64_const_caps_ready);
 117 static inline void finalize_system_capabilities(void)
 118 {
 119         static_branch_enable(&arm64_const_caps_ready);
 120 }
 121
 122 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
 123 {
 124         /* file-wide pr_fmt adds "CPU features: " prefix */
 125         pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
 126         return 0;
 127 }
 128
 129 static struct notifier_block cpu_hwcaps_notifier = {
 130         .notifier_call = dump_cpu_hwcaps
 131 };
 132
 133 static int __init register_cpu_hwcaps_dumper(void)
 134 {
 135         atomic_notifier_chain_register(&panic_notifier_list,
 136                                        &cpu_hwcaps_notifier);
 137         return 0;
 138 }
 139 __initcall(register_cpu_hwcaps_dumper);
 140
 141 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
 142 EXPORT_SYMBOL(cpu_hwcap_keys);
 143
 144 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 145         {                                               \
 146                 .sign = SIGNED,                         \
 147                 .visible = VISIBLE,                     \
 148                 .strict = STRICT,                       \
 149                 .type = TYPE,                           \
 150                 .shift = SHIFT,                         \
 151                 .width = WIDTH,                         \
 152                 .safe_val = SAFE_VAL,                   \
 153         }
 154
 155 /* Define a feature with unsigned values */
 156 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 157         __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 158
 159 /* Define a feature with a signed value */
 160 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 161         __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 162
 163 #define ARM64_FTR_END                                   \
 164         {                                               \
 165                 .width = 0,                             \
 166         }
 167
 168 /* meta feature for alternatives */
 169 static bool __maybe_unused
 170 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
 171
 172 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
 173
 174 static bool __system_matches_cap(unsigned int n);
 175
 176 /*
 177  * NOTE: Any changes to the visibility of features should be kept in
 178  * sync with the documentation of the CPU feature register ABI.
 179  */
 180 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
 181         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0),
 182         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
 183         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
 184         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
 185         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
 186         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
 187         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
 188         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
 189         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
 190         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
 191         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
 192         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
 193         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
 194         ARM64_FTR_END,
 195 };
 196
 197 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
 198         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0),
 199         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0),
 200         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0),
 201         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0),
 202         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
 203         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
 204         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 205                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
 206         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 207                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
 208         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
 209         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
 210         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
 211         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 212                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0),
 213         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 214                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0),
 215         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
 216         ARM64_FTR_END,
 217 };
 218
 219 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
 220         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
 221         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
 222         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
 223         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0),
 224         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 225                                    FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
 226         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
 227         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
 228         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
 229         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
 230         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
 231         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
 232         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
 233         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
 234         ARM64_FTR_END,
 235 };
 236
 237 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
 238         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
 239         ARM64_FTR_END,
 240 };
 241
 242 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
 243         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 244                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0),
 245         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 246                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0),
 247         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 248                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0),
 249         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 250                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
 251         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 252                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
 253         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 254                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0),
 255         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 256                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
 257         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 258                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
 259         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 260                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
 261         ARM64_FTR_END,
 262 };
 263
 264 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 265         /*
 266          * We already refuse to boot CPUs that don't support our configured
 267          * page size, so we can only detect mismatches for a page size other
 268          * than the one we're currently using. Unfortunately, SoCs like this
 269          * exist in the wild so, even though we don't like it, we'll have to go
 270          * along with it and treat them as non-strict.
 271          */
 272         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 273         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 274         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 275
 276         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 277         /* Linux shouldn't care about secure memory */
 278         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 279         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 280         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 281         /*
 282          * Differing PARange is fine as long as all peripherals and memory are mapped
 283          * within the minimum PARange of all CPUs
 284          */
 285         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 286         ARM64_FTR_END,
 287 };
 288
 289 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 290         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 291         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 292         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 293         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 294         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 295         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 296         ARM64_FTR_END,
 297 };
 298
 299 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 300         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0),
 301         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
 302         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
 303         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
 304         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
 305         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
 306         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
 307         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
 308         ARM64_FTR_END,
 309 };
 310
 311 static const struct arm64_ftr_bits ftr_ctr[] = {
 312         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
 313         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
 314         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
 315         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
 316         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
 317         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
 318         /*
 319          * Linux can handle differing I-cache policies. Userspace JITs will
 320          * make use of *minLine.
 321          * If we have differing I-cache policies, report it as the weakest - VIPT.
 322          */
 323         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT),       /* L1Ip */
 324         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
 325         ARM64_FTR_END,
 326 };
 327
 328 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
 329         .name           = "SYS_CTR_EL0",
 330         .ftr_bits       = ftr_ctr
 331 };
 332
 333 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
 334         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf),   /* InnerShr */
 335         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),       /* FCSE */
 336         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),    /* AuxReg */
 337         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),       /* TCM */
 338         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),       /* ShareLvl */
 339         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf),    /* OuterShr */
 340         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* PMSA */
 341         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),        /* VMSA */
 342         ARM64_FTR_END,
 343 };
 344
 345 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 346         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
 347         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
 348         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 349         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 350         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 351         /*
 352          * We can instantiate multiple PMU instances with different levels
 353          * of support.
 354          */
 355         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 356         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
 357         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 358         ARM64_FTR_END,
 359 };
 360
 361 static const struct arm64_ftr_bits ftr_mvfr2[] = {
 362         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* FPMisc */
 363         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* SIMDMisc */
 364         ARM64_FTR_END,
 365 };
 366
 367 static const struct arm64_ftr_bits ftr_dczid[] = {
 368         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1),            /* DZP */
 369         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),       /* BS */
 370         ARM64_FTR_END,
 371 };
 372
 373
 374 static const struct arm64_ftr_bits ftr_id_isar5[] = {
 375         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
 376         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
 377         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
 378         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
 379         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
 380         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
 381         ARM64_FTR_END,
 382 };
 383
 384 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
 385         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* ac2 */
 386         ARM64_FTR_END,
 387 };
 388
 389 static const struct arm64_ftr_bits ftr_id_isar4[] = {
 390         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0),
 391         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0),
 392         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0),
 393         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0),
 394         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0),
 395         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0),
 396         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0),
 397         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0),
 398         ARM64_FTR_END,
 399 };
 400
 401 static const struct arm64_ftr_bits ftr_id_isar6[] = {
 402         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),
 403         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
 404         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),
 405         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
 406         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),
 407         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0),
 408         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0),
 409         ARM64_FTR_END,
 410 };
 411
 412 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
 413         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),               /* State3 */
 414         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),                /* State2 */
 415         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* State1 */
 416         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* State0 */
 417         ARM64_FTR_END,
 418 };
 419
 420 static const struct arm64_ftr_bits ftr_id_pfr1[] = {
 421         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0),
 422         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0),
 423         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0),
 424         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0),
 425         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0),
 426         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0),
 427         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0),
 428         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0),
 429         ARM64_FTR_END,
 430 };
 431
 432 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
 433         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 434         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf),   /* PerfMon */
 435         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 436         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 437         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 438         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 439         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 440         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 441         ARM64_FTR_END,
 442 };
 443
 444 static const struct arm64_ftr_bits ftr_zcr[] = {
 445         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
 446                 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0),        /* LEN */
 447         ARM64_FTR_END,
 448 };
 449
 450 /*
 451  * Common ftr bits for a 32bit register with all hidden, strict
 452  * attributes, with 4bit feature fields and a default safe value of
 453  * 0. Covers the following 32bit registers:
 454  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 455  */
 456 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
 457         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 458         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 459         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 460         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 461         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 462         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 463         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 464         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 465         ARM64_FTR_END,
 466 };
 467
 468 /* Table for a single 32bit feature value */
 469 static const struct arm64_ftr_bits ftr_single32[] = {
 470         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
 471         ARM64_FTR_END,
 472 };
 473
 474 static const struct arm64_ftr_bits ftr_raz[] = {
 475         ARM64_FTR_END,
 476 };
 477
 478 #define ARM64_FTR_REG(id, table) {              \
 479         .sys_id = id,                           \
 480         .reg =  &(struct arm64_ftr_reg){        \
 481                 .name = #id,                    \
 482                 .ftr_bits = &((table)[0]),      \
 483         }}
 484
 485 static const struct __ftr_reg_entry {
 486         u32                     sys_id;
 487         struct arm64_ftr_reg    *reg;
 488 } arm64_ftr_regs[] = {
 489
 490         /* Op1 = 0, CRn = 0, CRm = 1 */
 491         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 492         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1),
 493         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
 494         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 495         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 496         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 497         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 498
 499         /* Op1 = 0, CRn = 0, CRm = 2 */
 500         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 501         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 502         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 503         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 504         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4),
 505         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 506         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 507         ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
 508
 509         /* Op1 = 0, CRn = 0, CRm = 3 */
 510         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 511         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 512         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 513
 514         /* Op1 = 0, CRn = 0, CRm = 4 */
 515         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 516         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
 517         ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
 518
 519         /* Op1 = 0, CRn = 0, CRm = 5 */
 520         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 521         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
 522
 523         /* Op1 = 0, CRn = 0, CRm = 6 */
 524         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 525         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
 526
 527         /* Op1 = 0, CRn = 0, CRm = 7 */
 528         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 529         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 530         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
 531
 532         /* Op1 = 0, CRn = 1, CRm = 2 */
 533         ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
 534
 535         /* Op1 = 3, CRn = 0, CRm = 0 */
 536         { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
 537         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 538
 539         /* Op1 = 3, CRn = 14, CRm = 0 */
 540         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
 541 };
 542
 543 static int search_cmp_ftr_reg(const void *id, const void *regp)
 544 {
 545         return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
 546 }
 547
 548 /*
 549  * get_arm64_ftr_reg - Lookup a feature register entry using its
 550  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 551  * ascending order of sys_id , we use binary search to find a matching
 552  * entry.
 553  *
 554  * returns - Upon success,  matching ftr_reg entry for id.
 555  *         - NULL on failure. It is upto the caller to decide
 556  *           the impact of a failure.
 557  */
 558 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 559 {
 560         const struct __ftr_reg_entry *ret;
 561
 562         ret = bsearch((const void *)(unsigned long)sys_id,
 563                         arm64_ftr_regs,
 564                         ARRAY_SIZE(arm64_ftr_regs),
 565                         sizeof(arm64_ftr_regs[0]),
 566                         search_cmp_ftr_reg);
 567         if (ret)
 568                 return ret->reg;
 569         return NULL;
 570 }
 571
 572 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
 573                                s64 ftr_val)
 574 {
 575         u64 mask = arm64_ftr_mask(ftrp);
 576
 577         reg &= ~mask;
 578         reg |= (ftr_val << ftrp->shift) & mask;
 579         return reg;
 580 }
 581
 582 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
 583                                 s64 cur)
 584 {
 585         s64 ret = 0;
 586
 587         switch (ftrp->type) {
 588         case FTR_EXACT:
 589                 ret = ftrp->safe_val;
 590                 break;
 591         case FTR_LOWER_SAFE:
 592                 ret = new < cur ? new : cur;
 593                 break;
 594         case FTR_HIGHER_OR_ZERO_SAFE:
 595                 if (!cur || !new)
 596                         break;
 597                 /* Fallthrough */
 598         case FTR_HIGHER_SAFE:
 599                 ret = new > cur ? new : cur;
 600                 break;
 601         default:
 602                 BUG();
 603         }
 604
 605         return ret;
 606 }
 607
 608 static void __init sort_ftr_regs(void)
 609 {
 610         int i;
 611
 612         /* Check that the array is sorted so that we can do the binary search */
 613         for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
 614                 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
 615 }
 616
 617 /*
 618  * Initialise the CPU feature register from Boot CPU values.
 619  * Also initiliases the strict_mask for the register.
 620  * Any bits that are not covered by an arm64_ftr_bits entry are considered
 621  * RES0 for the system-wide value, and must strictly match.
 622  */
 623 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 624 {
 625         u64 val = 0;
 626         u64 strict_mask = ~0x0ULL;
 627         u64 user_mask = 0;
 628         u64 valid_mask = 0;
 629
 630         const struct arm64_ftr_bits *ftrp;
 631         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 632
 633         BUG_ON(!reg);
 634
 635         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 636                 u64 ftr_mask = arm64_ftr_mask(ftrp);
 637                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 638
 639                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 640
 641                 valid_mask |= ftr_mask;
 642                 if (!ftrp->strict)
 643                         strict_mask &= ~ftr_mask;
 644                 if (ftrp->visible)
 645                         user_mask |= ftr_mask;
 646                 else
 647                         reg->user_val = arm64_ftr_set_value(ftrp,
 648                                                             reg->user_val,
 649                                                             ftrp->safe_val);
 650         }
 651
 652         val &= valid_mask;
 653
 654         reg->sys_val = val;
 655         reg->strict_mask = strict_mask;
 656         reg->user_mask = user_mask;
 657 }
 658
 659 extern const struct arm64_cpu_capabilities arm64_errata[];
 660 static const struct arm64_cpu_capabilities arm64_features[];
 661
 662 static void __init
 663 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
 664 {
 665         for (; caps->matches; caps++) {
 666                 if (WARN(caps->capability >= ARM64_NCAPS,
 667                         "Invalid capability %d\n", caps->capability))
 668                         continue;
 669                 if (WARN(cpu_hwcaps_ptrs[caps->capability],
 670                         "Duplicate entry for capability %d\n",
 671                         caps->capability))
 672                         continue;
 673                 cpu_hwcaps_ptrs[caps->capability] = caps;
 674         }
 675 }
 676
 677 static void __init init_cpu_hwcaps_indirect_list(void)
 678 {
 679         init_cpu_hwcaps_indirect_list_from_array(arm64_features);
 680         init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
 681 }
 682
 683 static void __init setup_boot_cpu_capabilities(void);
 684
 685 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 686 {
 687         /* Before we start using the tables, make sure it is sorted */
 688         sort_ftr_regs();
 689
 690         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 691         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 692         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 693         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 694         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 695         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 696         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 697         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 698         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 699         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
 700         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 701         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 702         init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
 703
 704         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 705                 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 706                 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 707                 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 708                 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 709                 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 710                 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 711                 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 712                 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6);
 713                 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 714                 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 715                 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 716                 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 717                 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 718                 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 719                 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 720                 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 721                 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 722         }
 723
 724         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 725                 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
 726                 sve_init_vq_map();
 727         }
 728
 729         /*
 730          * Initialize the indirect array of CPU hwcaps capabilities pointers
 731          * before we handle the boot CPU below.
 732          */
 733         init_cpu_hwcaps_indirect_list();
 734
 735         /*
 736          * Detect and enable early CPU capabilities based on the boot CPU,
 737          * after we have initialised the CPU feature infrastructure.
 738          */
 739         setup_boot_cpu_capabilities();
 740 }
 741
 742 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 743 {
 744         const struct arm64_ftr_bits *ftrp;
 745
 746         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 747                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 748                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 749
 750                 if (ftr_cur == ftr_new)
 751                         continue;
 752                 /* Find a safe value */
 753                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 754                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 755         }
 756
 757 }
 758
 759 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 760 {
 761         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 762
 763         BUG_ON(!regp);
 764         update_cpu_ftr_reg(regp, val);
 765         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 766                 return 0;
 767         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 768                         regp->name, boot, cpu, val);
 769         return 1;
 770 }
 771
 772 static void relax_cpu_ftr_reg(u32 sys_id, int field)
 773 {
 774         const struct arm64_ftr_bits *ftrp;
 775         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 776
 777         if (WARN_ON(!regp))
 778                 return;
 779
 780         for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) {
 781                 if (ftrp->shift == field) {
 782                         regp->strict_mask &= ~arm64_ftr_mask(ftrp);
 783                         break;
 784                 }
 785         }
 786
 787         /* Bogus field? */
 788         WARN_ON(!ftrp->width);
 789 }
 790
 791 static int update_32bit_cpu_features(int cpu, struct cpuinfo_arm64 *info,
 792                                      struct cpuinfo_arm64 *boot)
 793 {
 794         int taint = 0;
 795         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
 796
 797         /*
 798          * If we don't have AArch32 at all then skip the checks entirely
 799          * as the register values may be UNKNOWN and we're not going to be
 800          * using them for anything.
 801          */
 802         if (!id_aa64pfr0_32bit_el0(pfr0))
 803                 return taint;
 804
 805         /*
 806          * If we don't have AArch32 at EL1, then relax the strictness of
 807          * EL1-dependent register fields to avoid spurious sanity check fails.
 808          */
 809         if (!id_aa64pfr0_32bit_el1(pfr0)) {
 810                 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT);
 811                 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT);
 812                 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT);
 813                 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT);
 814                 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT);
 815                 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT);
 816         }
 817
 818         taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 819                                       info->reg_id_dfr0, boot->reg_id_dfr0);
 820         taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 821                                       info->reg_id_isar0, boot->reg_id_isar0);
 822         taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 823                                       info->reg_id_isar1, boot->reg_id_isar1);
 824         taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 825                                       info->reg_id_isar2, boot->reg_id_isar2);
 826         taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 827                                       info->reg_id_isar3, boot->reg_id_isar3);
 828         taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 829                                       info->reg_id_isar4, boot->reg_id_isar4);
 830         taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 831                                       info->reg_id_isar5, boot->reg_id_isar5);
 832         taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu,
 833                                       info->reg_id_isar6, boot->reg_id_isar6);
 834
 835         /*
 836          * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 837          * ACTLR formats could differ across CPUs and therefore would have to
 838          * be trapped for virtualization anyway.
 839          */
 840         taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 841                                       info->reg_id_mmfr0, boot->reg_id_mmfr0);
 842         taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 843                                       info->reg_id_mmfr1, boot->reg_id_mmfr1);
 844         taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 845                                       info->reg_id_mmfr2, boot->reg_id_mmfr2);
 846         taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 847                                       info->reg_id_mmfr3, boot->reg_id_mmfr3);
 848         taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 849                                       info->reg_id_pfr0, boot->reg_id_pfr0);
 850         taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 851                                       info->reg_id_pfr1, boot->reg_id_pfr1);
 852         taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 853                                       info->reg_mvfr0, boot->reg_mvfr0);
 854         taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 855                                       info->reg_mvfr1, boot->reg_mvfr1);
 856         taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 857                                       info->reg_mvfr2, boot->reg_mvfr2);
 858
 859         return taint;
 860 }
 861
 862 /*
 863  * Update system wide CPU feature registers with the values from a
 864  * non-boot CPU. Also performs SANITY checks to make sure that there
 865  * aren't any insane variations from that of the boot CPU.
 866  */
 867 void update_cpu_features(int cpu,
 868                          struct cpuinfo_arm64 *info,
 869                          struct cpuinfo_arm64 *boot)
 870 {
 871         int taint = 0;
 872
 873         /*
 874          * The kernel can handle differing I-cache policies, but otherwise
 875          * caches should look identical. Userspace JITs will make use of
 876          * *minLine.
 877          */
 878         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 879                                       info->reg_ctr, boot->reg_ctr);
 880
 881         /*
 882          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 883          * could result in too much or too little memory being zeroed if a
 884          * process is preempted and migrated between CPUs.
 885          */
 886         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 887                                       info->reg_dczid, boot->reg_dczid);
 888
 889         /* If different, timekeeping will be broken (especially with KVM) */
 890         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 891                                       info->reg_cntfrq, boot->reg_cntfrq);
 892
 893         /*
 894          * The kernel uses self-hosted debug features and expects CPUs to
 895          * support identical debug features. We presently need CTX_CMPs, WRPs,
 896          * and BRPs to be identical.
 897          * ID_AA64DFR1 is currently RES0.
 898          */
 899         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 900                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 901         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 902                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 903         /*
 904          * Even in big.LITTLE, processors should be identical instruction-set
 905          * wise.
 906          */
 907         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 908                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 909         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 910                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 911
 912         /*
 913          * Differing PARange support is fine as long as all peripherals and
 914          * memory are mapped within the minimum PARange of all CPUs.
 915          * Linux should not care about secure memory.
 916          */
 917         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 918                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 919         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 920                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 921         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
 922                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
 923
 924         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 925                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 926         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 927                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 928
 929         taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
 930                                       info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
 931
 932         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 933                 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
 934                                         info->reg_zcr, boot->reg_zcr);
 935
 936                 /* Probe vector lengths, unless we already gave up on SVE */
 937                 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 938                     !system_capabilities_finalized())
 939                         sve_update_vq_map();
 940         }
 941
 942         /*
 943          * This relies on a sanitised view of the AArch64 ID registers
 944          * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last.
 945          */
 946         taint |= update_32bit_cpu_features(cpu, info, boot);
 947
 948         /*
 949          * Mismatched CPU features are a recipe for disaster. Don't even
 950          * pretend to support them.
 951          */
 952         if (taint) {
 953                 pr_warn_once("Unsupported CPU feature variation detected.\n");
 954                 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
 955         }
 956 }
 957
 958 u64 read_sanitised_ftr_reg(u32 id)
 959 {
 960         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 961
 962         /* We shouldn't get a request for an unsupported register */
 963         BUG_ON(!regp);
 964         return regp->sys_val;
 965 }
 966
 967 #define read_sysreg_case(r)     \
 968         case r:         return read_sysreg_s(r)
 969
 970 /*
 971  * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
 972  * Read the system register on the current CPU
 973  */
 974 static u64 __read_sysreg_by_encoding(u32 sys_id)
 975 {
 976         switch (sys_id) {
 977         read_sysreg_case(SYS_ID_PFR0_EL1);
 978         read_sysreg_case(SYS_ID_PFR1_EL1);
 979         read_sysreg_case(SYS_ID_DFR0_EL1);
 980         read_sysreg_case(SYS_ID_MMFR0_EL1);
 981         read_sysreg_case(SYS_ID_MMFR1_EL1);
 982         read_sysreg_case(SYS_ID_MMFR2_EL1);
 983         read_sysreg_case(SYS_ID_MMFR3_EL1);
 984         read_sysreg_case(SYS_ID_ISAR0_EL1);
 985         read_sysreg_case(SYS_ID_ISAR1_EL1);
 986         read_sysreg_case(SYS_ID_ISAR2_EL1);
 987         read_sysreg_case(SYS_ID_ISAR3_EL1);
 988         read_sysreg_case(SYS_ID_ISAR4_EL1);
 989         read_sysreg_case(SYS_ID_ISAR5_EL1);
 990         read_sysreg_case(SYS_ID_ISAR6_EL1);
 991         read_sysreg_case(SYS_MVFR0_EL1);
 992         read_sysreg_case(SYS_MVFR1_EL1);
 993         read_sysreg_case(SYS_MVFR2_EL1);
 994
 995         read_sysreg_case(SYS_ID_AA64PFR0_EL1);
 996         read_sysreg_case(SYS_ID_AA64PFR1_EL1);
 997         read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
 998         read_sysreg_case(SYS_ID_AA64DFR0_EL1);
 999         read_sysreg_case(SYS_ID_AA64DFR1_EL1);
1000         read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
1001         read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
1002         read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
1003         read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
1004         read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
1005
1006         read_sysreg_case(SYS_CNTFRQ_EL0);
1007         read_sysreg_case(SYS_CTR_EL0);
1008         read_sysreg_case(SYS_DCZID_EL0);
1009
1010         default:
1011                 BUG();
1012                 return 0;
1013         }
1014 }
1015
1016 #include <linux/irqchip/arm-gic-v3.h>
1017
1018 static bool
1019 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
1020 {
1021         int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
1022
1023         return val >= entry->min_field_value;
1024 }
1025
1026 static bool
1027 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
1028 {
1029         u64 val;
1030
1031         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1032         if (scope == SCOPE_SYSTEM)
1033                 val = read_sanitised_ftr_reg(entry->sys_reg);
1034         else
1035                 val = __read_sysreg_by_encoding(entry->sys_reg);
1036
1037         return feature_matches(val, entry);
1038 }
1039
1040 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
1041 {
1042         bool has_sre;
1043
1044         if (!has_cpuid_feature(entry, scope))
1045                 return false;
1046
1047         has_sre = gic_enable_sre();
1048         if (!has_sre)
1049                 pr_warn_once("%s present but disabled by higher exception level\n",
1050                              entry->desc);
1051
1052         return has_sre;
1053 }
1054
1055 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
1056 {
1057         u32 midr = read_cpuid_id();
1058
1059         /* Cavium ThunderX pass 1.x and 2.x */
1060         return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
1061                 MIDR_CPU_VAR_REV(0, 0),
1062                 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
1063 }
1064
1065 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
1066 {
1067         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1068
1069         return cpuid_feature_extract_signed_field(pfr0,
1070                                         ID_AA64PFR0_FP_SHIFT) < 0;
1071 }
1072
1073 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
1074                           int scope)
1075 {
1076         u64 ctr;
1077
1078         if (scope == SCOPE_SYSTEM)
1079                 ctr = arm64_ftr_reg_ctrel0.sys_val;
1080         else
1081                 ctr = read_cpuid_effective_cachetype();
1082
1083         return ctr & BIT(CTR_IDC_SHIFT);
1084 }
1085
1086 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
1087 {
1088         /*
1089          * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
1090          * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
1091          * to the CTR_EL0 on this CPU and emulate it with the real/safe
1092          * value.
1093          */
1094         if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
1095                 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
1096 }
1097
1098 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
1099                           int scope)
1100 {
1101         u64 ctr;
1102
1103         if (scope == SCOPE_SYSTEM)
1104                 ctr = arm64_ftr_reg_ctrel0.sys_val;
1105         else
1106                 ctr = read_cpuid_cachetype();
1107
1108         return ctr & BIT(CTR_DIC_SHIFT);
1109 }
1110
1111 static bool __maybe_unused
1112 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
1113 {
1114         /*
1115          * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
1116          * may share TLB entries with a CPU stuck in the crashed
1117          * kernel.
1118          */
1119          if (is_kdump_kernel())
1120                 return false;
1121
1122         return has_cpuid_feature(entry, scope);
1123 }
1124
1125 /*
1126  * This check is triggered during the early boot before the cpufeature
1127  * is initialised. Checking the status on the local CPU allows the boot
1128  * CPU to detect the need for non-global mappings and thus avoiding a
1129  * pagetable re-write after all the CPUs are booted. This check will be
1130  * anyway run on individual CPUs, allowing us to get the consistent
1131  * state once the SMP CPUs are up and thus make the switch to non-global
1132  * mappings if required.
1133  */
1134 bool kaslr_requires_kpti(void)
1135 {
1136         if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE))
1137                 return false;
1138
1139         /*
1140          * E0PD does a similar job to KPTI so can be used instead
1141          * where available.
1142          */
1143         if (IS_ENABLED(CONFIG_ARM64_E0PD)) {
1144                 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1);
1145                 if (cpuid_feature_extract_unsigned_field(mmfr2,
1146                                                 ID_AA64MMFR2_E0PD_SHIFT))
1147                         return false;
1148         }
1149
1150         /*
1151          * Systems affected by Cavium erratum 24756 are incompatible
1152          * with KPTI.
1153          */
1154         if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) {
1155                 extern const struct midr_range cavium_erratum_27456_cpus[];
1156
1157                 if (is_midr_in_range_list(read_cpuid_id(),
1158                                           cavium_erratum_27456_cpus))
1159                         return false;
1160         }
1161
1162         return kaslr_offset() > 0;
1163 }
1164
1165 static bool __meltdown_safe = true;
1166 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
1167
1168 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
1169                                 int scope)
1170 {
1171         /* List of CPUs that are not vulnerable and don't need KPTI */
1172         static const struct midr_range kpti_safe_list[] = {
1173                 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
1174                 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
1175                 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
1176                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
1177                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
1178                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1179                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
1180                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
1181                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
1182                 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
1183                 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
1184                 { /* sentinel */ }
1185         };
1186         char const *str = "kpti command line option";
1187         bool meltdown_safe;
1188
1189         meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
1190
1191         /* Defer to CPU feature registers */
1192         if (has_cpuid_feature(entry, scope))
1193                 meltdown_safe = true;
1194
1195         if (!meltdown_safe)
1196                 __meltdown_safe = false;
1197
1198         /*
1199          * For reasons that aren't entirely clear, enabling KPTI on Cavium
1200          * ThunderX leads to apparent I-cache corruption of kernel text, which
1201          * ends as well as you might imagine. Don't even try.
1202          */
1203         if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1204                 str = "ARM64_WORKAROUND_CAVIUM_27456";
1205                 __kpti_forced = -1;
1206         }
1207
1208         /* Useful for KASLR robustness */
1209         if (kaslr_requires_kpti()) {
1210                 if (!__kpti_forced) {
1211                         str = "KASLR";
1212                         __kpti_forced = 1;
1213                 }
1214         }
1215
1216         if (cpu_mitigations_off() && !__kpti_forced) {
1217                 str = "mitigations=off";
1218                 __kpti_forced = -1;
1219         }
1220
1221         if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1222                 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1223                 return false;
1224         }
1225
1226         /* Forced? */
1227         if (__kpti_forced) {
1228                 pr_info_once("kernel page table isolation forced %s by %s\n",
1229                              __kpti_forced > 0 ? "ON" : "OFF", str);
1230                 return __kpti_forced > 0;
1231         }
1232
1233         return !meltdown_safe;
1234 }
1235
1236 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1237 static void
1238 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1239 {
1240         typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1241         extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1242         kpti_remap_fn *remap_fn;
1243
1244         int cpu = smp_processor_id();
1245
1246         /*
1247          * We don't need to rewrite the page-tables if either we've done
1248          * it already or we have KASLR enabled and therefore have not
1249          * created any global mappings at all.
1250          */
1251         if (arm64_use_ng_mappings)
1252                 return;
1253
1254         remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
1255
1256         cpu_install_idmap();
1257         remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1258         cpu_uninstall_idmap();
1259
1260         if (!cpu)
1261                 arm64_use_ng_mappings = true;
1262
1263         return;
1264 }
1265 #else
1266 static void
1267 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1268 {
1269 }
1270 #endif  /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1271
1272 static int __init parse_kpti(char *str)
1273 {
1274         bool enabled;
1275         int ret = strtobool(str, &enabled);
1276
1277         if (ret)
1278                 return ret;
1279
1280         __kpti_forced = enabled ? 1 : -1;
1281         return 0;
1282 }
1283 early_param("kpti", parse_kpti);
1284
1285 #ifdef CONFIG_ARM64_HW_AFDBM
1286 static inline void __cpu_enable_hw_dbm(void)
1287 {
1288         u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1289
1290         write_sysreg(tcr, tcr_el1);
1291         isb();
1292 }
1293
1294 static bool cpu_has_broken_dbm(void)
1295 {
1296         /* List of CPUs which have broken DBM support. */
1297         static const struct midr_range cpus[] = {
1298 #ifdef CONFIG_ARM64_ERRATUM_1024718
1299                 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0),  // A55 r0p0 -r1p0
1300 #endif
1301                 {},
1302         };
1303
1304         return is_midr_in_range_list(read_cpuid_id(), cpus);
1305 }
1306
1307 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1308 {
1309         return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1310                !cpu_has_broken_dbm();
1311 }
1312
1313 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1314 {
1315         if (cpu_can_use_dbm(cap))
1316                 __cpu_enable_hw_dbm();
1317 }
1318
1319 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1320                        int __unused)
1321 {
1322         static bool detected = false;
1323         /*
1324          * DBM is a non-conflicting feature. i.e, the kernel can safely
1325          * run a mix of CPUs with and without the feature. So, we
1326          * unconditionally enable the capability to allow any late CPU
1327          * to use the feature. We only enable the control bits on the
1328          * CPU, if it actually supports.
1329          *
1330          * We have to make sure we print the "feature" detection only
1331          * when at least one CPU actually uses it. So check if this CPU
1332          * can actually use it and print the message exactly once.
1333          *
1334          * This is safe as all CPUs (including secondary CPUs - due to the
1335          * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1336          * goes through the "matches" check exactly once. Also if a CPU
1337          * matches the criteria, it is guaranteed that the CPU will turn
1338          * the DBM on, as the capability is unconditionally enabled.
1339          */
1340         if (!detected && cpu_can_use_dbm(cap)) {
1341                 detected = true;
1342                 pr_info("detected: Hardware dirty bit management\n");
1343         }
1344
1345         return true;
1346 }
1347
1348 #endif
1349
1350 #ifdef CONFIG_ARM64_AMU_EXTN
1351
1352 /*
1353  * The "amu_cpus" cpumask only signals that the CPU implementation for the
1354  * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide
1355  * information regarding all the events that it supports. When a CPU bit is
1356  * set in the cpumask, the user of this feature can only rely on the presence
1357  * of the 4 fixed counters for that CPU. But this does not guarantee that the
1358  * counters are enabled or access to these counters is enabled by code
1359  * executed at higher exception levels (firmware).
1360  */
1361 static struct cpumask amu_cpus __read_mostly;
1362
1363 bool cpu_has_amu_feat(int cpu)
1364 {
1365         return cpumask_test_cpu(cpu, &amu_cpus);
1366 }
1367
1368 /* Initialize the use of AMU counters for frequency invariance */
1369 extern void init_cpu_freq_invariance_counters(void);
1370
1371 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
1372 {
1373         if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) {
1374                 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n",
1375                         smp_processor_id());
1376                 cpumask_set_cpu(smp_processor_id(), &amu_cpus);
1377                 init_cpu_freq_invariance_counters();
1378         }
1379 }
1380
1381 static bool has_amu(const struct arm64_cpu_capabilities *cap,
1382                     int __unused)
1383 {
1384         /*
1385          * The AMU extension is a non-conflicting feature: the kernel can
1386          * safely run a mix of CPUs with and without support for the
1387          * activity monitors extension. Therefore, unconditionally enable
1388          * the capability to allow any late CPU to use the feature.
1389          *
1390          * With this feature unconditionally enabled, the cpu_enable
1391          * function will be called for all CPUs that match the criteria,
1392          * including secondary and hotplugged, marking this feature as
1393          * present on that respective CPU. The enable function will also
1394          * print a detection message.
1395          */
1396
1397         return true;
1398 }
1399 #endif
1400
1401 #ifdef CONFIG_ARM64_VHE
1402 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1403 {
1404         return is_kernel_in_hyp_mode();
1405 }
1406
1407 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1408 {
1409         /*
1410          * Copy register values that aren't redirected by hardware.
1411          *
1412          * Before code patching, we only set tpidr_el1, all CPUs need to copy
1413          * this value to tpidr_el2 before we patch the code. Once we've done
1414          * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1415          * do anything here.
1416          */
1417         if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1418                 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1419 }
1420 #endif
1421
1422 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1423 {
1424         u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1425
1426         /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1427         WARN_ON(val & (7 << 27 | 7 << 21));
1428 }
1429
1430 #ifdef CONFIG_ARM64_SSBD
1431 static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
1432 {
1433         if (user_mode(regs))
1434                 return 1;
1435
1436         if (instr & BIT(PSTATE_Imm_shift))
1437                 regs->pstate |= PSR_SSBS_BIT;
1438         else
1439                 regs->pstate &= ~PSR_SSBS_BIT;
1440
1441         arm64_skip_faulting_instruction(regs, 4);
1442         return 0;
1443 }
1444
1445 static struct undef_hook ssbs_emulation_hook = {
1446         .instr_mask     = ~(1U << PSTATE_Imm_shift),
1447         .instr_val      = 0xd500401f | PSTATE_SSBS,
1448         .fn             = ssbs_emulation_handler,
1449 };
1450
1451 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
1452 {
1453         static bool undef_hook_registered = false;
1454         static DEFINE_RAW_SPINLOCK(hook_lock);
1455
1456         raw_spin_lock(&hook_lock);
1457         if (!undef_hook_registered) {
1458                 register_undef_hook(&ssbs_emulation_hook);
1459                 undef_hook_registered = true;
1460         }
1461         raw_spin_unlock(&hook_lock);
1462
1463         if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
1464                 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
1465                 arm64_set_ssbd_mitigation(false);
1466         } else {
1467                 arm64_set_ssbd_mitigation(true);
1468         }
1469 }
1470 #endif /* CONFIG_ARM64_SSBD */
1471
1472 #ifdef CONFIG_ARM64_PAN
1473 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1474 {
1475         /*
1476          * We modify PSTATE. This won't work from irq context as the PSTATE
1477          * is discarded once we return from the exception.
1478          */
1479         WARN_ON_ONCE(in_interrupt());
1480
1481         sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1482         asm(SET_PSTATE_PAN(1));
1483 }
1484 #endif /* CONFIG_ARM64_PAN */
1485
1486 #ifdef CONFIG_ARM64_RAS_EXTN
1487 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1488 {
1489         /* Firmware may have left a deferred SError in this register. */
1490         write_sysreg_s(0, SYS_DISR_EL1);
1491 }
1492 #endif /* CONFIG_ARM64_RAS_EXTN */
1493
1494 #ifdef CONFIG_ARM64_PTR_AUTH
1495 static bool has_address_auth(const struct arm64_cpu_capabilities *entry,
1496                              int __unused)
1497 {
1498         return __system_matches_cap(ARM64_HAS_ADDRESS_AUTH_ARCH) ||
1499                __system_matches_cap(ARM64_HAS_ADDRESS_AUTH_IMP_DEF);
1500 }
1501
1502 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,
1503                              int __unused)
1504 {
1505         return __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH) ||
1506                __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF);
1507 }
1508 #endif /* CONFIG_ARM64_PTR_AUTH */
1509
1510 #ifdef CONFIG_ARM64_E0PD
1511 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
1512 {
1513         if (this_cpu_has_cap(ARM64_HAS_E0PD))
1514                 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
1515 }
1516 #endif /* CONFIG_ARM64_E0PD */
1517
1518 #ifdef CONFIG_ARM64_PSEUDO_NMI
1519 static bool enable_pseudo_nmi;
1520
1521 static int __init early_enable_pseudo_nmi(char *p)
1522 {
1523         return strtobool(p, &enable_pseudo_nmi);
1524 }
1525 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1526
1527 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1528                                    int scope)
1529 {
1530         return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
1531 }
1532 #endif
1533
1534 /* Internal helper functions to match cpu capability type */
1535 static bool
1536 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
1537 {
1538         return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);
1539 }
1540
1541 static bool
1542 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap)
1543 {
1544         return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);
1545 }
1546
1547 static bool
1548 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap)
1549 {
1550         return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT);
1551 }
1552
1553 static const struct arm64_cpu_capabilities arm64_features[] = {
1554         {
1555                 .desc = "GIC system register CPU interface",
1556                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1557                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1558                 .matches = has_useable_gicv3_cpuif,
1559                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1560                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1561                 .sign = FTR_UNSIGNED,
1562                 .min_field_value = 1,
1563         },
1564 #ifdef CONFIG_ARM64_PAN
1565         {
1566                 .desc = "Privileged Access Never",
1567                 .capability = ARM64_HAS_PAN,
1568                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1569                 .matches = has_cpuid_feature,
1570                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1571                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1572                 .sign = FTR_UNSIGNED,
1573                 .min_field_value = 1,
1574                 .cpu_enable = cpu_enable_pan,
1575         },
1576 #endif /* CONFIG_ARM64_PAN */
1577 #ifdef CONFIG_ARM64_LSE_ATOMICS
1578         {
1579                 .desc = "LSE atomic instructions",
1580                 .capability = ARM64_HAS_LSE_ATOMICS,
1581                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1582                 .matches = has_cpuid_feature,
1583                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1584                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1585                 .sign = FTR_UNSIGNED,
1586                 .min_field_value = 2,
1587         },
1588 #endif /* CONFIG_ARM64_LSE_ATOMICS */
1589         {
1590                 .desc = "Software prefetching using PRFM",
1591                 .capability = ARM64_HAS_NO_HW_PREFETCH,
1592                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1593                 .matches = has_no_hw_prefetch,
1594         },
1595 #ifdef CONFIG_ARM64_UAO
1596         {
1597                 .desc = "User Access Override",
1598                 .capability = ARM64_HAS_UAO,
1599                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1600                 .matches = has_cpuid_feature,
1601                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1602                 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1603                 .min_field_value = 1,
1604                 /*
1605                  * We rely on stop_machine() calling uao_thread_switch() to set
1606                  * UAO immediately after patching.
1607                  */
1608         },
1609 #endif /* CONFIG_ARM64_UAO */
1610 #ifdef CONFIG_ARM64_PAN
1611         {
1612                 .capability = ARM64_ALT_PAN_NOT_UAO,
1613                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1614                 .matches = cpufeature_pan_not_uao,
1615         },
1616 #endif /* CONFIG_ARM64_PAN */
1617 #ifdef CONFIG_ARM64_VHE
1618         {
1619                 .desc = "Virtualization Host Extensions",
1620                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1621                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1622                 .matches = runs_at_el2,
1623                 .cpu_enable = cpu_copy_el2regs,
1624         },
1625 #endif  /* CONFIG_ARM64_VHE */
1626         {
1627                 .desc = "32-bit EL0 Support",
1628                 .capability = ARM64_HAS_32BIT_EL0,
1629                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1630                 .matches = has_cpuid_feature,
1631                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1632                 .sign = FTR_UNSIGNED,
1633                 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1634                 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1635         },
1636 #ifdef CONFIG_KVM
1637         {
1638                 .desc = "32-bit EL1 Support",
1639                 .capability = ARM64_HAS_32BIT_EL1,
1640                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1641                 .matches = has_cpuid_feature,
1642                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1643                 .sign = FTR_UNSIGNED,
1644                 .field_pos = ID_AA64PFR0_EL1_SHIFT,
1645                 .min_field_value = ID_AA64PFR0_EL1_32BIT_64BIT,
1646         },
1647 #endif
1648         {
1649                 .desc = "Kernel page table isolation (KPTI)",
1650                 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1651                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1652                 /*
1653                  * The ID feature fields below are used to indicate that
1654                  * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1655                  * more details.
1656                  */
1657                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1658                 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1659                 .min_field_value = 1,
1660                 .matches = unmap_kernel_at_el0,
1661                 .cpu_enable = kpti_install_ng_mappings,
1662         },
1663         {
1664                 /* FP/SIMD is not implemented */
1665                 .capability = ARM64_HAS_NO_FPSIMD,
1666                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1667                 .min_field_value = 0,
1668                 .matches = has_no_fpsimd,
1669         },
1670 #ifdef CONFIG_ARM64_PMEM
1671         {
1672                 .desc = "Data cache clean to Point of Persistence",
1673                 .capability = ARM64_HAS_DCPOP,
1674                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1675                 .matches = has_cpuid_feature,
1676                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1677                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1678                 .min_field_value = 1,
1679         },
1680         {
1681                 .desc = "Data cache clean to Point of Deep Persistence",
1682                 .capability = ARM64_HAS_DCPODP,
1683                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1684                 .matches = has_cpuid_feature,
1685                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1686                 .sign = FTR_UNSIGNED,
1687                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1688                 .min_field_value = 2,
1689         },
1690 #endif
1691 #ifdef CONFIG_ARM64_SVE
1692         {
1693                 .desc = "Scalable Vector Extension",
1694                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1695                 .capability = ARM64_SVE,
1696                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1697                 .sign = FTR_UNSIGNED,
1698                 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1699                 .min_field_value = ID_AA64PFR0_SVE,
1700                 .matches = has_cpuid_feature,
1701                 .cpu_enable = sve_kernel_enable,
1702         },
1703 #endif /* CONFIG_ARM64_SVE */
1704 #ifdef CONFIG_ARM64_RAS_EXTN
1705         {
1706                 .desc = "RAS Extension Support",
1707                 .capability = ARM64_HAS_RAS_EXTN,
1708                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1709                 .matches = has_cpuid_feature,
1710                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1711                 .sign = FTR_UNSIGNED,
1712                 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1713                 .min_field_value = ID_AA64PFR0_RAS_V1,
1714                 .cpu_enable = cpu_clear_disr,
1715         },
1716 #endif /* CONFIG_ARM64_RAS_EXTN */
1717 #ifdef CONFIG_ARM64_AMU_EXTN
1718         {
1719                 /*
1720                  * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y.
1721                  * Therefore, don't provide .desc as we don't want the detection
1722                  * message to be shown until at least one CPU is detected to
1723                  * support the feature.
1724                  */
1725                 .capability = ARM64_HAS_AMU_EXTN,
1726                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1727                 .matches = has_amu,
1728                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1729                 .sign = FTR_UNSIGNED,
1730                 .field_pos = ID_AA64PFR0_AMU_SHIFT,
1731                 .min_field_value = ID_AA64PFR0_AMU,
1732                 .cpu_enable = cpu_amu_enable,
1733         },
1734 #endif /* CONFIG_ARM64_AMU_EXTN */
1735         {
1736                 .desc = "Data cache clean to the PoU not required for I/D coherence",
1737                 .capability = ARM64_HAS_CACHE_IDC,
1738                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1739                 .matches = has_cache_idc,
1740                 .cpu_enable = cpu_emulate_effective_ctr,
1741         },
1742         {
1743                 .desc = "Instruction cache invalidation not required for I/D coherence",
1744                 .capability = ARM64_HAS_CACHE_DIC,
1745                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1746                 .matches = has_cache_dic,
1747         },
1748         {
1749                 .desc = "Stage-2 Force Write-Back",
1750                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1751                 .capability = ARM64_HAS_STAGE2_FWB,
1752                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1753                 .sign = FTR_UNSIGNED,
1754                 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
1755                 .min_field_value = 1,
1756                 .matches = has_cpuid_feature,
1757                 .cpu_enable = cpu_has_fwb,
1758         },
1759 #ifdef CONFIG_ARM64_HW_AFDBM
1760         {
1761                 /*
1762                  * Since we turn this on always, we don't want the user to
1763                  * think that the feature is available when it may not be.
1764                  * So hide the description.
1765                  *
1766                  * .desc = "Hardware pagetable Dirty Bit Management",
1767                  *
1768                  */
1769                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1770                 .capability = ARM64_HW_DBM,
1771                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1772                 .sign = FTR_UNSIGNED,
1773                 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
1774                 .min_field_value = 2,
1775                 .matches = has_hw_dbm,
1776                 .cpu_enable = cpu_enable_hw_dbm,
1777         },
1778 #endif
1779         {
1780                 .desc = "CRC32 instructions",
1781                 .capability = ARM64_HAS_CRC32,
1782                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1783                 .matches = has_cpuid_feature,
1784                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1785                 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
1786                 .min_field_value = 1,
1787         },
1788 #ifdef CONFIG_ARM64_SSBD
1789         {
1790                 .desc = "Speculative Store Bypassing Safe (SSBS)",
1791                 .capability = ARM64_SSBS,
1792                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1793                 .matches = has_cpuid_feature,
1794                 .sys_reg = SYS_ID_AA64PFR1_EL1,
1795                 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
1796                 .sign = FTR_UNSIGNED,
1797                 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
1798                 .cpu_enable = cpu_enable_ssbs,
1799         },
1800 #endif
1801 #ifdef CONFIG_ARM64_CNP
1802         {
1803                 .desc = "Common not Private translations",
1804                 .capability = ARM64_HAS_CNP,
1805                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1806                 .matches = has_useable_cnp,
1807                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1808                 .sign = FTR_UNSIGNED,
1809                 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
1810                 .min_field_value = 1,
1811                 .cpu_enable = cpu_enable_cnp,
1812         },
1813 #endif
1814         {
1815                 .desc = "Speculation barrier (SB)",
1816                 .capability = ARM64_HAS_SB,
1817                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1818                 .matches = has_cpuid_feature,
1819                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1820                 .field_pos = ID_AA64ISAR1_SB_SHIFT,
1821                 .sign = FTR_UNSIGNED,
1822                 .min_field_value = 1,
1823         },
1824 #ifdef CONFIG_ARM64_PTR_AUTH
1825         {
1826                 .desc = "Address authentication (architected algorithm)",
1827                 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
1828                 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
1829                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1830                 .sign = FTR_UNSIGNED,
1831                 .field_pos = ID_AA64ISAR1_APA_SHIFT,
1832                 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
1833                 .matches = has_cpuid_feature,
1834         },
1835         {
1836                 .desc = "Address authentication (IMP DEF algorithm)",
1837                 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
1838                 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
1839                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1840                 .sign = FTR_UNSIGNED,
1841                 .field_pos = ID_AA64ISAR1_API_SHIFT,
1842                 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
1843                 .matches = has_cpuid_feature,
1844         },
1845         {
1846                 .capability = ARM64_HAS_ADDRESS_AUTH,
1847                 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
1848                 .matches = has_address_auth,
1849         },
1850         {
1851                 .desc = "Generic authentication (architected algorithm)",
1852                 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
1853                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1854                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1855                 .sign = FTR_UNSIGNED,
1856                 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
1857                 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
1858                 .matches = has_cpuid_feature,
1859         },
1860         {
1861                 .desc = "Generic authentication (IMP DEF algorithm)",
1862                 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
1863                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1864                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1865                 .sign = FTR_UNSIGNED,
1866                 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
1867                 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
1868                 .matches = has_cpuid_feature,
1869         },
1870         {
1871                 .capability = ARM64_HAS_GENERIC_AUTH,
1872                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1873                 .matches = has_generic_auth,
1874         },
1875 #endif /* CONFIG_ARM64_PTR_AUTH */
1876 #ifdef CONFIG_ARM64_PSEUDO_NMI
1877         {
1878                 /*
1879                  * Depends on having GICv3
1880                  */
1881                 .desc = "IRQ priority masking",
1882                 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
1883                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1884                 .matches = can_use_gic_priorities,
1885                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1886                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1887                 .sign = FTR_UNSIGNED,
1888                 .min_field_value = 1,
1889         },
1890 #endif
1891 #ifdef CONFIG_ARM64_E0PD
1892         {
1893                 .desc = "E0PD",
1894                 .capability = ARM64_HAS_E0PD,
1895                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1896                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1897                 .sign = FTR_UNSIGNED,
1898                 .field_pos = ID_AA64MMFR2_E0PD_SHIFT,
1899                 .matches = has_cpuid_feature,
1900                 .min_field_value = 1,
1901                 .cpu_enable = cpu_enable_e0pd,
1902         },
1903 #endif
1904 #ifdef CONFIG_ARCH_RANDOM
1905         {
1906                 .desc = "Random Number Generator",
1907                 .capability = ARM64_HAS_RNG,
1908                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1909                 .matches = has_cpuid_feature,
1910                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1911                 .field_pos = ID_AA64ISAR0_RNDR_SHIFT,
1912                 .sign = FTR_UNSIGNED,
1913                 .min_field_value = 1,
1914         },
1915 #endif
1916         {},
1917 };
1918
1919 #define HWCAP_CPUID_MATCH(reg, field, s, min_value)                             \
1920                 .matches = has_cpuid_feature,                                   \
1921                 .sys_reg = reg,                                                 \
1922                 .field_pos = field,                                             \
1923                 .sign = s,                                                      \
1924                 .min_field_value = min_value,
1925
1926 #define __HWCAP_CAP(name, cap_type, cap)                                        \
1927                 .desc = name,                                                   \
1928                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,                            \
1929                 .hwcap_type = cap_type,                                         \
1930                 .hwcap = cap,                                                   \
1931
1932 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap)                      \
1933         {                                                                       \
1934                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1935                 HWCAP_CPUID_MATCH(reg, field, s, min_value)                     \
1936         }
1937
1938 #define HWCAP_MULTI_CAP(list, cap_type, cap)                                    \
1939         {                                                                       \
1940                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1941                 .matches = cpucap_multi_entry_cap_matches,                      \
1942                 .match_list = list,                                             \
1943         }
1944
1945 #define HWCAP_CAP_MATCH(match, cap_type, cap)                                   \
1946         {                                                                       \
1947                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1948                 .matches = match,                                               \
1949         }
1950
1951 #ifdef CONFIG_ARM64_PTR_AUTH
1952 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
1953         {
1954                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
1955                                   FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
1956         },
1957         {
1958                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
1959                                   FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
1960         },
1961         {},
1962 };
1963
1964 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
1965         {
1966                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
1967                                   FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
1968         },
1969         {
1970                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
1971                                   FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
1972         },
1973         {},
1974 };
1975 #endif
1976
1977 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
1978         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
1979         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
1980         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
1981         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
1982         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
1983         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
1984         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
1985         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
1986         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
1987         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
1988         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
1989         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
1990         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
1991         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
1992         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
1993         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG),
1994         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
1995         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
1996         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
1997         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
1998         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
1999         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
2000         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
2001         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
2002         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
2003         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
2004         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
2005         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
2006         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
2007         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16),
2008         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH),
2009         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM),
2010         HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
2011 #ifdef CONFIG_ARM64_SVE
2012         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
2013         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
2014         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
2015         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
2016         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
2017         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
2018         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
2019         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
2020         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
2021         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
2022         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
2023 #endif
2024         HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
2025 #ifdef CONFIG_ARM64_PTR_AUTH
2026         HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
2027         HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
2028 #endif
2029         {},
2030 };
2031
2032 #ifdef CONFIG_COMPAT
2033 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
2034 {
2035         /*
2036          * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
2037          * in line with that of arm32 as in vfp_init(). We make sure that the
2038          * check is future proof, by making sure value is non-zero.
2039          */
2040         u32 mvfr1;
2041
2042         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
2043         if (scope == SCOPE_SYSTEM)
2044                 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
2045         else
2046                 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
2047
2048         return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
2049                 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
2050                 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
2051 }
2052 #endif
2053
2054 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
2055 #ifdef CONFIG_COMPAT
2056         HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
2057         HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
2058         /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
2059         HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
2060         HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
2061         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
2062         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
2063         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
2064         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
2065         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
2066 #endif
2067         {},
2068 };
2069
2070 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2071 {
2072         switch (cap->hwcap_type) {
2073         case CAP_HWCAP:
2074                 cpu_set_feature(cap->hwcap);
2075                 break;
2076 #ifdef CONFIG_COMPAT
2077         case CAP_COMPAT_HWCAP:
2078                 compat_elf_hwcap |= (u32)cap->hwcap;
2079                 break;
2080         case CAP_COMPAT_HWCAP2:
2081                 compat_elf_hwcap2 |= (u32)cap->hwcap;
2082                 break;
2083 #endif
2084         default:
2085                 WARN_ON(1);
2086                 break;
2087         }
2088 }
2089
2090 /* Check if we have a particular HWCAP enabled */
2091 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2092 {
2093         bool rc;
2094
2095         switch (cap->hwcap_type) {
2096         case CAP_HWCAP:
2097                 rc = cpu_have_feature(cap->hwcap);
2098                 break;
2099 #ifdef CONFIG_COMPAT
2100         case CAP_COMPAT_HWCAP:
2101                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
2102                 break;
2103         case CAP_COMPAT_HWCAP2:
2104                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
2105                 break;
2106 #endif
2107         default:
2108                 WARN_ON(1);
2109                 rc = false;
2110         }
2111
2112         return rc;
2113 }
2114
2115 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
2116 {
2117         /* We support emulation of accesses to CPU ID feature registers */
2118         cpu_set_named_feature(CPUID);
2119         for (; hwcaps->matches; hwcaps++)
2120                 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
2121                         cap_set_elf_hwcap(hwcaps);
2122 }
2123
2124 static void update_cpu_capabilities(u16 scope_mask)
2125 {
2126         int i;
2127         const struct arm64_cpu_capabilities *caps;
2128
2129         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2130         for (i = 0; i < ARM64_NCAPS; i++) {
2131                 caps = cpu_hwcaps_ptrs[i];
2132                 if (!caps || !(caps->type & scope_mask) ||
2133                     cpus_have_cap(caps->capability) ||
2134                     !caps->matches(caps, cpucap_default_scope(caps)))
2135                         continue;
2136
2137                 if (caps->desc)
2138                         pr_info("detected: %s\n", caps->desc);
2139                 cpus_set_cap(caps->capability);
2140
2141                 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
2142                         set_bit(caps->capability, boot_capabilities);
2143         }
2144 }
2145
2146 /*
2147  * Enable all the available capabilities on this CPU. The capabilities
2148  * with BOOT_CPU scope are handled separately and hence skipped here.
2149  */
2150 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
2151 {
2152         int i;
2153         u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
2154
2155         for_each_available_cap(i) {
2156                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
2157
2158                 if (WARN_ON(!cap))
2159                         continue;
2160
2161                 if (!(cap->type & non_boot_scope))
2162                         continue;
2163
2164                 if (cap->cpu_enable)
2165                         cap->cpu_enable(cap);
2166         }
2167         return 0;
2168 }
2169
2170 /*
2171  * Run through the enabled capabilities and enable() it on all active
2172  * CPUs
2173  */
2174 static void __init enable_cpu_capabilities(u16 scope_mask)
2175 {
2176         int i;
2177         const struct arm64_cpu_capabilities *caps;
2178         bool boot_scope;
2179
2180         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2181         boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
2182
2183         for (i = 0; i < ARM64_NCAPS; i++) {
2184                 unsigned int num;
2185
2186                 caps = cpu_hwcaps_ptrs[i];
2187                 if (!caps || !(caps->type & scope_mask))
2188                         continue;
2189                 num = caps->capability;
2190                 if (!cpus_have_cap(num))
2191                         continue;
2192
2193                 /* Ensure cpus_have_const_cap(num) works */
2194                 static_branch_enable(&cpu_hwcap_keys[num]);
2195
2196                 if (boot_scope && caps->cpu_enable)
2197                         /*
2198                          * Capabilities with SCOPE_BOOT_CPU scope are finalised
2199                          * before any secondary CPU boots. Thus, each secondary
2200                          * will enable the capability as appropriate via
2201                          * check_local_cpu_capabilities(). The only exception is
2202                          * the boot CPU, for which the capability must be
2203                          * enabled here. This approach avoids costly
2204                          * stop_machine() calls for this case.
2205                          */
2206                         caps->cpu_enable(caps);
2207         }
2208
2209         /*
2210          * For all non-boot scope capabilities, use stop_machine()
2211          * as it schedules the work allowing us to modify PSTATE,
2212          * instead of on_each_cpu() which uses an IPI, giving us a
2213          * PSTATE that disappears when we return.
2214          */
2215         if (!boot_scope)
2216                 stop_machine(cpu_enable_non_boot_scope_capabilities,
2217                              NULL, cpu_online_mask);
2218 }
2219
2220 /*
2221  * Run through the list of capabilities to check for conflicts.
2222  * If the system has already detected a capability, take necessary
2223  * action on this CPU.
2224  */
2225 static void verify_local_cpu_caps(u16 scope_mask)
2226 {
2227         int i;
2228         bool cpu_has_cap, system_has_cap;
2229         const struct arm64_cpu_capabilities *caps;
2230
2231         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2232
2233         for (i = 0; i < ARM64_NCAPS; i++) {
2234                 caps = cpu_hwcaps_ptrs[i];
2235                 if (!caps || !(caps->type & scope_mask))
2236                         continue;
2237
2238                 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
2239                 system_has_cap = cpus_have_cap(caps->capability);
2240
2241                 if (system_has_cap) {
2242                         /*
2243                          * Check if the new CPU misses an advertised feature,
2244                          * which is not safe to miss.
2245                          */
2246                         if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
2247                                 break;
2248                         /*
2249                          * We have to issue cpu_enable() irrespective of
2250                          * whether the CPU has it or not, as it is enabeld
2251                          * system wide. It is upto the call back to take
2252                          * appropriate action on this CPU.
2253                          */
2254                         if (caps->cpu_enable)
2255                                 caps->cpu_enable(caps);
2256                 } else {
2257                         /*
2258                          * Check if the CPU has this capability if it isn't
2259                          * safe to have when the system doesn't.
2260                          */
2261                         if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
2262                                 break;
2263                 }
2264         }
2265
2266         if (i < ARM64_NCAPS) {
2267                 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
2268                         smp_processor_id(), caps->capability,
2269                         caps->desc, system_has_cap, cpu_has_cap);
2270
2271                 if (cpucap_panic_on_conflict(caps))
2272                         cpu_panic_kernel();
2273                 else
2274                         cpu_die_early();
2275         }
2276 }
2277
2278 /*
2279  * Check for CPU features that are used in early boot
2280  * based on the Boot CPU value.
2281  */
2282 static void check_early_cpu_features(void)
2283 {
2284         verify_cpu_asid_bits();
2285
2286         verify_local_cpu_caps(SCOPE_BOOT_CPU);
2287 }
2288
2289 static void
2290 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
2291 {
2292
2293         for (; caps->matches; caps++)
2294                 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
2295                         pr_crit("CPU%d: missing HWCAP: %s\n",
2296                                         smp_processor_id(), caps->desc);
2297                         cpu_die_early();
2298                 }
2299 }
2300
2301 static void verify_sve_features(void)
2302 {
2303         u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
2304         u64 zcr = read_zcr_features();
2305
2306         unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
2307         unsigned int len = zcr & ZCR_ELx_LEN_MASK;
2308
2309         if (len < safe_len || sve_verify_vq_map()) {
2310                 pr_crit("CPU%d: SVE: vector length support mismatch\n",
2311                         smp_processor_id());
2312                 cpu_die_early();
2313         }
2314
2315         /* Add checks on other ZCR bits here if necessary */
2316 }
2317
2318 static void verify_hyp_capabilities(void)
2319 {
2320         u64 safe_mmfr1, mmfr0, mmfr1;
2321         int parange, ipa_max;
2322         unsigned int safe_vmid_bits, vmid_bits;
2323
2324         if (!IS_ENABLED(CONFIG_KVM) || !IS_ENABLED(CONFIG_KVM_ARM_HOST))
2325                 return;
2326
2327         safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
2328         mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
2329         mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
2330
2331         /* Verify VMID bits */
2332         safe_vmid_bits = get_vmid_bits(safe_mmfr1);
2333         vmid_bits = get_vmid_bits(mmfr1);
2334         if (vmid_bits < safe_vmid_bits) {
2335                 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id());
2336                 cpu_die_early();
2337         }
2338
2339         /* Verify IPA range */
2340         parange = mmfr0 & 0x7;
2341         ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange);
2342         if (ipa_max < get_kvm_ipa_limit()) {
2343                 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id());
2344                 cpu_die_early();
2345         }
2346 }
2347
2348 /*
2349  * Run through the enabled system capabilities and enable() it on this CPU.
2350  * The capabilities were decided based on the available CPUs at the boot time.
2351  * Any new CPU should match the system wide status of the capability. If the
2352  * new CPU doesn't have a capability which the system now has enabled, we
2353  * cannot do anything to fix it up and could cause unexpected failures. So
2354  * we park the CPU.
2355  */
2356 static void verify_local_cpu_capabilities(void)
2357 {
2358         /*
2359          * The capabilities with SCOPE_BOOT_CPU are checked from
2360          * check_early_cpu_features(), as they need to be verified
2361          * on all secondary CPUs.
2362          */
2363         verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2364
2365         verify_local_elf_hwcaps(arm64_elf_hwcaps);
2366
2367         if (system_supports_32bit_el0())
2368                 verify_local_elf_hwcaps(compat_elf_hwcaps);
2369
2370         if (system_supports_sve())
2371                 verify_sve_features();
2372
2373         if (is_hyp_mode_available())
2374                 verify_hyp_capabilities();
2375 }
2376
2377 void check_local_cpu_capabilities(void)
2378 {
2379         /*
2380          * All secondary CPUs should conform to the early CPU features
2381          * in use by the kernel based on boot CPU.
2382          */
2383         check_early_cpu_features();
2384
2385         /*
2386          * If we haven't finalised the system capabilities, this CPU gets
2387          * a chance to update the errata work arounds and local features.
2388          * Otherwise, this CPU should verify that it has all the system
2389          * advertised capabilities.
2390          */
2391         if (!system_capabilities_finalized())
2392                 update_cpu_capabilities(SCOPE_LOCAL_CPU);
2393         else
2394                 verify_local_cpu_capabilities();
2395 }
2396
2397 static void __init setup_boot_cpu_capabilities(void)
2398 {
2399         /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
2400         update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
2401         /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
2402         enable_cpu_capabilities(SCOPE_BOOT_CPU);
2403 }
2404
2405 bool this_cpu_has_cap(unsigned int n)
2406 {
2407         if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
2408                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2409
2410                 if (cap)
2411                         return cap->matches(cap, SCOPE_LOCAL_CPU);
2412         }
2413
2414         return false;
2415 }
2416
2417 /*
2418  * This helper function is used in a narrow window when,
2419  * - The system wide safe registers are set with all the SMP CPUs and,
2420  * - The SYSTEM_FEATURE cpu_hwcaps may not have been set.
2421  * In all other cases cpus_have_{const_}cap() should be used.
2422  */
2423 static bool __system_matches_cap(unsigned int n)
2424 {
2425         if (n < ARM64_NCAPS) {
2426                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2427
2428                 if (cap)
2429                         return cap->matches(cap, SCOPE_SYSTEM);
2430         }
2431         return false;
2432 }
2433
2434 void cpu_set_feature(unsigned int num)
2435 {
2436         WARN_ON(num >= MAX_CPU_FEATURES);
2437         elf_hwcap |= BIT(num);
2438 }
2439 EXPORT_SYMBOL_GPL(cpu_set_feature);
2440
2441 bool cpu_have_feature(unsigned int num)
2442 {
2443         WARN_ON(num >= MAX_CPU_FEATURES);
2444         return elf_hwcap & BIT(num);
2445 }
2446 EXPORT_SYMBOL_GPL(cpu_have_feature);
2447
2448 unsigned long cpu_get_elf_hwcap(void)
2449 {
2450         /*
2451          * We currently only populate the first 32 bits of AT_HWCAP. Please
2452          * note that for userspace compatibility we guarantee that bits 62
2453          * and 63 will always be returned as 0.
2454          */
2455         return lower_32_bits(elf_hwcap);
2456 }
2457
2458 unsigned long cpu_get_elf_hwcap2(void)
2459 {
2460         return upper_32_bits(elf_hwcap);
2461 }
2462
2463 static void __init setup_system_capabilities(void)
2464 {
2465         /*
2466          * We have finalised the system-wide safe feature
2467          * registers, finalise the capabilities that depend
2468          * on it. Also enable all the available capabilities,
2469          * that are not enabled already.
2470          */
2471         update_cpu_capabilities(SCOPE_SYSTEM);
2472         enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2473 }
2474
2475 void __init setup_cpu_features(void)
2476 {
2477         u32 cwg;
2478
2479         setup_system_capabilities();
2480         setup_elf_hwcaps(arm64_elf_hwcaps);
2481
2482         if (system_supports_32bit_el0())
2483                 setup_elf_hwcaps(compat_elf_hwcaps);
2484
2485         if (system_uses_ttbr0_pan())
2486                 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
2487
2488         sve_setup();
2489         minsigstksz_setup();
2490
2491         /* Advertise that we have computed the system capabilities */
2492         finalize_system_capabilities();
2493
2494         /*
2495          * Check for sane CTR_EL0.CWG value.
2496          */
2497         cwg = cache_type_cwg();
2498         if (!cwg)
2499                 pr_warn("No Cache Writeback Granule information, assuming %d\n",
2500                         ARCH_DMA_MINALIGN);
2501 }
2502
2503 static bool __maybe_unused
2504 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
2505 {
2506         return (__system_matches_cap(ARM64_HAS_PAN) && !__system_matches_cap(ARM64_HAS_UAO));
2507 }
2508
2509 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
2510 {
2511         cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
2512 }
2513
2514 /*
2515  * We emulate only the following system register space.
2516  * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
2517  * See Table C5-6 System instruction encodings for System register accesses,
2518  * ARMv8 ARM(ARM DDI 0487A.f) for more details.
2519  */
2520 static inline bool __attribute_const__ is_emulated(u32 id)
2521 {
2522         return (sys_reg_Op0(id) == 0x3 &&
2523                 sys_reg_CRn(id) == 0x0 &&
2524                 sys_reg_Op1(id) == 0x0 &&
2525                 (sys_reg_CRm(id) == 0 ||
2526                  ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
2527 }
2528
2529 /*
2530  * With CRm == 0, reg should be one of :
2531  * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
2532  */
2533 static inline int emulate_id_reg(u32 id, u64 *valp)
2534 {
2535         switch (id) {
2536         case SYS_MIDR_EL1:
2537                 *valp = read_cpuid_id();
2538                 break;
2539         case SYS_MPIDR_EL1:
2540                 *valp = SYS_MPIDR_SAFE_VAL;
2541                 break;
2542         case SYS_REVIDR_EL1:
2543                 /* IMPLEMENTATION DEFINED values are emulated with 0 */
2544                 *valp = 0;
2545                 break;
2546         default:
2547                 return -EINVAL;
2548         }
2549
2550         return 0;
2551 }
2552
2553 static int emulate_sys_reg(u32 id, u64 *valp)
2554 {
2555         struct arm64_ftr_reg *regp;
2556
2557         if (!is_emulated(id))
2558                 return -EINVAL;
2559
2560         if (sys_reg_CRm(id) == 0)
2561                 return emulate_id_reg(id, valp);
2562
2563         regp = get_arm64_ftr_reg(id);
2564         if (regp)
2565                 *valp = arm64_ftr_reg_user_value(regp);
2566         else
2567                 /*
2568                  * The untracked registers are either IMPLEMENTATION DEFINED
2569                  * (e.g, ID_AFR0_EL1) or reserved RAZ.
2570                  */
2571                 *valp = 0;
2572         return 0;
2573 }
2574
2575 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
2576 {
2577         int rc;
2578         u64 val;
2579
2580         rc = emulate_sys_reg(sys_reg, &val);
2581         if (!rc) {
2582                 pt_regs_write_reg(regs, rt, val);
2583                 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
2584         }
2585         return rc;
2586 }
2587
2588 static int emulate_mrs(struct pt_regs *regs, u32 insn)
2589 {
2590         u32 sys_reg, rt;
2591
2592         /*
2593          * sys_reg values are defined as used in mrs/msr instruction.
2594          * shift the imm value to get the encoding.
2595          */
2596         sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
2597         rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
2598         return do_emulate_mrs(regs, sys_reg, rt);
2599 }
2600
2601 static struct undef_hook mrs_hook = {
2602         .instr_mask = 0xfff00000,
2603         .instr_val  = 0xd5300000,
2604         .pstate_mask = PSR_AA32_MODE_MASK,
2605         .pstate_val = PSR_MODE_EL0t,
2606         .fn = emulate_mrs,
2607 };
2608
2609 static int __init enable_mrs_emulation(void)
2610 {
2611         register_undef_hook(&mrs_hook);
2612         return 0;
2613 }
2614
2615 core_initcall(enable_mrs_emulation);
2616
2617 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
2618                           char *buf)
2619 {
2620         if (__meltdown_safe)
2621                 return sprintf(buf, "Not affected\n");
2622
2623         if (arm64_kernel_unmapped_at_el0())
2624                 return sprintf(buf, "Mitigation: PTI\n");
2625
2626         return sprintf(buf, "Vulnerable\n");
2627 }