arch/arm64/kernel/cpufeature.c

   1 /*
   2  * Contains CPU feature definitions
   3  *
   4  * Copyright (C) 2015 ARM Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #define pr_fmt(fmt) "CPU features: " fmt
  20
  21 #include <linux/bsearch.h>
  22 #include <linux/cpumask.h>
  23 #include <linux/sort.h>
  24 #include <linux/stop_machine.h>
  25 #include <linux/types.h>
  26 #include <linux/mm.h>
  27 #include <asm/cpu.h>
  28 #include <asm/cpufeature.h>
  29 #include <asm/cpu_ops.h>
  30 #include <asm/fpsimd.h>
  31 #include <asm/mmu_context.h>
  32 #include <asm/processor.h>
  33 #include <asm/sysreg.h>
  34 #include <asm/traps.h>
  35 #include <asm/virt.h>
  36
  37 unsigned long elf_hwcap __read_mostly;
  38 EXPORT_SYMBOL_GPL(elf_hwcap);
  39
  40 #ifdef CONFIG_COMPAT
  41 #define COMPAT_ELF_HWCAP_DEFAULT        \
  42                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  43                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  44                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
  45                                  COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
  46                                  COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
  47                                  COMPAT_HWCAP_LPAE)
  48 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  49 unsigned int compat_elf_hwcap2 __read_mostly;
  50 #endif
  51
  52 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  53 EXPORT_SYMBOL(cpu_hwcaps);
  54
  55 /*
  56  * Flag to indicate if we have computed the system wide
  57  * capabilities based on the boot time active CPUs. This
  58  * will be used to determine if a new booting CPU should
  59  * go through the verification process to make sure that it
  60  * supports the system capabilities, without using a hotplug
  61  * notifier.
  62  */
  63 static bool sys_caps_initialised;
  64
  65 static inline void set_sys_caps_initialised(void)
  66 {
  67         sys_caps_initialised = true;
  68 }
  69
  70 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
  71 {
  72         /* file-wide pr_fmt adds "CPU features: " prefix */
  73         pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
  74         return 0;
  75 }
  76
  77 static struct notifier_block cpu_hwcaps_notifier = {
  78         .notifier_call = dump_cpu_hwcaps
  79 };
  80
  81 static int __init register_cpu_hwcaps_dumper(void)
  82 {
  83         atomic_notifier_chain_register(&panic_notifier_list,
  84                                        &cpu_hwcaps_notifier);
  85         return 0;
  86 }
  87 __initcall(register_cpu_hwcaps_dumper);
  88
  89 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
  90 EXPORT_SYMBOL(cpu_hwcap_keys);
  91
  92 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  93         {                                               \
  94                 .sign = SIGNED,                         \
  95                 .visible = VISIBLE,                     \
  96                 .strict = STRICT,                       \
  97                 .type = TYPE,                           \
  98                 .shift = SHIFT,                         \
  99                 .width = WIDTH,                         \
 100                 .safe_val = SAFE_VAL,                   \
 101         }
 102
 103 /* Define a feature with unsigned values */
 104 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 105         __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 106
 107 /* Define a feature with a signed value */
 108 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 109         __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 110
 111 #define ARM64_FTR_END                                   \
 112         {                                               \
 113                 .width = 0,                             \
 114         }
 115
 116 /* meta feature for alternatives */
 117 static bool __maybe_unused
 118 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
 119
 120
 121 /*
 122  * NOTE: Any changes to the visibility of features should be kept in
 123  * sync with the documentation of the CPU feature register ABI.
 124  */
 125 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
 126         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
 127         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
 128         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
 129         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
 130         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
 131         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
 132         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
 133         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
 134         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
 135         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
 136         ARM64_FTR_END,
 137 };
 138
 139 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
 140         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
 141         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
 142         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
 143         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
 144         ARM64_FTR_END,
 145 };
 146
 147 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
 148         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
 149         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
 150         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
 151         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
 152         /* Linux doesn't care about the EL3 */
 153         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
 154         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
 155         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
 156         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
 157         ARM64_FTR_END,
 158 };
 159
 160 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 161         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 162         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 163         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 164         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 165         /* Linux shouldn't care about secure memory */
 166         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 167         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 168         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 169         /*
 170          * Differing PARange is fine as long as all peripherals and memory are mapped
 171          * within the minimum PARange of all CPUs
 172          */
 173         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 174         ARM64_FTR_END,
 175 };
 176
 177 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 178         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 179         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 180         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 181         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 182         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 183         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 184         ARM64_FTR_END,
 185 };
 186
 187 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 188         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
 189         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
 190         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
 191         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
 192         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
 193         ARM64_FTR_END,
 194 };
 195
 196 static const struct arm64_ftr_bits ftr_ctr[] = {
 197         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1),   /* RAO */
 198         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0),     /* CWG */
 199         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),      /* ERG */
 200         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1),      /* DminLine */
 201         /*
 202          * Linux can handle differing I-cache policies. Userspace JITs will
 203          * make use of *minLine.
 204          * If we have differing I-cache policies, report it as the weakest - VIPT.
 205          */
 206         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT),       /* L1Ip */
 207         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),       /* IminLine */
 208         ARM64_FTR_END,
 209 };
 210
 211 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
 212         .name           = "SYS_CTR_EL0",
 213         .ftr_bits       = ftr_ctr
 214 };
 215
 216 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
 217         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf),   /* InnerShr */
 218         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),       /* FCSE */
 219         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),    /* AuxReg */
 220         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),       /* TCM */
 221         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),       /* ShareLvl */
 222         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf),    /* OuterShr */
 223         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* PMSA */
 224         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),        /* VMSA */
 225         ARM64_FTR_END,
 226 };
 227
 228 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 229         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
 230         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
 231         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 232         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 233         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 234         /*
 235          * We can instantiate multiple PMU instances with different levels
 236          * of support.
 237          */
 238         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 239         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
 240         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 241         ARM64_FTR_END,
 242 };
 243
 244 static const struct arm64_ftr_bits ftr_mvfr2[] = {
 245         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* FPMisc */
 246         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* SIMDMisc */
 247         ARM64_FTR_END,
 248 };
 249
 250 static const struct arm64_ftr_bits ftr_dczid[] = {
 251         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1),            /* DZP */
 252         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),       /* BS */
 253         ARM64_FTR_END,
 254 };
 255
 256
 257 static const struct arm64_ftr_bits ftr_id_isar5[] = {
 258         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
 259         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
 260         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
 261         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
 262         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
 263         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
 264         ARM64_FTR_END,
 265 };
 266
 267 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
 268         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* ac2 */
 269         ARM64_FTR_END,
 270 };
 271
 272 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
 273         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),               /* State3 */
 274         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),                /* State2 */
 275         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* State1 */
 276         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* State0 */
 277         ARM64_FTR_END,
 278 };
 279
 280 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
 281         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 282         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf),   /* PerfMon */
 283         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 284         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 285         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 286         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 287         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 288         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 289         ARM64_FTR_END,
 290 };
 291
 292 static const struct arm64_ftr_bits ftr_zcr[] = {
 293         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
 294                 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0),        /* LEN */
 295         ARM64_FTR_END,
 296 };
 297
 298 /*
 299  * Common ftr bits for a 32bit register with all hidden, strict
 300  * attributes, with 4bit feature fields and a default safe value of
 301  * 0. Covers the following 32bit registers:
 302  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 303  */
 304 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
 305         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 306         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 307         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 308         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 309         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 310         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 311         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 312         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 313         ARM64_FTR_END,
 314 };
 315
 316 /* Table for a single 32bit feature value */
 317 static const struct arm64_ftr_bits ftr_single32[] = {
 318         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
 319         ARM64_FTR_END,
 320 };
 321
 322 static const struct arm64_ftr_bits ftr_raz[] = {
 323         ARM64_FTR_END,
 324 };
 325
 326 #define ARM64_FTR_REG(id, table) {              \
 327         .sys_id = id,                           \
 328         .reg =  &(struct arm64_ftr_reg){        \
 329                 .name = #id,                    \
 330                 .ftr_bits = &((table)[0]),      \
 331         }}
 332
 333 static const struct __ftr_reg_entry {
 334         u32                     sys_id;
 335         struct arm64_ftr_reg    *reg;
 336 } arm64_ftr_regs[] = {
 337
 338         /* Op1 = 0, CRn = 0, CRm = 1 */
 339         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 340         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
 341         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
 342         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 343         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 344         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 345         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 346
 347         /* Op1 = 0, CRn = 0, CRm = 2 */
 348         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 349         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 350         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 351         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 352         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
 353         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 354         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 355
 356         /* Op1 = 0, CRn = 0, CRm = 3 */
 357         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 358         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 359         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 360
 361         /* Op1 = 0, CRn = 0, CRm = 4 */
 362         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 363         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_raz),
 364         ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_raz),
 365
 366         /* Op1 = 0, CRn = 0, CRm = 5 */
 367         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 368         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
 369
 370         /* Op1 = 0, CRn = 0, CRm = 6 */
 371         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 372         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
 373
 374         /* Op1 = 0, CRn = 0, CRm = 7 */
 375         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 376         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 377         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
 378
 379         /* Op1 = 0, CRn = 1, CRm = 2 */
 380         ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
 381
 382         /* Op1 = 3, CRn = 0, CRm = 0 */
 383         { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
 384         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 385
 386         /* Op1 = 3, CRn = 14, CRm = 0 */
 387         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
 388 };
 389
 390 static int search_cmp_ftr_reg(const void *id, const void *regp)
 391 {
 392         return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
 393 }
 394
 395 /*
 396  * get_arm64_ftr_reg - Lookup a feature register entry using its
 397  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 398  * ascending order of sys_id , we use binary search to find a matching
 399  * entry.
 400  *
 401  * returns - Upon success,  matching ftr_reg entry for id.
 402  *         - NULL on failure. It is upto the caller to decide
 403  *           the impact of a failure.
 404  */
 405 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 406 {
 407         const struct __ftr_reg_entry *ret;
 408
 409         ret = bsearch((const void *)(unsigned long)sys_id,
 410                         arm64_ftr_regs,
 411                         ARRAY_SIZE(arm64_ftr_regs),
 412                         sizeof(arm64_ftr_regs[0]),
 413                         search_cmp_ftr_reg);
 414         if (ret)
 415                 return ret->reg;
 416         return NULL;
 417 }
 418
 419 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
 420                                s64 ftr_val)
 421 {
 422         u64 mask = arm64_ftr_mask(ftrp);
 423
 424         reg &= ~mask;
 425         reg |= (ftr_val << ftrp->shift) & mask;
 426         return reg;
 427 }
 428
 429 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
 430                                 s64 cur)
 431 {
 432         s64 ret = 0;
 433
 434         switch (ftrp->type) {
 435         case FTR_EXACT:
 436                 ret = ftrp->safe_val;
 437                 break;
 438         case FTR_LOWER_SAFE:
 439                 ret = new < cur ? new : cur;
 440                 break;
 441         case FTR_HIGHER_SAFE:
 442                 ret = new > cur ? new : cur;
 443                 break;
 444         default:
 445                 BUG();
 446         }
 447
 448         return ret;
 449 }
 450
 451 static void __init sort_ftr_regs(void)
 452 {
 453         int i;
 454
 455         /* Check that the array is sorted so that we can do the binary search */
 456         for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
 457                 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
 458 }
 459
 460 /*
 461  * Initialise the CPU feature register from Boot CPU values.
 462  * Also initiliases the strict_mask for the register.
 463  * Any bits that are not covered by an arm64_ftr_bits entry are considered
 464  * RES0 for the system-wide value, and must strictly match.
 465  */
 466 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 467 {
 468         u64 val = 0;
 469         u64 strict_mask = ~0x0ULL;
 470         u64 user_mask = 0;
 471         u64 valid_mask = 0;
 472
 473         const struct arm64_ftr_bits *ftrp;
 474         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 475
 476         BUG_ON(!reg);
 477
 478         for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
 479                 u64 ftr_mask = arm64_ftr_mask(ftrp);
 480                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 481
 482                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 483
 484                 valid_mask |= ftr_mask;
 485                 if (!ftrp->strict)
 486                         strict_mask &= ~ftr_mask;
 487                 if (ftrp->visible)
 488                         user_mask |= ftr_mask;
 489                 else
 490                         reg->user_val = arm64_ftr_set_value(ftrp,
 491                                                             reg->user_val,
 492                                                             ftrp->safe_val);
 493         }
 494
 495         val &= valid_mask;
 496
 497         reg->sys_val = val;
 498         reg->strict_mask = strict_mask;
 499         reg->user_mask = user_mask;
 500 }
 501
 502 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 503 {
 504         /* Before we start using the tables, make sure it is sorted */
 505         sort_ftr_regs();
 506
 507         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 508         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 509         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 510         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 511         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 512         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 513         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 514         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 515         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 516         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
 517         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 518         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 519         init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
 520
 521         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 522                 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 523                 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 524                 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 525                 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 526                 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 527                 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 528                 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 529                 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 530                 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 531                 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 532                 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 533                 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 534                 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 535                 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 536                 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 537                 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 538         }
 539
 540         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 541                 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
 542                 sve_init_vq_map();
 543         }
 544 }
 545
 546 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 547 {
 548         const struct arm64_ftr_bits *ftrp;
 549
 550         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 551                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 552                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 553
 554                 if (ftr_cur == ftr_new)
 555                         continue;
 556                 /* Find a safe value */
 557                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 558                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 559         }
 560
 561 }
 562
 563 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 564 {
 565         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 566
 567         BUG_ON(!regp);
 568         update_cpu_ftr_reg(regp, val);
 569         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 570                 return 0;
 571         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 572                         regp->name, boot, cpu, val);
 573         return 1;
 574 }
 575
 576 /*
 577  * Update system wide CPU feature registers with the values from a
 578  * non-boot CPU. Also performs SANITY checks to make sure that there
 579  * aren't any insane variations from that of the boot CPU.
 580  */
 581 void update_cpu_features(int cpu,
 582                          struct cpuinfo_arm64 *info,
 583                          struct cpuinfo_arm64 *boot)
 584 {
 585         int taint = 0;
 586
 587         /*
 588          * The kernel can handle differing I-cache policies, but otherwise
 589          * caches should look identical. Userspace JITs will make use of
 590          * *minLine.
 591          */
 592         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 593                                       info->reg_ctr, boot->reg_ctr);
 594
 595         /*
 596          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 597          * could result in too much or too little memory being zeroed if a
 598          * process is preempted and migrated between CPUs.
 599          */
 600         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 601                                       info->reg_dczid, boot->reg_dczid);
 602
 603         /* If different, timekeeping will be broken (especially with KVM) */
 604         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 605                                       info->reg_cntfrq, boot->reg_cntfrq);
 606
 607         /*
 608          * The kernel uses self-hosted debug features and expects CPUs to
 609          * support identical debug features. We presently need CTX_CMPs, WRPs,
 610          * and BRPs to be identical.
 611          * ID_AA64DFR1 is currently RES0.
 612          */
 613         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 614                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 615         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 616                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 617         /*
 618          * Even in big.LITTLE, processors should be identical instruction-set
 619          * wise.
 620          */
 621         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 622                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 623         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 624                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 625
 626         /*
 627          * Differing PARange support is fine as long as all peripherals and
 628          * memory are mapped within the minimum PARange of all CPUs.
 629          * Linux should not care about secure memory.
 630          */
 631         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 632                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 633         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 634                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 635         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
 636                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
 637
 638         /*
 639          * EL3 is not our concern.
 640          * ID_AA64PFR1 is currently RES0.
 641          */
 642         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 643                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 644         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 645                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 646
 647         taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
 648                                       info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
 649
 650         /*
 651          * If we have AArch32, we care about 32-bit features for compat.
 652          * If the system doesn't support AArch32, don't update them.
 653          */
 654         if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 655                 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 656
 657                 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 658                                         info->reg_id_dfr0, boot->reg_id_dfr0);
 659                 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 660                                         info->reg_id_isar0, boot->reg_id_isar0);
 661                 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 662                                         info->reg_id_isar1, boot->reg_id_isar1);
 663                 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 664                                         info->reg_id_isar2, boot->reg_id_isar2);
 665                 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 666                                         info->reg_id_isar3, boot->reg_id_isar3);
 667                 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 668                                         info->reg_id_isar4, boot->reg_id_isar4);
 669                 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 670                                         info->reg_id_isar5, boot->reg_id_isar5);
 671
 672                 /*
 673                  * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 674                  * ACTLR formats could differ across CPUs and therefore would have to
 675                  * be trapped for virtualization anyway.
 676                  */
 677                 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 678                                         info->reg_id_mmfr0, boot->reg_id_mmfr0);
 679                 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 680                                         info->reg_id_mmfr1, boot->reg_id_mmfr1);
 681                 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 682                                         info->reg_id_mmfr2, boot->reg_id_mmfr2);
 683                 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 684                                         info->reg_id_mmfr3, boot->reg_id_mmfr3);
 685                 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 686                                         info->reg_id_pfr0, boot->reg_id_pfr0);
 687                 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 688                                         info->reg_id_pfr1, boot->reg_id_pfr1);
 689                 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 690                                         info->reg_mvfr0, boot->reg_mvfr0);
 691                 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 692                                         info->reg_mvfr1, boot->reg_mvfr1);
 693                 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 694                                         info->reg_mvfr2, boot->reg_mvfr2);
 695         }
 696
 697         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 698                 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
 699                                         info->reg_zcr, boot->reg_zcr);
 700
 701                 /* Probe vector lengths, unless we already gave up on SVE */
 702                 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 703                     !sys_caps_initialised)
 704                         sve_update_vq_map();
 705         }
 706
 707         /*
 708          * Mismatched CPU features are a recipe for disaster. Don't even
 709          * pretend to support them.
 710          */
 711         if (taint) {
 712                 pr_warn_once("Unsupported CPU feature variation detected.\n");
 713                 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
 714         }
 715 }
 716
 717 u64 read_sanitised_ftr_reg(u32 id)
 718 {
 719         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 720
 721         /* We shouldn't get a request for an unsupported register */
 722         BUG_ON(!regp);
 723         return regp->sys_val;
 724 }
 725
 726 #define read_sysreg_case(r)     \
 727         case r:         return read_sysreg_s(r)
 728
 729 /*
 730  * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
 731  * Read the system register on the current CPU
 732  */
 733 static u64 __read_sysreg_by_encoding(u32 sys_id)
 734 {
 735         switch (sys_id) {
 736         read_sysreg_case(SYS_ID_PFR0_EL1);
 737         read_sysreg_case(SYS_ID_PFR1_EL1);
 738         read_sysreg_case(SYS_ID_DFR0_EL1);
 739         read_sysreg_case(SYS_ID_MMFR0_EL1);
 740         read_sysreg_case(SYS_ID_MMFR1_EL1);
 741         read_sysreg_case(SYS_ID_MMFR2_EL1);
 742         read_sysreg_case(SYS_ID_MMFR3_EL1);
 743         read_sysreg_case(SYS_ID_ISAR0_EL1);
 744         read_sysreg_case(SYS_ID_ISAR1_EL1);
 745         read_sysreg_case(SYS_ID_ISAR2_EL1);
 746         read_sysreg_case(SYS_ID_ISAR3_EL1);
 747         read_sysreg_case(SYS_ID_ISAR4_EL1);
 748         read_sysreg_case(SYS_ID_ISAR5_EL1);
 749         read_sysreg_case(SYS_MVFR0_EL1);
 750         read_sysreg_case(SYS_MVFR1_EL1);
 751         read_sysreg_case(SYS_MVFR2_EL1);
 752
 753         read_sysreg_case(SYS_ID_AA64PFR0_EL1);
 754         read_sysreg_case(SYS_ID_AA64PFR1_EL1);
 755         read_sysreg_case(SYS_ID_AA64DFR0_EL1);
 756         read_sysreg_case(SYS_ID_AA64DFR1_EL1);
 757         read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
 758         read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
 759         read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
 760         read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
 761         read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
 762
 763         read_sysreg_case(SYS_CNTFRQ_EL0);
 764         read_sysreg_case(SYS_CTR_EL0);
 765         read_sysreg_case(SYS_DCZID_EL0);
 766
 767         default:
 768                 BUG();
 769                 return 0;
 770         }
 771 }
 772
 773 #include <linux/irqchip/arm-gic-v3.h>
 774
 775 static bool
 776 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
 777 {
 778         int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
 779
 780         return val >= entry->min_field_value;
 781 }
 782
 783 static bool
 784 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
 785 {
 786         u64 val;
 787
 788         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
 789         if (scope == SCOPE_SYSTEM)
 790                 val = read_sanitised_ftr_reg(entry->sys_reg);
 791         else
 792                 val = __read_sysreg_by_encoding(entry->sys_reg);
 793
 794         return feature_matches(val, entry);
 795 }
 796
 797 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
 798 {
 799         bool has_sre;
 800
 801         if (!has_cpuid_feature(entry, scope))
 802                 return false;
 803
 804         has_sre = gic_enable_sre();
 805         if (!has_sre)
 806                 pr_warn_once("%s present but disabled by higher exception level\n",
 807                              entry->desc);
 808
 809         return has_sre;
 810 }
 811
 812 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
 813 {
 814         u32 midr = read_cpuid_id();
 815
 816         /* Cavium ThunderX pass 1.x and 2.x */
 817         return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX,
 818                 MIDR_CPU_VAR_REV(0, 0),
 819                 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
 820 }
 821
 822 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
 823 {
 824         return is_kernel_in_hyp_mode();
 825 }
 826
 827 static bool hyp_offset_low(const struct arm64_cpu_capabilities *entry,
 828                            int __unused)
 829 {
 830         phys_addr_t idmap_addr = __pa_symbol(__hyp_idmap_text_start);
 831
 832         /*
 833          * Activate the lower HYP offset only if:
 834          * - the idmap doesn't clash with it,
 835          * - the kernel is not running at EL2.
 836          */
 837         return idmap_addr > GENMASK(VA_BITS - 2, 0) && !is_kernel_in_hyp_mode();
 838 }
 839
 840 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
 841 {
 842         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
 843
 844         return cpuid_feature_extract_signed_field(pfr0,
 845                                         ID_AA64PFR0_FP_SHIFT) < 0;
 846 }
 847
 848 static const struct arm64_cpu_capabilities arm64_features[] = {
 849         {
 850                 .desc = "GIC system register CPU interface",
 851                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
 852                 .def_scope = SCOPE_SYSTEM,
 853                 .matches = has_useable_gicv3_cpuif,
 854                 .sys_reg = SYS_ID_AA64PFR0_EL1,
 855                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
 856                 .sign = FTR_UNSIGNED,
 857                 .min_field_value = 1,
 858         },
 859 #ifdef CONFIG_ARM64_PAN
 860         {
 861                 .desc = "Privileged Access Never",
 862                 .capability = ARM64_HAS_PAN,
 863                 .def_scope = SCOPE_SYSTEM,
 864                 .matches = has_cpuid_feature,
 865                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
 866                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
 867                 .sign = FTR_UNSIGNED,
 868                 .min_field_value = 1,
 869                 .enable = cpu_enable_pan,
 870         },
 871 #endif /* CONFIG_ARM64_PAN */
 872 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
 873         {
 874                 .desc = "LSE atomic instructions",
 875                 .capability = ARM64_HAS_LSE_ATOMICS,
 876                 .def_scope = SCOPE_SYSTEM,
 877                 .matches = has_cpuid_feature,
 878                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
 879                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
 880                 .sign = FTR_UNSIGNED,
 881                 .min_field_value = 2,
 882         },
 883 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
 884         {
 885                 .desc = "Software prefetching using PRFM",
 886                 .capability = ARM64_HAS_NO_HW_PREFETCH,
 887                 .def_scope = SCOPE_SYSTEM,
 888                 .matches = has_no_hw_prefetch,
 889         },
 890 #ifdef CONFIG_ARM64_UAO
 891         {
 892                 .desc = "User Access Override",
 893                 .capability = ARM64_HAS_UAO,
 894                 .def_scope = SCOPE_SYSTEM,
 895                 .matches = has_cpuid_feature,
 896                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
 897                 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
 898                 .min_field_value = 1,
 899                 /*
 900                  * We rely on stop_machine() calling uao_thread_switch() to set
 901                  * UAO immediately after patching.
 902                  */
 903         },
 904 #endif /* CONFIG_ARM64_UAO */
 905 #ifdef CONFIG_ARM64_PAN
 906         {
 907                 .capability = ARM64_ALT_PAN_NOT_UAO,
 908                 .def_scope = SCOPE_SYSTEM,
 909                 .matches = cpufeature_pan_not_uao,
 910         },
 911 #endif /* CONFIG_ARM64_PAN */
 912         {
 913                 .desc = "Virtualization Host Extensions",
 914                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
 915                 .def_scope = SCOPE_SYSTEM,
 916                 .matches = runs_at_el2,
 917         },
 918         {
 919                 .desc = "32-bit EL0 Support",
 920                 .capability = ARM64_HAS_32BIT_EL0,
 921                 .def_scope = SCOPE_SYSTEM,
 922                 .matches = has_cpuid_feature,
 923                 .sys_reg = SYS_ID_AA64PFR0_EL1,
 924                 .sign = FTR_UNSIGNED,
 925                 .field_pos = ID_AA64PFR0_EL0_SHIFT,
 926                 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
 927         },
 928         {
 929                 .desc = "Reduced HYP mapping offset",
 930                 .capability = ARM64_HYP_OFFSET_LOW,
 931                 .def_scope = SCOPE_SYSTEM,
 932                 .matches = hyp_offset_low,
 933         },
 934         {
 935                 /* FP/SIMD is not implemented */
 936                 .capability = ARM64_HAS_NO_FPSIMD,
 937                 .def_scope = SCOPE_SYSTEM,
 938                 .min_field_value = 0,
 939                 .matches = has_no_fpsimd,
 940         },
 941 #ifdef CONFIG_ARM64_PMEM
 942         {
 943                 .desc = "Data cache clean to Point of Persistence",
 944                 .capability = ARM64_HAS_DCPOP,
 945                 .def_scope = SCOPE_SYSTEM,
 946                 .matches = has_cpuid_feature,
 947                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
 948                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
 949                 .min_field_value = 1,
 950         },
 951 #endif
 952 #ifdef CONFIG_ARM64_SVE
 953         {
 954                 .desc = "Scalable Vector Extension",
 955                 .capability = ARM64_SVE,
 956                 .def_scope = SCOPE_SYSTEM,
 957                 .sys_reg = SYS_ID_AA64PFR0_EL1,
 958                 .sign = FTR_UNSIGNED,
 959                 .field_pos = ID_AA64PFR0_SVE_SHIFT,
 960                 .min_field_value = ID_AA64PFR0_SVE,
 961                 .matches = has_cpuid_feature,
 962                 .enable = sve_kernel_enable,
 963         },
 964 #endif /* CONFIG_ARM64_SVE */
 965         {},
 966 };
 967
 968 #define HWCAP_CAP(reg, field, s, min_value, type, cap)  \
 969         {                                                       \
 970                 .desc = #cap,                                   \
 971                 .def_scope = SCOPE_SYSTEM,                      \
 972                 .matches = has_cpuid_feature,                   \
 973                 .sys_reg = reg,                                 \
 974                 .field_pos = field,                             \
 975                 .sign = s,                                      \
 976                 .min_field_value = min_value,                   \
 977                 .hwcap_type = type,                             \
 978                 .hwcap = cap,                                   \
 979         }
 980
 981 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
 982         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
 983         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
 984         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
 985         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
 986         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_SHA512),
 987         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
 988         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
 989         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM),
 990         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA3),
 991         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM3),
 992         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM4),
 993         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDDP),
 994         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
 995         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
 996         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
 997         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
 998         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP),
 999         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),
1000         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),
1001         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC),
1002 #ifdef CONFIG_ARM64_SVE
1003         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE),
1004 #endif
1005         {},
1006 };
1007
1008 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
1009 #ifdef CONFIG_COMPAT
1010         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1011         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1012         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1013         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1014         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
1015 #endif
1016         {},
1017 };
1018
1019 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1020 {
1021         switch (cap->hwcap_type) {
1022         case CAP_HWCAP:
1023                 elf_hwcap |= cap->hwcap;
1024                 break;
1025 #ifdef CONFIG_COMPAT
1026         case CAP_COMPAT_HWCAP:
1027                 compat_elf_hwcap |= (u32)cap->hwcap;
1028                 break;
1029         case CAP_COMPAT_HWCAP2:
1030                 compat_elf_hwcap2 |= (u32)cap->hwcap;
1031                 break;
1032 #endif
1033         default:
1034                 WARN_ON(1);
1035                 break;
1036         }
1037 }
1038
1039 /* Check if we have a particular HWCAP enabled */
1040 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1041 {
1042         bool rc;
1043
1044         switch (cap->hwcap_type) {
1045         case CAP_HWCAP:
1046                 rc = (elf_hwcap & cap->hwcap) != 0;
1047                 break;
1048 #ifdef CONFIG_COMPAT
1049         case CAP_COMPAT_HWCAP:
1050                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1051                 break;
1052         case CAP_COMPAT_HWCAP2:
1053                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1054                 break;
1055 #endif
1056         default:
1057                 WARN_ON(1);
1058                 rc = false;
1059         }
1060
1061         return rc;
1062 }
1063
1064 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
1065 {
1066         /* We support emulation of accesses to CPU ID feature registers */
1067         elf_hwcap |= HWCAP_CPUID;
1068         for (; hwcaps->matches; hwcaps++)
1069                 if (hwcaps->matches(hwcaps, hwcaps->def_scope))
1070                         cap_set_elf_hwcap(hwcaps);
1071 }
1072
1073 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
1074                             const char *info)
1075 {
1076         for (; caps->matches; caps++) {
1077                 if (!caps->matches(caps, caps->def_scope))
1078                         continue;
1079
1080                 if (!cpus_have_cap(caps->capability) && caps->desc)
1081                         pr_info("%s %s\n", info, caps->desc);
1082                 cpus_set_cap(caps->capability);
1083         }
1084 }
1085
1086 /*
1087  * Run through the enabled capabilities and enable() it on all active
1088  * CPUs
1089  */
1090 void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
1091 {
1092         for (; caps->matches; caps++) {
1093                 unsigned int num = caps->capability;
1094
1095                 if (!cpus_have_cap(num))
1096                         continue;
1097
1098                 /* Ensure cpus_have_const_cap(num) works */
1099                 static_branch_enable(&cpu_hwcap_keys[num]);
1100
1101                 if (caps->enable) {
1102                         /*
1103                          * Use stop_machine() as it schedules the work allowing
1104                          * us to modify PSTATE, instead of on_each_cpu() which
1105                          * uses an IPI, giving us a PSTATE that disappears when
1106                          * we return.
1107                          */
1108                         stop_machine(caps->enable, NULL, cpu_online_mask);
1109                 }
1110         }
1111 }
1112
1113 /*
1114  * Check for CPU features that are used in early boot
1115  * based on the Boot CPU value.
1116  */
1117 static void check_early_cpu_features(void)
1118 {
1119         verify_cpu_run_el();
1120         verify_cpu_asid_bits();
1121 }
1122
1123 static void
1124 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1125 {
1126
1127         for (; caps->matches; caps++)
1128                 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
1129                         pr_crit("CPU%d: missing HWCAP: %s\n",
1130                                         smp_processor_id(), caps->desc);
1131                         cpu_die_early();
1132                 }
1133 }
1134
1135 static void
1136 verify_local_cpu_features(const struct arm64_cpu_capabilities *caps)
1137 {
1138         for (; caps->matches; caps++) {
1139                 if (!cpus_have_cap(caps->capability))
1140                         continue;
1141                 /*
1142                  * If the new CPU misses an advertised feature, we cannot proceed
1143                  * further, park the cpu.
1144                  */
1145                 if (!caps->matches(caps, SCOPE_LOCAL_CPU)) {
1146                         pr_crit("CPU%d: missing feature: %s\n",
1147                                         smp_processor_id(), caps->desc);
1148                         cpu_die_early();
1149                 }
1150                 if (caps->enable)
1151                         caps->enable(NULL);
1152         }
1153 }
1154
1155 static void verify_sve_features(void)
1156 {
1157         u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
1158         u64 zcr = read_zcr_features();
1159
1160         unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
1161         unsigned int len = zcr & ZCR_ELx_LEN_MASK;
1162
1163         if (len < safe_len || sve_verify_vq_map()) {
1164                 pr_crit("CPU%d: SVE: required vector length(s) missing\n",
1165                         smp_processor_id());
1166                 cpu_die_early();
1167         }
1168
1169         /* Add checks on other ZCR bits here if necessary */
1170 }
1171
1172 /*
1173  * Run through the enabled system capabilities and enable() it on this CPU.
1174  * The capabilities were decided based on the available CPUs at the boot time.
1175  * Any new CPU should match the system wide status of the capability. If the
1176  * new CPU doesn't have a capability which the system now has enabled, we
1177  * cannot do anything to fix it up and could cause unexpected failures. So
1178  * we park the CPU.
1179  */
1180 static void verify_local_cpu_capabilities(void)
1181 {
1182         verify_local_cpu_errata_workarounds();
1183         verify_local_cpu_features(arm64_features);
1184         verify_local_elf_hwcaps(arm64_elf_hwcaps);
1185
1186         if (system_supports_32bit_el0())
1187                 verify_local_elf_hwcaps(compat_elf_hwcaps);
1188
1189         if (system_supports_sve())
1190                 verify_sve_features();
1191 }
1192
1193 void check_local_cpu_capabilities(void)
1194 {
1195         /*
1196          * All secondary CPUs should conform to the early CPU features
1197          * in use by the kernel based on boot CPU.
1198          */
1199         check_early_cpu_features();
1200
1201         /*
1202          * If we haven't finalised the system capabilities, this CPU gets
1203          * a chance to update the errata work arounds.
1204          * Otherwise, this CPU should verify that it has all the system
1205          * advertised capabilities.
1206          */
1207         if (!sys_caps_initialised)
1208                 update_cpu_errata_workarounds();
1209         else
1210                 verify_local_cpu_capabilities();
1211 }
1212
1213 static void __init setup_feature_capabilities(void)
1214 {
1215         update_cpu_capabilities(arm64_features, "detected feature:");
1216         enable_cpu_capabilities(arm64_features);
1217 }
1218
1219 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
1220 EXPORT_SYMBOL(arm64_const_caps_ready);
1221
1222 static void __init mark_const_caps_ready(void)
1223 {
1224         static_branch_enable(&arm64_const_caps_ready);
1225 }
1226
1227 /*
1228  * Check if the current CPU has a given feature capability.
1229  * Should be called from non-preemptible context.
1230  */
1231 static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities *cap_array,
1232                                unsigned int cap)
1233 {
1234         const struct arm64_cpu_capabilities *caps;
1235
1236         if (WARN_ON(preemptible()))
1237                 return false;
1238
1239         for (caps = cap_array; caps->desc; caps++)
1240                 if (caps->capability == cap && caps->matches)
1241                         return caps->matches(caps, SCOPE_LOCAL_CPU);
1242
1243         return false;
1244 }
1245
1246 extern const struct arm64_cpu_capabilities arm64_errata[];
1247
1248 bool this_cpu_has_cap(unsigned int cap)
1249 {
1250         return (__this_cpu_has_cap(arm64_features, cap) ||
1251                 __this_cpu_has_cap(arm64_errata, cap));
1252 }
1253
1254 void __init setup_cpu_features(void)
1255 {
1256         u32 cwg;
1257         int cls;
1258
1259         /* Set the CPU feature capabilies */
1260         setup_feature_capabilities();
1261         enable_errata_workarounds();
1262         mark_const_caps_ready();
1263         setup_elf_hwcaps(arm64_elf_hwcaps);
1264
1265         if (system_supports_32bit_el0())
1266                 setup_elf_hwcaps(compat_elf_hwcaps);
1267
1268         sve_setup();
1269
1270         /* Advertise that we have computed the system capabilities */
1271         set_sys_caps_initialised();
1272
1273         /*
1274          * Check for sane CTR_EL0.CWG value.
1275          */
1276         cwg = cache_type_cwg();
1277         cls = cache_line_size();
1278         if (!cwg)
1279                 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
1280                         cls);
1281         if (L1_CACHE_BYTES < cls)
1282                 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
1283                         L1_CACHE_BYTES, cls);
1284 }
1285
1286 static bool __maybe_unused
1287 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
1288 {
1289         return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
1290 }
1291
1292 /*
1293  * We emulate only the following system register space.
1294  * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
1295  * See Table C5-6 System instruction encodings for System register accesses,
1296  * ARMv8 ARM(ARM DDI 0487A.f) for more details.
1297  */
1298 static inline bool __attribute_const__ is_emulated(u32 id)
1299 {
1300         return (sys_reg_Op0(id) == 0x3 &&
1301                 sys_reg_CRn(id) == 0x0 &&
1302                 sys_reg_Op1(id) == 0x0 &&
1303                 (sys_reg_CRm(id) == 0 ||
1304                  ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
1305 }
1306
1307 /*
1308  * With CRm == 0, reg should be one of :
1309  * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
1310  */
1311 static inline int emulate_id_reg(u32 id, u64 *valp)
1312 {
1313         switch (id) {
1314         case SYS_MIDR_EL1:
1315                 *valp = read_cpuid_id();
1316                 break;
1317         case SYS_MPIDR_EL1:
1318                 *valp = SYS_MPIDR_SAFE_VAL;
1319                 break;
1320         case SYS_REVIDR_EL1:
1321                 /* IMPLEMENTATION DEFINED values are emulated with 0 */
1322                 *valp = 0;
1323                 break;
1324         default:
1325                 return -EINVAL;
1326         }
1327
1328         return 0;
1329 }
1330
1331 static int emulate_sys_reg(u32 id, u64 *valp)
1332 {
1333         struct arm64_ftr_reg *regp;
1334
1335         if (!is_emulated(id))
1336                 return -EINVAL;
1337
1338         if (sys_reg_CRm(id) == 0)
1339                 return emulate_id_reg(id, valp);
1340
1341         regp = get_arm64_ftr_reg(id);
1342         if (regp)
1343                 *valp = arm64_ftr_reg_user_value(regp);
1344         else
1345                 /*
1346                  * The untracked registers are either IMPLEMENTATION DEFINED
1347                  * (e.g, ID_AFR0_EL1) or reserved RAZ.
1348                  */
1349                 *valp = 0;
1350         return 0;
1351 }
1352
1353 static int emulate_mrs(struct pt_regs *regs, u32 insn)
1354 {
1355         int rc;
1356         u32 sys_reg, dst;
1357         u64 val;
1358
1359         /*
1360          * sys_reg values are defined as used in mrs/msr instruction.
1361          * shift the imm value to get the encoding.
1362          */
1363         sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
1364         rc = emulate_sys_reg(sys_reg, &val);
1365         if (!rc) {
1366                 dst = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
1367                 pt_regs_write_reg(regs, dst, val);
1368                 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
1369         }
1370
1371         return rc;
1372 }
1373
1374 static struct undef_hook mrs_hook = {
1375         .instr_mask = 0xfff00000,
1376         .instr_val  = 0xd5300000,
1377         .pstate_mask = COMPAT_PSR_MODE_MASK,
1378         .pstate_val = PSR_MODE_EL0t,
1379         .fn = emulate_mrs,
1380 };
1381
1382 static int __init enable_mrs_emulation(void)
1383 {
1384         register_undef_hook(&mrs_hook);
1385         return 0;
1386 }
1387
1388 late_initcall(enable_mrs_emulation);