arch/arm64/kernel/cpufeature.c

   1 /*
   2  * Contains CPU feature definitions
   3  *
   4  * Copyright (C) 2015 ARM Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #define pr_fmt(fmt) "CPU features: " fmt
  20
  21 #include <linux/bsearch.h>
  22 #include <linux/cpumask.h>
  23 #include <linux/crash_dump.h>
  24 #include <linux/sort.h>
  25 #include <linux/stop_machine.h>
  26 #include <linux/types.h>
  27 #include <linux/mm.h>
  28 #include <asm/cpu.h>
  29 #include <asm/cpufeature.h>
  30 #include <asm/cpu_ops.h>
  31 #include <asm/fpsimd.h>
  32 #include <asm/mmu_context.h>
  33 #include <asm/processor.h>
  34 #include <asm/sysreg.h>
  35 #include <asm/traps.h>
  36 #include <asm/virt.h>
  37
  38 unsigned long elf_hwcap __read_mostly;
  39 EXPORT_SYMBOL_GPL(elf_hwcap);
  40
  41 #ifdef CONFIG_COMPAT
  42 #define COMPAT_ELF_HWCAP_DEFAULT        \
  43                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  44                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  45                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
  46                                  COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
  47                                  COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
  48                                  COMPAT_HWCAP_LPAE)
  49 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  50 unsigned int compat_elf_hwcap2 __read_mostly;
  51 #endif
  52
  53 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  54 EXPORT_SYMBOL(cpu_hwcaps);
  55 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
  56
  57 /*
  58  * Flag to indicate if we have computed the system wide
  59  * capabilities based on the boot time active CPUs. This
  60  * will be used to determine if a new booting CPU should
  61  * go through the verification process to make sure that it
  62  * supports the system capabilities, without using a hotplug
  63  * notifier.
  64  */
  65 static bool sys_caps_initialised;
  66
  67 static inline void set_sys_caps_initialised(void)
  68 {
  69         sys_caps_initialised = true;
  70 }
  71
  72 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
  73 {
  74         /* file-wide pr_fmt adds "CPU features: " prefix */
  75         pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
  76         return 0;
  77 }
  78
  79 static struct notifier_block cpu_hwcaps_notifier = {
  80         .notifier_call = dump_cpu_hwcaps
  81 };
  82
  83 static int __init register_cpu_hwcaps_dumper(void)
  84 {
  85         atomic_notifier_chain_register(&panic_notifier_list,
  86                                        &cpu_hwcaps_notifier);
  87         return 0;
  88 }
  89 __initcall(register_cpu_hwcaps_dumper);
  90
  91 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
  92 EXPORT_SYMBOL(cpu_hwcap_keys);
  93
  94 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  95         {                                               \
  96                 .sign = SIGNED,                         \
  97                 .visible = VISIBLE,                     \
  98                 .strict = STRICT,                       \
  99                 .type = TYPE,                           \
 100                 .shift = SHIFT,                         \
 101                 .width = WIDTH,                         \
 102                 .safe_val = SAFE_VAL,                   \
 103         }
 104
 105 /* Define a feature with unsigned values */
 106 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 107         __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 108
 109 /* Define a feature with a signed value */
 110 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 111         __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 112
 113 #define ARM64_FTR_END                                   \
 114         {                                               \
 115                 .width = 0,                             \
 116         }
 117
 118 /* meta feature for alternatives */
 119 static bool __maybe_unused
 120 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
 121
 122 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
 123
 124 /*
 125  * NOTE: Any changes to the visibility of features should be kept in
 126  * sync with the documentation of the CPU feature register ABI.
 127  */
 128 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
 129         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
 130         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
 131         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
 132         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
 133         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
 134         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
 135         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
 136         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
 137         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
 138         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
 139         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
 140         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
 141         ARM64_FTR_END,
 142 };
 143
 144 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
 145         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
 146         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
 147         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
 148         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
 149         ARM64_FTR_END,
 150 };
 151
 152 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
 153         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
 154         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
 155         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
 156         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 157                                    FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
 158         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
 159         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
 160         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
 161         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
 162         /* Linux doesn't care about the EL3 */
 163         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
 164         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
 165         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
 166         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
 167         ARM64_FTR_END,
 168 };
 169
 170 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
 171         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
 172         ARM64_FTR_END,
 173 };
 174
 175 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 176         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 177         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 178         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 179         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 180         /* Linux shouldn't care about secure memory */
 181         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 182         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 183         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 184         /*
 185          * Differing PARange is fine as long as all peripherals and memory are mapped
 186          * within the minimum PARange of all CPUs
 187          */
 188         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 189         ARM64_FTR_END,
 190 };
 191
 192 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 193         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 194         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 195         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 196         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 197         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 198         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 199         ARM64_FTR_END,
 200 };
 201
 202 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 203         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
 204         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
 205         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
 206         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
 207         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
 208         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
 209         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
 210         ARM64_FTR_END,
 211 };
 212
 213 static const struct arm64_ftr_bits ftr_ctr[] = {
 214         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
 215         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
 216         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
 217         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_CWG_SHIFT, 4, 0),
 218         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_ERG_SHIFT, 4, 0),
 219         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
 220         /*
 221          * Linux can handle differing I-cache policies. Userspace JITs will
 222          * make use of *minLine.
 223          * If we have differing I-cache policies, report it as the weakest - VIPT.
 224          */
 225         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT),       /* L1Ip */
 226         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
 227         ARM64_FTR_END,
 228 };
 229
 230 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
 231         .name           = "SYS_CTR_EL0",
 232         .ftr_bits       = ftr_ctr
 233 };
 234
 235 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
 236         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf),   /* InnerShr */
 237         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),       /* FCSE */
 238         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),    /* AuxReg */
 239         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),       /* TCM */
 240         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),       /* ShareLvl */
 241         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf),    /* OuterShr */
 242         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* PMSA */
 243         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),        /* VMSA */
 244         ARM64_FTR_END,
 245 };
 246
 247 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 248         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
 249         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
 250         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 251         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 252         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 253         /*
 254          * We can instantiate multiple PMU instances with different levels
 255          * of support.
 256          */
 257         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 258         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
 259         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 260         ARM64_FTR_END,
 261 };
 262
 263 static const struct arm64_ftr_bits ftr_mvfr2[] = {
 264         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* FPMisc */
 265         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* SIMDMisc */
 266         ARM64_FTR_END,
 267 };
 268
 269 static const struct arm64_ftr_bits ftr_dczid[] = {
 270         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1),            /* DZP */
 271         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),       /* BS */
 272         ARM64_FTR_END,
 273 };
 274
 275
 276 static const struct arm64_ftr_bits ftr_id_isar5[] = {
 277         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
 278         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
 279         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
 280         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
 281         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
 282         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
 283         ARM64_FTR_END,
 284 };
 285
 286 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
 287         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* ac2 */
 288         ARM64_FTR_END,
 289 };
 290
 291 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
 292         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),               /* State3 */
 293         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),                /* State2 */
 294         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* State1 */
 295         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* State0 */
 296         ARM64_FTR_END,
 297 };
 298
 299 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
 300         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 301         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf),   /* PerfMon */
 302         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 303         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 304         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 305         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 306         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 307         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 308         ARM64_FTR_END,
 309 };
 310
 311 static const struct arm64_ftr_bits ftr_zcr[] = {
 312         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
 313                 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0),        /* LEN */
 314         ARM64_FTR_END,
 315 };
 316
 317 /*
 318  * Common ftr bits for a 32bit register with all hidden, strict
 319  * attributes, with 4bit feature fields and a default safe value of
 320  * 0. Covers the following 32bit registers:
 321  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 322  */
 323 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
 324         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 325         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 326         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 327         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 328         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 329         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 330         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 331         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 332         ARM64_FTR_END,
 333 };
 334
 335 /* Table for a single 32bit feature value */
 336 static const struct arm64_ftr_bits ftr_single32[] = {
 337         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
 338         ARM64_FTR_END,
 339 };
 340
 341 static const struct arm64_ftr_bits ftr_raz[] = {
 342         ARM64_FTR_END,
 343 };
 344
 345 #define ARM64_FTR_REG(id, table) {              \
 346         .sys_id = id,                           \
 347         .reg =  &(struct arm64_ftr_reg){        \
 348                 .name = #id,                    \
 349                 .ftr_bits = &((table)[0]),      \
 350         }}
 351
 352 static const struct __ftr_reg_entry {
 353         u32                     sys_id;
 354         struct arm64_ftr_reg    *reg;
 355 } arm64_ftr_regs[] = {
 356
 357         /* Op1 = 0, CRn = 0, CRm = 1 */
 358         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 359         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
 360         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
 361         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 362         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 363         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 364         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 365
 366         /* Op1 = 0, CRn = 0, CRm = 2 */
 367         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 368         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 369         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 370         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 371         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
 372         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 373         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 374
 375         /* Op1 = 0, CRn = 0, CRm = 3 */
 376         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 377         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 378         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 379
 380         /* Op1 = 0, CRn = 0, CRm = 4 */
 381         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 382         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
 383         ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_raz),
 384
 385         /* Op1 = 0, CRn = 0, CRm = 5 */
 386         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 387         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
 388
 389         /* Op1 = 0, CRn = 0, CRm = 6 */
 390         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 391         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
 392
 393         /* Op1 = 0, CRn = 0, CRm = 7 */
 394         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 395         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 396         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
 397
 398         /* Op1 = 0, CRn = 1, CRm = 2 */
 399         ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
 400
 401         /* Op1 = 3, CRn = 0, CRm = 0 */
 402         { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
 403         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 404
 405         /* Op1 = 3, CRn = 14, CRm = 0 */
 406         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
 407 };
 408
 409 static int search_cmp_ftr_reg(const void *id, const void *regp)
 410 {
 411         return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
 412 }
 413
 414 /*
 415  * get_arm64_ftr_reg - Lookup a feature register entry using its
 416  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 417  * ascending order of sys_id , we use binary search to find a matching
 418  * entry.
 419  *
 420  * returns - Upon success,  matching ftr_reg entry for id.
 421  *         - NULL on failure. It is upto the caller to decide
 422  *           the impact of a failure.
 423  */
 424 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 425 {
 426         const struct __ftr_reg_entry *ret;
 427
 428         ret = bsearch((const void *)(unsigned long)sys_id,
 429                         arm64_ftr_regs,
 430                         ARRAY_SIZE(arm64_ftr_regs),
 431                         sizeof(arm64_ftr_regs[0]),
 432                         search_cmp_ftr_reg);
 433         if (ret)
 434                 return ret->reg;
 435         return NULL;
 436 }
 437
 438 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
 439                                s64 ftr_val)
 440 {
 441         u64 mask = arm64_ftr_mask(ftrp);
 442
 443         reg &= ~mask;
 444         reg |= (ftr_val << ftrp->shift) & mask;
 445         return reg;
 446 }
 447
 448 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
 449                                 s64 cur)
 450 {
 451         s64 ret = 0;
 452
 453         switch (ftrp->type) {
 454         case FTR_EXACT:
 455                 ret = ftrp->safe_val;
 456                 break;
 457         case FTR_LOWER_SAFE:
 458                 ret = new < cur ? new : cur;
 459                 break;
 460         case FTR_HIGHER_SAFE:
 461                 ret = new > cur ? new : cur;
 462                 break;
 463         default:
 464                 BUG();
 465         }
 466
 467         return ret;
 468 }
 469
 470 static void __init sort_ftr_regs(void)
 471 {
 472         int i;
 473
 474         /* Check that the array is sorted so that we can do the binary search */
 475         for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
 476                 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
 477 }
 478
 479 /*
 480  * Initialise the CPU feature register from Boot CPU values.
 481  * Also initiliases the strict_mask for the register.
 482  * Any bits that are not covered by an arm64_ftr_bits entry are considered
 483  * RES0 for the system-wide value, and must strictly match.
 484  */
 485 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 486 {
 487         u64 val = 0;
 488         u64 strict_mask = ~0x0ULL;
 489         u64 user_mask = 0;
 490         u64 valid_mask = 0;
 491
 492         const struct arm64_ftr_bits *ftrp;
 493         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 494
 495         BUG_ON(!reg);
 496
 497         for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
 498                 u64 ftr_mask = arm64_ftr_mask(ftrp);
 499                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 500
 501                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 502
 503                 valid_mask |= ftr_mask;
 504                 if (!ftrp->strict)
 505                         strict_mask &= ~ftr_mask;
 506                 if (ftrp->visible)
 507                         user_mask |= ftr_mask;
 508                 else
 509                         reg->user_val = arm64_ftr_set_value(ftrp,
 510                                                             reg->user_val,
 511                                                             ftrp->safe_val);
 512         }
 513
 514         val &= valid_mask;
 515
 516         reg->sys_val = val;
 517         reg->strict_mask = strict_mask;
 518         reg->user_mask = user_mask;
 519 }
 520
 521 extern const struct arm64_cpu_capabilities arm64_errata[];
 522 static const struct arm64_cpu_capabilities arm64_features[];
 523
 524 static void __init
 525 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
 526 {
 527         for (; caps->matches; caps++) {
 528                 if (WARN(caps->capability >= ARM64_NCAPS,
 529                         "Invalid capability %d\n", caps->capability))
 530                         continue;
 531                 if (WARN(cpu_hwcaps_ptrs[caps->capability],
 532                         "Duplicate entry for capability %d\n",
 533                         caps->capability))
 534                         continue;
 535                 cpu_hwcaps_ptrs[caps->capability] = caps;
 536         }
 537 }
 538
 539 static void __init init_cpu_hwcaps_indirect_list(void)
 540 {
 541         init_cpu_hwcaps_indirect_list_from_array(arm64_features);
 542         init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
 543 }
 544
 545 static void __init setup_boot_cpu_capabilities(void);
 546
 547 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 548 {
 549         /* Before we start using the tables, make sure it is sorted */
 550         sort_ftr_regs();
 551
 552         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 553         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 554         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 555         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 556         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 557         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 558         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 559         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 560         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 561         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
 562         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 563         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 564         init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
 565
 566         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 567                 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 568                 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 569                 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 570                 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 571                 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 572                 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 573                 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 574                 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 575                 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 576                 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 577                 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 578                 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 579                 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 580                 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 581                 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 582                 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 583         }
 584
 585         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 586                 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
 587                 sve_init_vq_map();
 588         }
 589
 590         /*
 591          * Initialize the indirect array of CPU hwcaps capabilities pointers
 592          * before we handle the boot CPU below.
 593          */
 594         init_cpu_hwcaps_indirect_list();
 595
 596         /*
 597          * Detect and enable early CPU capabilities based on the boot CPU,
 598          * after we have initialised the CPU feature infrastructure.
 599          */
 600         setup_boot_cpu_capabilities();
 601 }
 602
 603 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 604 {
 605         const struct arm64_ftr_bits *ftrp;
 606
 607         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 608                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 609                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 610
 611                 if (ftr_cur == ftr_new)
 612                         continue;
 613                 /* Find a safe value */
 614                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 615                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 616         }
 617
 618 }
 619
 620 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 621 {
 622         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 623
 624         BUG_ON(!regp);
 625         update_cpu_ftr_reg(regp, val);
 626         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 627                 return 0;
 628         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 629                         regp->name, boot, cpu, val);
 630         return 1;
 631 }
 632
 633 /*
 634  * Update system wide CPU feature registers with the values from a
 635  * non-boot CPU. Also performs SANITY checks to make sure that there
 636  * aren't any insane variations from that of the boot CPU.
 637  */
 638 void update_cpu_features(int cpu,
 639                          struct cpuinfo_arm64 *info,
 640                          struct cpuinfo_arm64 *boot)
 641 {
 642         int taint = 0;
 643
 644         /*
 645          * The kernel can handle differing I-cache policies, but otherwise
 646          * caches should look identical. Userspace JITs will make use of
 647          * *minLine.
 648          */
 649         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 650                                       info->reg_ctr, boot->reg_ctr);
 651
 652         /*
 653          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 654          * could result in too much or too little memory being zeroed if a
 655          * process is preempted and migrated between CPUs.
 656          */
 657         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 658                                       info->reg_dczid, boot->reg_dczid);
 659
 660         /* If different, timekeeping will be broken (especially with KVM) */
 661         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 662                                       info->reg_cntfrq, boot->reg_cntfrq);
 663
 664         /*
 665          * The kernel uses self-hosted debug features and expects CPUs to
 666          * support identical debug features. We presently need CTX_CMPs, WRPs,
 667          * and BRPs to be identical.
 668          * ID_AA64DFR1 is currently RES0.
 669          */
 670         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 671                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 672         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 673                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 674         /*
 675          * Even in big.LITTLE, processors should be identical instruction-set
 676          * wise.
 677          */
 678         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 679                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 680         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 681                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 682
 683         /*
 684          * Differing PARange support is fine as long as all peripherals and
 685          * memory are mapped within the minimum PARange of all CPUs.
 686          * Linux should not care about secure memory.
 687          */
 688         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 689                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 690         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 691                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 692         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
 693                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
 694
 695         /*
 696          * EL3 is not our concern.
 697          */
 698         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 699                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 700         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 701                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 702
 703         taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
 704                                       info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
 705
 706         /*
 707          * If we have AArch32, we care about 32-bit features for compat.
 708          * If the system doesn't support AArch32, don't update them.
 709          */
 710         if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 711                 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 712
 713                 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 714                                         info->reg_id_dfr0, boot->reg_id_dfr0);
 715                 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 716                                         info->reg_id_isar0, boot->reg_id_isar0);
 717                 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 718                                         info->reg_id_isar1, boot->reg_id_isar1);
 719                 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 720                                         info->reg_id_isar2, boot->reg_id_isar2);
 721                 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 722                                         info->reg_id_isar3, boot->reg_id_isar3);
 723                 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 724                                         info->reg_id_isar4, boot->reg_id_isar4);
 725                 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 726                                         info->reg_id_isar5, boot->reg_id_isar5);
 727
 728                 /*
 729                  * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 730                  * ACTLR formats could differ across CPUs and therefore would have to
 731                  * be trapped for virtualization anyway.
 732                  */
 733                 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 734                                         info->reg_id_mmfr0, boot->reg_id_mmfr0);
 735                 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 736                                         info->reg_id_mmfr1, boot->reg_id_mmfr1);
 737                 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 738                                         info->reg_id_mmfr2, boot->reg_id_mmfr2);
 739                 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 740                                         info->reg_id_mmfr3, boot->reg_id_mmfr3);
 741                 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 742                                         info->reg_id_pfr0, boot->reg_id_pfr0);
 743                 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 744                                         info->reg_id_pfr1, boot->reg_id_pfr1);
 745                 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 746                                         info->reg_mvfr0, boot->reg_mvfr0);
 747                 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 748                                         info->reg_mvfr1, boot->reg_mvfr1);
 749                 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 750                                         info->reg_mvfr2, boot->reg_mvfr2);
 751         }
 752
 753         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 754                 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
 755                                         info->reg_zcr, boot->reg_zcr);
 756
 757                 /* Probe vector lengths, unless we already gave up on SVE */
 758                 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 759                     !sys_caps_initialised)
 760                         sve_update_vq_map();
 761         }
 762
 763         /*
 764          * Mismatched CPU features are a recipe for disaster. Don't even
 765          * pretend to support them.
 766          */
 767         if (taint) {
 768                 pr_warn_once("Unsupported CPU feature variation detected.\n");
 769                 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
 770         }
 771 }
 772
 773 u64 read_sanitised_ftr_reg(u32 id)
 774 {
 775         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 776
 777         /* We shouldn't get a request for an unsupported register */
 778         BUG_ON(!regp);
 779         return regp->sys_val;
 780 }
 781
 782 #define read_sysreg_case(r)     \
 783         case r:         return read_sysreg_s(r)
 784
 785 /*
 786  * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
 787  * Read the system register on the current CPU
 788  */
 789 static u64 __read_sysreg_by_encoding(u32 sys_id)
 790 {
 791         switch (sys_id) {
 792         read_sysreg_case(SYS_ID_PFR0_EL1);
 793         read_sysreg_case(SYS_ID_PFR1_EL1);
 794         read_sysreg_case(SYS_ID_DFR0_EL1);
 795         read_sysreg_case(SYS_ID_MMFR0_EL1);
 796         read_sysreg_case(SYS_ID_MMFR1_EL1);
 797         read_sysreg_case(SYS_ID_MMFR2_EL1);
 798         read_sysreg_case(SYS_ID_MMFR3_EL1);
 799         read_sysreg_case(SYS_ID_ISAR0_EL1);
 800         read_sysreg_case(SYS_ID_ISAR1_EL1);
 801         read_sysreg_case(SYS_ID_ISAR2_EL1);
 802         read_sysreg_case(SYS_ID_ISAR3_EL1);
 803         read_sysreg_case(SYS_ID_ISAR4_EL1);
 804         read_sysreg_case(SYS_ID_ISAR5_EL1);
 805         read_sysreg_case(SYS_MVFR0_EL1);
 806         read_sysreg_case(SYS_MVFR1_EL1);
 807         read_sysreg_case(SYS_MVFR2_EL1);
 808
 809         read_sysreg_case(SYS_ID_AA64PFR0_EL1);
 810         read_sysreg_case(SYS_ID_AA64PFR1_EL1);
 811         read_sysreg_case(SYS_ID_AA64DFR0_EL1);
 812         read_sysreg_case(SYS_ID_AA64DFR1_EL1);
 813         read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
 814         read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
 815         read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
 816         read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
 817         read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
 818
 819         read_sysreg_case(SYS_CNTFRQ_EL0);
 820         read_sysreg_case(SYS_CTR_EL0);
 821         read_sysreg_case(SYS_DCZID_EL0);
 822
 823         default:
 824                 BUG();
 825                 return 0;
 826         }
 827 }
 828
 829 #include <linux/irqchip/arm-gic-v3.h>
 830
 831 static bool
 832 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
 833 {
 834         int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
 835
 836         return val >= entry->min_field_value;
 837 }
 838
 839 static bool
 840 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
 841 {
 842         u64 val;
 843
 844         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
 845         if (scope == SCOPE_SYSTEM)
 846                 val = read_sanitised_ftr_reg(entry->sys_reg);
 847         else
 848                 val = __read_sysreg_by_encoding(entry->sys_reg);
 849
 850         return feature_matches(val, entry);
 851 }
 852
 853 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
 854 {
 855         bool has_sre;
 856
 857         if (!has_cpuid_feature(entry, scope))
 858                 return false;
 859
 860         has_sre = gic_enable_sre();
 861         if (!has_sre)
 862                 pr_warn_once("%s present but disabled by higher exception level\n",
 863                              entry->desc);
 864
 865         return has_sre;
 866 }
 867
 868 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
 869 {
 870         u32 midr = read_cpuid_id();
 871
 872         /* Cavium ThunderX pass 1.x and 2.x */
 873         return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX,
 874                 MIDR_CPU_VAR_REV(0, 0),
 875                 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
 876 }
 877
 878 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
 879 {
 880         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
 881
 882         return cpuid_feature_extract_signed_field(pfr0,
 883                                         ID_AA64PFR0_FP_SHIFT) < 0;
 884 }
 885
 886 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
 887                           int scope)
 888 {
 889         u64 ctr;
 890
 891         if (scope == SCOPE_SYSTEM)
 892                 ctr = arm64_ftr_reg_ctrel0.sys_val;
 893         else
 894                 ctr = read_cpuid_effective_cachetype();
 895
 896         return ctr & BIT(CTR_IDC_SHIFT);
 897 }
 898
 899 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
 900 {
 901         /*
 902          * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
 903          * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
 904          * to the CTR_EL0 on this CPU and emulate it with the real/safe
 905          * value.
 906          */
 907         if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
 908                 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
 909 }
 910
 911 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
 912                           int scope)
 913 {
 914         u64 ctr;
 915
 916         if (scope == SCOPE_SYSTEM)
 917                 ctr = arm64_ftr_reg_ctrel0.sys_val;
 918         else
 919                 ctr = read_cpuid_cachetype();
 920
 921         return ctr & BIT(CTR_DIC_SHIFT);
 922 }
 923
 924 static bool __maybe_unused
 925 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
 926 {
 927         /*
 928          * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
 929          * may share TLB entries with a CPU stuck in the crashed
 930          * kernel.
 931          */
 932          if (is_kdump_kernel())
 933                 return false;
 934
 935         return has_cpuid_feature(entry, scope);
 936 }
 937
 938 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
 939 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
 940
 941 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
 942                                 int scope)
 943 {
 944         /* List of CPUs that are not vulnerable and don't need KPTI */
 945         static const struct midr_range kpti_safe_list[] = {
 946                 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
 947                 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
 948                 { /* sentinel */ }
 949         };
 950         char const *str = "command line option";
 951
 952         /*
 953          * For reasons that aren't entirely clear, enabling KPTI on Cavium
 954          * ThunderX leads to apparent I-cache corruption of kernel text, which
 955          * ends as well as you might imagine. Don't even try.
 956          */
 957         if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
 958                 str = "ARM64_WORKAROUND_CAVIUM_27456";
 959                 __kpti_forced = -1;
 960         }
 961
 962         /* Forced? */
 963         if (__kpti_forced) {
 964                 pr_info_once("kernel page table isolation forced %s by %s\n",
 965                              __kpti_forced > 0 ? "ON" : "OFF", str);
 966                 return __kpti_forced > 0;
 967         }
 968
 969         /* Useful for KASLR robustness */
 970         if (IS_ENABLED(CONFIG_RANDOMIZE_BASE))
 971                 return true;
 972
 973         /* Don't force KPTI for CPUs that are not vulnerable */
 974         if (is_midr_in_range_list(read_cpuid_id(), kpti_safe_list))
 975                 return false;
 976
 977         /* Defer to CPU feature registers */
 978         return !has_cpuid_feature(entry, scope);
 979 }
 980
 981 static void
 982 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
 983 {
 984         typedef void (kpti_remap_fn)(int, int, phys_addr_t);
 985         extern kpti_remap_fn idmap_kpti_install_ng_mappings;
 986         kpti_remap_fn *remap_fn;
 987
 988         static bool kpti_applied = false;
 989         int cpu = smp_processor_id();
 990
 991         if (kpti_applied)
 992                 return;
 993
 994         remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
 995
 996         cpu_install_idmap();
 997         remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
 998         cpu_uninstall_idmap();
 999
1000         if (!cpu)
1001                 kpti_applied = true;
1002
1003         return;
1004 }
1005
1006 static int __init parse_kpti(char *str)
1007 {
1008         bool enabled;
1009         int ret = strtobool(str, &enabled);
1010
1011         if (ret)
1012                 return ret;
1013
1014         __kpti_forced = enabled ? 1 : -1;
1015         return 0;
1016 }
1017 early_param("kpti", parse_kpti);
1018 #endif  /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1019
1020 #ifdef CONFIG_ARM64_HW_AFDBM
1021 static inline void __cpu_enable_hw_dbm(void)
1022 {
1023         u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1024
1025         write_sysreg(tcr, tcr_el1);
1026         isb();
1027 }
1028
1029 static bool cpu_has_broken_dbm(void)
1030 {
1031         /* List of CPUs which have broken DBM support. */
1032         static const struct midr_range cpus[] = {
1033 #ifdef CONFIG_ARM64_ERRATUM_1024718
1034                 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0),  // A55 r0p0 -r1p0
1035 #endif
1036                 {},
1037         };
1038
1039         return is_midr_in_range_list(read_cpuid_id(), cpus);
1040 }
1041
1042 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1043 {
1044         return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1045                !cpu_has_broken_dbm();
1046 }
1047
1048 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1049 {
1050         if (cpu_can_use_dbm(cap))
1051                 __cpu_enable_hw_dbm();
1052 }
1053
1054 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1055                        int __unused)
1056 {
1057         static bool detected = false;
1058         /*
1059          * DBM is a non-conflicting feature. i.e, the kernel can safely
1060          * run a mix of CPUs with and without the feature. So, we
1061          * unconditionally enable the capability to allow any late CPU
1062          * to use the feature. We only enable the control bits on the
1063          * CPU, if it actually supports.
1064          *
1065          * We have to make sure we print the "feature" detection only
1066          * when at least one CPU actually uses it. So check if this CPU
1067          * can actually use it and print the message exactly once.
1068          *
1069          * This is safe as all CPUs (including secondary CPUs - due to the
1070          * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1071          * goes through the "matches" check exactly once. Also if a CPU
1072          * matches the criteria, it is guaranteed that the CPU will turn
1073          * the DBM on, as the capability is unconditionally enabled.
1074          */
1075         if (!detected && cpu_can_use_dbm(cap)) {
1076                 detected = true;
1077                 pr_info("detected: Hardware dirty bit management\n");
1078         }
1079
1080         return true;
1081 }
1082
1083 #endif
1084
1085 #ifdef CONFIG_ARM64_VHE
1086 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1087 {
1088         return is_kernel_in_hyp_mode();
1089 }
1090
1091 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1092 {
1093         /*
1094          * Copy register values that aren't redirected by hardware.
1095          *
1096          * Before code patching, we only set tpidr_el1, all CPUs need to copy
1097          * this value to tpidr_el2 before we patch the code. Once we've done
1098          * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1099          * do anything here.
1100          */
1101         if (!alternatives_applied)
1102                 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1103 }
1104 #endif
1105
1106 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1107 {
1108         u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1109
1110         /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1111         WARN_ON(val & (7 << 27 | 7 << 21));
1112 }
1113
1114 #ifdef CONFIG_ARM64_SSBD
1115 static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
1116 {
1117         if (user_mode(regs))
1118                 return 1;
1119
1120         if (instr & BIT(PSTATE_Imm_shift))
1121                 regs->pstate |= PSR_SSBS_BIT;
1122         else
1123                 regs->pstate &= ~PSR_SSBS_BIT;
1124
1125         arm64_skip_faulting_instruction(regs, 4);
1126         return 0;
1127 }
1128
1129 static struct undef_hook ssbs_emulation_hook = {
1130         .instr_mask     = ~(1U << PSTATE_Imm_shift),
1131         .instr_val      = 0xd500401f | PSTATE_SSBS,
1132         .fn             = ssbs_emulation_handler,
1133 };
1134
1135 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
1136 {
1137         static bool undef_hook_registered = false;
1138         static DEFINE_SPINLOCK(hook_lock);
1139
1140         spin_lock(&hook_lock);
1141         if (!undef_hook_registered) {
1142                 register_undef_hook(&ssbs_emulation_hook);
1143                 undef_hook_registered = true;
1144         }
1145         spin_unlock(&hook_lock);
1146
1147         if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
1148                 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
1149                 arm64_set_ssbd_mitigation(false);
1150         } else {
1151                 arm64_set_ssbd_mitigation(true);
1152         }
1153 }
1154 #endif /* CONFIG_ARM64_SSBD */
1155
1156 #ifdef CONFIG_ARM64_PAN
1157 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1158 {
1159         /*
1160          * We modify PSTATE. This won't work from irq context as the PSTATE
1161          * is discarded once we return from the exception.
1162          */
1163         WARN_ON_ONCE(in_interrupt());
1164
1165         sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1166         asm(SET_PSTATE_PAN(1));
1167 }
1168 #endif /* CONFIG_ARM64_PAN */
1169
1170 #ifdef CONFIG_ARM64_RAS_EXTN
1171 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1172 {
1173         /* Firmware may have left a deferred SError in this register. */
1174         write_sysreg_s(0, SYS_DISR_EL1);
1175 }
1176 #endif /* CONFIG_ARM64_RAS_EXTN */
1177
1178 static const struct arm64_cpu_capabilities arm64_features[] = {
1179         {
1180                 .desc = "GIC system register CPU interface",
1181                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1182                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1183                 .matches = has_useable_gicv3_cpuif,
1184                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1185                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1186                 .sign = FTR_UNSIGNED,
1187                 .min_field_value = 1,
1188         },
1189 #ifdef CONFIG_ARM64_PAN
1190         {
1191                 .desc = "Privileged Access Never",
1192                 .capability = ARM64_HAS_PAN,
1193                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1194                 .matches = has_cpuid_feature,
1195                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1196                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1197                 .sign = FTR_UNSIGNED,
1198                 .min_field_value = 1,
1199                 .cpu_enable = cpu_enable_pan,
1200         },
1201 #endif /* CONFIG_ARM64_PAN */
1202 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
1203         {
1204                 .desc = "LSE atomic instructions",
1205                 .capability = ARM64_HAS_LSE_ATOMICS,
1206                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1207                 .matches = has_cpuid_feature,
1208                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1209                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1210                 .sign = FTR_UNSIGNED,
1211                 .min_field_value = 2,
1212         },
1213 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
1214         {
1215                 .desc = "Software prefetching using PRFM",
1216                 .capability = ARM64_HAS_NO_HW_PREFETCH,
1217                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1218                 .matches = has_no_hw_prefetch,
1219         },
1220 #ifdef CONFIG_ARM64_UAO
1221         {
1222                 .desc = "User Access Override",
1223                 .capability = ARM64_HAS_UAO,
1224                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1225                 .matches = has_cpuid_feature,
1226                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1227                 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1228                 .min_field_value = 1,
1229                 /*
1230                  * We rely on stop_machine() calling uao_thread_switch() to set
1231                  * UAO immediately after patching.
1232                  */
1233         },
1234 #endif /* CONFIG_ARM64_UAO */
1235 #ifdef CONFIG_ARM64_PAN
1236         {
1237                 .capability = ARM64_ALT_PAN_NOT_UAO,
1238                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1239                 .matches = cpufeature_pan_not_uao,
1240         },
1241 #endif /* CONFIG_ARM64_PAN */
1242 #ifdef CONFIG_ARM64_VHE
1243         {
1244                 .desc = "Virtualization Host Extensions",
1245                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1246                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1247                 .matches = runs_at_el2,
1248                 .cpu_enable = cpu_copy_el2regs,
1249         },
1250 #endif  /* CONFIG_ARM64_VHE */
1251         {
1252                 .desc = "32-bit EL0 Support",
1253                 .capability = ARM64_HAS_32BIT_EL0,
1254                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1255                 .matches = has_cpuid_feature,
1256                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1257                 .sign = FTR_UNSIGNED,
1258                 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1259                 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1260         },
1261 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1262         {
1263                 .desc = "Kernel page table isolation (KPTI)",
1264                 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1265                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1266                 /*
1267                  * The ID feature fields below are used to indicate that
1268                  * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1269                  * more details.
1270                  */
1271                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1272                 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1273                 .min_field_value = 1,
1274                 .matches = unmap_kernel_at_el0,
1275                 .cpu_enable = kpti_install_ng_mappings,
1276         },
1277 #endif
1278         {
1279                 /* FP/SIMD is not implemented */
1280                 .capability = ARM64_HAS_NO_FPSIMD,
1281                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1282                 .min_field_value = 0,
1283                 .matches = has_no_fpsimd,
1284         },
1285 #ifdef CONFIG_ARM64_PMEM
1286         {
1287                 .desc = "Data cache clean to Point of Persistence",
1288                 .capability = ARM64_HAS_DCPOP,
1289                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1290                 .matches = has_cpuid_feature,
1291                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1292                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1293                 .min_field_value = 1,
1294         },
1295 #endif
1296 #ifdef CONFIG_ARM64_SVE
1297         {
1298                 .desc = "Scalable Vector Extension",
1299                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1300                 .capability = ARM64_SVE,
1301                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1302                 .sign = FTR_UNSIGNED,
1303                 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1304                 .min_field_value = ID_AA64PFR0_SVE,
1305                 .matches = has_cpuid_feature,
1306                 .cpu_enable = sve_kernel_enable,
1307         },
1308 #endif /* CONFIG_ARM64_SVE */
1309 #ifdef CONFIG_ARM64_RAS_EXTN
1310         {
1311                 .desc = "RAS Extension Support",
1312                 .capability = ARM64_HAS_RAS_EXTN,
1313                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1314                 .matches = has_cpuid_feature,
1315                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1316                 .sign = FTR_UNSIGNED,
1317                 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1318                 .min_field_value = ID_AA64PFR0_RAS_V1,
1319                 .cpu_enable = cpu_clear_disr,
1320         },
1321 #endif /* CONFIG_ARM64_RAS_EXTN */
1322         {
1323                 .desc = "Data cache clean to the PoU not required for I/D coherence",
1324                 .capability = ARM64_HAS_CACHE_IDC,
1325                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1326                 .matches = has_cache_idc,
1327                 .cpu_enable = cpu_emulate_effective_ctr,
1328         },
1329         {
1330                 .desc = "Instruction cache invalidation not required for I/D coherence",
1331                 .capability = ARM64_HAS_CACHE_DIC,
1332                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1333                 .matches = has_cache_dic,
1334         },
1335         {
1336                 .desc = "Stage-2 Force Write-Back",
1337                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1338                 .capability = ARM64_HAS_STAGE2_FWB,
1339                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1340                 .sign = FTR_UNSIGNED,
1341                 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
1342                 .min_field_value = 1,
1343                 .matches = has_cpuid_feature,
1344                 .cpu_enable = cpu_has_fwb,
1345         },
1346 #ifdef CONFIG_ARM64_HW_AFDBM
1347         {
1348                 /*
1349                  * Since we turn this on always, we don't want the user to
1350                  * think that the feature is available when it may not be.
1351                  * So hide the description.
1352                  *
1353                  * .desc = "Hardware pagetable Dirty Bit Management",
1354                  *
1355                  */
1356                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1357                 .capability = ARM64_HW_DBM,
1358                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1359                 .sign = FTR_UNSIGNED,
1360                 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
1361                 .min_field_value = 2,
1362                 .matches = has_hw_dbm,
1363                 .cpu_enable = cpu_enable_hw_dbm,
1364         },
1365 #endif
1366 #ifdef CONFIG_ARM64_SSBD
1367         {
1368                 .desc = "CRC32 instructions",
1369                 .capability = ARM64_HAS_CRC32,
1370                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1371                 .matches = has_cpuid_feature,
1372                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1373                 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
1374                 .min_field_value = 1,
1375         },
1376         {
1377                 .desc = "Speculative Store Bypassing Safe (SSBS)",
1378                 .capability = ARM64_SSBS,
1379                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1380                 .matches = has_cpuid_feature,
1381                 .sys_reg = SYS_ID_AA64PFR1_EL1,
1382                 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
1383                 .sign = FTR_UNSIGNED,
1384                 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
1385                 .cpu_enable = cpu_enable_ssbs,
1386         },
1387 #endif
1388 #ifdef CONFIG_ARM64_CNP
1389         {
1390                 .desc = "Common not Private translations",
1391                 .capability = ARM64_HAS_CNP,
1392                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1393                 .matches = has_useable_cnp,
1394                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1395                 .sign = FTR_UNSIGNED,
1396                 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
1397                 .min_field_value = 1,
1398                 .cpu_enable = cpu_enable_cnp,
1399         },
1400 #endif
1401         {},
1402 };
1403
1404 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap)      \
1405         {                                                       \
1406                 .desc = #cap,                                   \
1407                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,            \
1408                 .matches = has_cpuid_feature,                   \
1409                 .sys_reg = reg,                                 \
1410                 .field_pos = field,                             \
1411                 .sign = s,                                      \
1412                 .min_field_value = min_value,                   \
1413                 .hwcap_type = cap_type,                         \
1414                 .hwcap = cap,                                   \
1415         }
1416
1417 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
1418         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
1419         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
1420         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
1421         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
1422         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_SHA512),
1423         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
1424         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
1425         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM),
1426         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA3),
1427         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM3),
1428         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM4),
1429         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDDP),
1430         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDFHM),
1431         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FLAGM),
1432         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
1433         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
1434         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
1435         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
1436         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_DIT),
1437         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP),
1438         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),
1439         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),
1440         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC),
1441         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ILRCPC),
1442         HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_USCAT),
1443 #ifdef CONFIG_ARM64_SVE
1444         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE),
1445 #endif
1446         HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, HWCAP_SSBS),
1447         {},
1448 };
1449
1450 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
1451 #ifdef CONFIG_COMPAT
1452         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1453         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1454         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1455         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1456         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
1457 #endif
1458         {},
1459 };
1460
1461 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1462 {
1463         switch (cap->hwcap_type) {
1464         case CAP_HWCAP:
1465                 elf_hwcap |= cap->hwcap;
1466                 break;
1467 #ifdef CONFIG_COMPAT
1468         case CAP_COMPAT_HWCAP:
1469                 compat_elf_hwcap |= (u32)cap->hwcap;
1470                 break;
1471         case CAP_COMPAT_HWCAP2:
1472                 compat_elf_hwcap2 |= (u32)cap->hwcap;
1473                 break;
1474 #endif
1475         default:
1476                 WARN_ON(1);
1477                 break;
1478         }
1479 }
1480
1481 /* Check if we have a particular HWCAP enabled */
1482 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1483 {
1484         bool rc;
1485
1486         switch (cap->hwcap_type) {
1487         case CAP_HWCAP:
1488                 rc = (elf_hwcap & cap->hwcap) != 0;
1489                 break;
1490 #ifdef CONFIG_COMPAT
1491         case CAP_COMPAT_HWCAP:
1492                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1493                 break;
1494         case CAP_COMPAT_HWCAP2:
1495                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1496                 break;
1497 #endif
1498         default:
1499                 WARN_ON(1);
1500                 rc = false;
1501         }
1502
1503         return rc;
1504 }
1505
1506 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
1507 {
1508         /* We support emulation of accesses to CPU ID feature registers */
1509         elf_hwcap |= HWCAP_CPUID;
1510         for (; hwcaps->matches; hwcaps++)
1511                 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
1512                         cap_set_elf_hwcap(hwcaps);
1513 }
1514
1515 static void update_cpu_capabilities(u16 scope_mask)
1516 {
1517         int i;
1518         const struct arm64_cpu_capabilities *caps;
1519
1520         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1521         for (i = 0; i < ARM64_NCAPS; i++) {
1522                 caps = cpu_hwcaps_ptrs[i];
1523                 if (!caps || !(caps->type & scope_mask) ||
1524                     cpus_have_cap(caps->capability) ||
1525                     !caps->matches(caps, cpucap_default_scope(caps)))
1526                         continue;
1527
1528                 if (caps->desc)
1529                         pr_info("detected: %s\n", caps->desc);
1530                 cpus_set_cap(caps->capability);
1531         }
1532 }
1533
1534 static int __enable_cpu_capability(void *arg)
1535 {
1536         const struct arm64_cpu_capabilities *cap = arg;
1537
1538         cap->cpu_enable(cap);
1539         return 0;
1540 }
1541
1542 /*
1543  * Run through the enabled capabilities and enable() it on all active
1544  * CPUs
1545  */
1546 static void __init
1547 __enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
1548                           u16 scope_mask)
1549 {
1550         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1551         for (; caps->matches; caps++) {
1552                 unsigned int num = caps->capability;
1553
1554                 if (!(caps->type & scope_mask) || !cpus_have_cap(num))
1555                         continue;
1556
1557                 /* Ensure cpus_have_const_cap(num) works */
1558                 static_branch_enable(&cpu_hwcap_keys[num]);
1559
1560                 if (caps->cpu_enable) {
1561                         /*
1562                          * Capabilities with SCOPE_BOOT_CPU scope are finalised
1563                          * before any secondary CPU boots. Thus, each secondary
1564                          * will enable the capability as appropriate via
1565                          * check_local_cpu_capabilities(). The only exception is
1566                          * the boot CPU, for which the capability must be
1567                          * enabled here. This approach avoids costly
1568                          * stop_machine() calls for this case.
1569                          *
1570                          * Otherwise, use stop_machine() as it schedules the
1571                          * work allowing us to modify PSTATE, instead of
1572                          * on_each_cpu() which uses an IPI, giving us a PSTATE
1573                          * that disappears when we return.
1574                          */
1575                         if (scope_mask & SCOPE_BOOT_CPU)
1576                                 caps->cpu_enable(caps);
1577                         else
1578                                 stop_machine(__enable_cpu_capability,
1579                                              (void *)caps, cpu_online_mask);
1580                 }
1581         }
1582 }
1583
1584 static void __init enable_cpu_capabilities(u16 scope_mask)
1585 {
1586         __enable_cpu_capabilities(arm64_errata, scope_mask);
1587         __enable_cpu_capabilities(arm64_features, scope_mask);
1588 }
1589
1590 /*
1591  * Run through the list of capabilities to check for conflicts.
1592  * If the system has already detected a capability, take necessary
1593  * action on this CPU.
1594  *
1595  * Returns "false" on conflicts.
1596  */
1597 static bool verify_local_cpu_caps(u16 scope_mask)
1598 {
1599         int i;
1600         bool cpu_has_cap, system_has_cap;
1601         const struct arm64_cpu_capabilities *caps;
1602
1603         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1604
1605         for (i = 0; i < ARM64_NCAPS; i++) {
1606                 caps = cpu_hwcaps_ptrs[i];
1607                 if (!caps || !(caps->type & scope_mask))
1608                         continue;
1609
1610                 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
1611                 system_has_cap = cpus_have_cap(caps->capability);
1612
1613                 if (system_has_cap) {
1614                         /*
1615                          * Check if the new CPU misses an advertised feature,
1616                          * which is not safe to miss.
1617                          */
1618                         if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
1619                                 break;
1620                         /*
1621                          * We have to issue cpu_enable() irrespective of
1622                          * whether the CPU has it or not, as it is enabeld
1623                          * system wide. It is upto the call back to take
1624                          * appropriate action on this CPU.
1625                          */
1626                         if (caps->cpu_enable)
1627                                 caps->cpu_enable(caps);
1628                 } else {
1629                         /*
1630                          * Check if the CPU has this capability if it isn't
1631                          * safe to have when the system doesn't.
1632                          */
1633                         if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
1634                                 break;
1635                 }
1636         }
1637
1638         if (i < ARM64_NCAPS) {
1639                 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
1640                         smp_processor_id(), caps->capability,
1641                         caps->desc, system_has_cap, cpu_has_cap);
1642                 return false;
1643         }
1644
1645         return true;
1646 }
1647
1648 /*
1649  * Check for CPU features that are used in early boot
1650  * based on the Boot CPU value.
1651  */
1652 static void check_early_cpu_features(void)
1653 {
1654         verify_cpu_asid_bits();
1655         /*
1656          * Early features are used by the kernel already. If there
1657          * is a conflict, we cannot proceed further.
1658          */
1659         if (!verify_local_cpu_caps(SCOPE_BOOT_CPU))
1660                 cpu_panic_kernel();
1661 }
1662
1663 static void
1664 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1665 {
1666
1667         for (; caps->matches; caps++)
1668                 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
1669                         pr_crit("CPU%d: missing HWCAP: %s\n",
1670                                         smp_processor_id(), caps->desc);
1671                         cpu_die_early();
1672                 }
1673 }
1674
1675 static void verify_sve_features(void)
1676 {
1677         u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
1678         u64 zcr = read_zcr_features();
1679
1680         unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
1681         unsigned int len = zcr & ZCR_ELx_LEN_MASK;
1682
1683         if (len < safe_len || sve_verify_vq_map()) {
1684                 pr_crit("CPU%d: SVE: required vector length(s) missing\n",
1685                         smp_processor_id());
1686                 cpu_die_early();
1687         }
1688
1689         /* Add checks on other ZCR bits here if necessary */
1690 }
1691
1692
1693 /*
1694  * Run through the enabled system capabilities and enable() it on this CPU.
1695  * The capabilities were decided based on the available CPUs at the boot time.
1696  * Any new CPU should match the system wide status of the capability. If the
1697  * new CPU doesn't have a capability which the system now has enabled, we
1698  * cannot do anything to fix it up and could cause unexpected failures. So
1699  * we park the CPU.
1700  */
1701 static void verify_local_cpu_capabilities(void)
1702 {
1703         /*
1704          * The capabilities with SCOPE_BOOT_CPU are checked from
1705          * check_early_cpu_features(), as they need to be verified
1706          * on all secondary CPUs.
1707          */
1708         if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU))
1709                 cpu_die_early();
1710
1711         verify_local_elf_hwcaps(arm64_elf_hwcaps);
1712
1713         if (system_supports_32bit_el0())
1714                 verify_local_elf_hwcaps(compat_elf_hwcaps);
1715
1716         if (system_supports_sve())
1717                 verify_sve_features();
1718 }
1719
1720 void check_local_cpu_capabilities(void)
1721 {
1722         /*
1723          * All secondary CPUs should conform to the early CPU features
1724          * in use by the kernel based on boot CPU.
1725          */
1726         check_early_cpu_features();
1727
1728         /*
1729          * If we haven't finalised the system capabilities, this CPU gets
1730          * a chance to update the errata work arounds and local features.
1731          * Otherwise, this CPU should verify that it has all the system
1732          * advertised capabilities.
1733          */
1734         if (!sys_caps_initialised)
1735                 update_cpu_capabilities(SCOPE_LOCAL_CPU);
1736         else
1737                 verify_local_cpu_capabilities();
1738 }
1739
1740 static void __init setup_boot_cpu_capabilities(void)
1741 {
1742         /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
1743         update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
1744         /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
1745         enable_cpu_capabilities(SCOPE_BOOT_CPU);
1746 }
1747
1748 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
1749 EXPORT_SYMBOL(arm64_const_caps_ready);
1750
1751 static void __init mark_const_caps_ready(void)
1752 {
1753         static_branch_enable(&arm64_const_caps_ready);
1754 }
1755
1756 bool this_cpu_has_cap(unsigned int n)
1757 {
1758         if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
1759                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
1760
1761                 if (cap)
1762                         return cap->matches(cap, SCOPE_LOCAL_CPU);
1763         }
1764
1765         return false;
1766 }
1767
1768 static void __init setup_system_capabilities(void)
1769 {
1770         /*
1771          * We have finalised the system-wide safe feature
1772          * registers, finalise the capabilities that depend
1773          * on it. Also enable all the available capabilities,
1774          * that are not enabled already.
1775          */
1776         update_cpu_capabilities(SCOPE_SYSTEM);
1777         enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
1778 }
1779
1780 void __init setup_cpu_features(void)
1781 {
1782         u32 cwg;
1783
1784         setup_system_capabilities();
1785         mark_const_caps_ready();
1786         setup_elf_hwcaps(arm64_elf_hwcaps);
1787
1788         if (system_supports_32bit_el0())
1789                 setup_elf_hwcaps(compat_elf_hwcaps);
1790
1791         if (system_uses_ttbr0_pan())
1792                 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
1793
1794         sve_setup();
1795         minsigstksz_setup();
1796
1797         /* Advertise that we have computed the system capabilities */
1798         set_sys_caps_initialised();
1799
1800         /*
1801          * Check for sane CTR_EL0.CWG value.
1802          */
1803         cwg = cache_type_cwg();
1804         if (!cwg)
1805                 pr_warn("No Cache Writeback Granule information, assuming %d\n",
1806                         ARCH_DMA_MINALIGN);
1807 }
1808
1809 static bool __maybe_unused
1810 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
1811 {
1812         return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
1813 }
1814
1815 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
1816 {
1817         cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
1818 }
1819
1820 /*
1821  * We emulate only the following system register space.
1822  * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
1823  * See Table C5-6 System instruction encodings for System register accesses,
1824  * ARMv8 ARM(ARM DDI 0487A.f) for more details.
1825  */
1826 static inline bool __attribute_const__ is_emulated(u32 id)
1827 {
1828         return (sys_reg_Op0(id) == 0x3 &&
1829                 sys_reg_CRn(id) == 0x0 &&
1830                 sys_reg_Op1(id) == 0x0 &&
1831                 (sys_reg_CRm(id) == 0 ||
1832                  ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
1833 }
1834
1835 /*
1836  * With CRm == 0, reg should be one of :
1837  * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
1838  */
1839 static inline int emulate_id_reg(u32 id, u64 *valp)
1840 {
1841         switch (id) {
1842         case SYS_MIDR_EL1:
1843                 *valp = read_cpuid_id();
1844                 break;
1845         case SYS_MPIDR_EL1:
1846                 *valp = SYS_MPIDR_SAFE_VAL;
1847                 break;
1848         case SYS_REVIDR_EL1:
1849                 /* IMPLEMENTATION DEFINED values are emulated with 0 */
1850                 *valp = 0;
1851                 break;
1852         default:
1853                 return -EINVAL;
1854         }
1855
1856         return 0;
1857 }
1858
1859 static int emulate_sys_reg(u32 id, u64 *valp)
1860 {
1861         struct arm64_ftr_reg *regp;
1862
1863         if (!is_emulated(id))
1864                 return -EINVAL;
1865
1866         if (sys_reg_CRm(id) == 0)
1867                 return emulate_id_reg(id, valp);
1868
1869         regp = get_arm64_ftr_reg(id);
1870         if (regp)
1871                 *valp = arm64_ftr_reg_user_value(regp);
1872         else
1873                 /*
1874                  * The untracked registers are either IMPLEMENTATION DEFINED
1875                  * (e.g, ID_AFR0_EL1) or reserved RAZ.
1876                  */
1877                 *valp = 0;
1878         return 0;
1879 }
1880
1881 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
1882 {
1883         int rc;
1884         u64 val;
1885
1886         rc = emulate_sys_reg(sys_reg, &val);
1887         if (!rc) {
1888                 pt_regs_write_reg(regs, rt, val);
1889                 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
1890         }
1891         return rc;
1892 }
1893
1894 static int emulate_mrs(struct pt_regs *regs, u32 insn)
1895 {
1896         u32 sys_reg, rt;
1897
1898         /*
1899          * sys_reg values are defined as used in mrs/msr instruction.
1900          * shift the imm value to get the encoding.
1901          */
1902         sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
1903         rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
1904         return do_emulate_mrs(regs, sys_reg, rt);
1905 }
1906
1907 static struct undef_hook mrs_hook = {
1908         .instr_mask = 0xfff00000,
1909         .instr_val  = 0xd5300000,
1910         .pstate_mask = PSR_AA32_MODE_MASK,
1911         .pstate_val = PSR_MODE_EL0t,
1912         .fn = emulate_mrs,
1913 };
1914
1915 static int __init enable_mrs_emulation(void)
1916 {
1917         register_undef_hook(&mrs_hook);
1918         return 0;
1919 }
1920
1921 core_initcall(enable_mrs_emulation);