arch/arm64/kernel/cpufeature.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Contains CPU feature definitions
   4  *
   5  * Copyright (C) 2015 ARM Ltd.
   6  */
   7
   8 #define pr_fmt(fmt) "CPU features: " fmt
   9
  10 #include <linux/bsearch.h>
  11 #include <linux/cpumask.h>
  12 #include <linux/crash_dump.h>
  13 #include <linux/sort.h>
  14 #include <linux/stop_machine.h>
  15 #include <linux/types.h>
  16 #include <linux/mm.h>
  17 #include <linux/cpu.h>
  18 #include <asm/cpu.h>
  19 #include <asm/cpufeature.h>
  20 #include <asm/cpu_ops.h>
  21 #include <asm/fpsimd.h>
  22 #include <asm/mmu_context.h>
  23 #include <asm/processor.h>
  24 #include <asm/sysreg.h>
  25 #include <asm/traps.h>
  26 #include <asm/virt.h>
  27
  28 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
  29 static unsigned long elf_hwcap __read_mostly;
  30
  31 #ifdef CONFIG_COMPAT
  32 #define COMPAT_ELF_HWCAP_DEFAULT        \
  33                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  34                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  35                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
  36                                  COMPAT_HWCAP_LPAE)
  37 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  38 unsigned int compat_elf_hwcap2 __read_mostly;
  39 #endif
  40
  41 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  42 EXPORT_SYMBOL(cpu_hwcaps);
  43 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
  44
  45 /* Need also bit for ARM64_CB_PATCH */
  46 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
  47
  48 bool arm64_use_ng_mappings = false;
  49 EXPORT_SYMBOL(arm64_use_ng_mappings);
  50
  51 /*
  52  * Flag to indicate if we have computed the system wide
  53  * capabilities based on the boot time active CPUs. This
  54  * will be used to determine if a new booting CPU should
  55  * go through the verification process to make sure that it
  56  * supports the system capabilities, without using a hotplug
  57  * notifier. This is also used to decide if we could use
  58  * the fast path for checking constant CPU caps.
  59  */
  60 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
  61 EXPORT_SYMBOL(arm64_const_caps_ready);
  62 static inline void finalize_system_capabilities(void)
  63 {
  64         static_branch_enable(&arm64_const_caps_ready);
  65 }
  66
  67 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
  68 {
  69         /* file-wide pr_fmt adds "CPU features: " prefix */
  70         pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
  71         return 0;
  72 }
  73
  74 static struct notifier_block cpu_hwcaps_notifier = {
  75         .notifier_call = dump_cpu_hwcaps
  76 };
  77
  78 static int __init register_cpu_hwcaps_dumper(void)
  79 {
  80         atomic_notifier_chain_register(&panic_notifier_list,
  81                                        &cpu_hwcaps_notifier);
  82         return 0;
  83 }
  84 __initcall(register_cpu_hwcaps_dumper);
  85
  86 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
  87 EXPORT_SYMBOL(cpu_hwcap_keys);
  88
  89 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  90         {                                               \
  91                 .sign = SIGNED,                         \
  92                 .visible = VISIBLE,                     \
  93                 .strict = STRICT,                       \
  94                 .type = TYPE,                           \
  95                 .shift = SHIFT,                         \
  96                 .width = WIDTH,                         \
  97                 .safe_val = SAFE_VAL,                   \
  98         }
  99
 100 /* Define a feature with unsigned values */
 101 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 102         __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 103
 104 /* Define a feature with a signed value */
 105 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 106         __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 107
 108 #define ARM64_FTR_END                                   \
 109         {                                               \
 110                 .width = 0,                             \
 111         }
 112
 113 /* meta feature for alternatives */
 114 static bool __maybe_unused
 115 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
 116
 117 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
 118
 119 /*
 120  * NOTE: Any changes to the visibility of features should be kept in
 121  * sync with the documentation of the CPU feature register ABI.
 122  */
 123 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
 124         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0),
 125         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
 126         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
 127         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
 128         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
 129         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
 130         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
 131         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
 132         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
 133         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
 134         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
 135         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
 136         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
 137         ARM64_FTR_END,
 138 };
 139
 140 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
 141         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0),
 142         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0),
 143         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0),
 144         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0),
 145         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
 146         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
 147         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 148                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
 149         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 150                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
 151         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
 152         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
 153         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
 154         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 155                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0),
 156         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 157                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0),
 158         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
 159         ARM64_FTR_END,
 160 };
 161
 162 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
 163         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
 164         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
 165         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
 166         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0),
 167         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 168                                    FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
 169         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
 170         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
 171         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
 172         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
 173         /* Linux doesn't care about the EL3 */
 174         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
 175         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
 176         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
 177         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
 178         ARM64_FTR_END,
 179 };
 180
 181 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
 182         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
 183         ARM64_FTR_END,
 184 };
 185
 186 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
 187         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 188                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0),
 189         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 190                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0),
 191         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 192                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0),
 193         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 194                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
 195         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 196                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
 197         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 198                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0),
 199         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 200                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
 201         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 202                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
 203         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 204                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
 205         ARM64_FTR_END,
 206 };
 207
 208 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 209         /*
 210          * We already refuse to boot CPUs that don't support our configured
 211          * page size, so we can only detect mismatches for a page size other
 212          * than the one we're currently using. Unfortunately, SoCs like this
 213          * exist in the wild so, even though we don't like it, we'll have to go
 214          * along with it and treat them as non-strict.
 215          */
 216         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 217         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 218         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 219
 220         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 221         /* Linux shouldn't care about secure memory */
 222         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 223         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 224         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 225         /*
 226          * Differing PARange is fine as long as all peripherals and memory are mapped
 227          * within the minimum PARange of all CPUs
 228          */
 229         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 230         ARM64_FTR_END,
 231 };
 232
 233 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 234         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 235         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 236         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 237         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 238         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 239         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 240         ARM64_FTR_END,
 241 };
 242
 243 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 244         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0),
 245         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
 246         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
 247         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
 248         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
 249         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
 250         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
 251         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
 252         ARM64_FTR_END,
 253 };
 254
 255 static const struct arm64_ftr_bits ftr_ctr[] = {
 256         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
 257         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
 258         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
 259         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
 260         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
 261         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
 262         /*
 263          * Linux can handle differing I-cache policies. Userspace JITs will
 264          * make use of *minLine.
 265          * If we have differing I-cache policies, report it as the weakest - VIPT.
 266          */
 267         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT),       /* L1Ip */
 268         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
 269         ARM64_FTR_END,
 270 };
 271
 272 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
 273         .name           = "SYS_CTR_EL0",
 274         .ftr_bits       = ftr_ctr
 275 };
 276
 277 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
 278         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf),   /* InnerShr */
 279         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),       /* FCSE */
 280         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),    /* AuxReg */
 281         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),       /* TCM */
 282         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),       /* ShareLvl */
 283         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf),    /* OuterShr */
 284         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* PMSA */
 285         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),        /* VMSA */
 286         ARM64_FTR_END,
 287 };
 288
 289 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 290         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
 291         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
 292         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 293         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 294         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 295         /*
 296          * We can instantiate multiple PMU instances with different levels
 297          * of support.
 298          */
 299         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 300         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
 301         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 302         ARM64_FTR_END,
 303 };
 304
 305 static const struct arm64_ftr_bits ftr_mvfr2[] = {
 306         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* FPMisc */
 307         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* SIMDMisc */
 308         ARM64_FTR_END,
 309 };
 310
 311 static const struct arm64_ftr_bits ftr_dczid[] = {
 312         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1),            /* DZP */
 313         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),       /* BS */
 314         ARM64_FTR_END,
 315 };
 316
 317
 318 static const struct arm64_ftr_bits ftr_id_isar5[] = {
 319         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
 320         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
 321         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
 322         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
 323         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
 324         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
 325         ARM64_FTR_END,
 326 };
 327
 328 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
 329         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* ac2 */
 330         ARM64_FTR_END,
 331 };
 332
 333 static const struct arm64_ftr_bits ftr_id_isar6[] = {
 334         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),
 335         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
 336         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),
 337         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
 338         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),
 339         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0),
 340         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0),
 341         ARM64_FTR_END,
 342 };
 343
 344 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
 345         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),               /* State3 */
 346         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),                /* State2 */
 347         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* State1 */
 348         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* State0 */
 349         ARM64_FTR_END,
 350 };
 351
 352 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
 353         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 354         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf),   /* PerfMon */
 355         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 356         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 357         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 358         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 359         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 360         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 361         ARM64_FTR_END,
 362 };
 363
 364 static const struct arm64_ftr_bits ftr_zcr[] = {
 365         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
 366                 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0),        /* LEN */
 367         ARM64_FTR_END,
 368 };
 369
 370 /*
 371  * Common ftr bits for a 32bit register with all hidden, strict
 372  * attributes, with 4bit feature fields and a default safe value of
 373  * 0. Covers the following 32bit registers:
 374  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 375  */
 376 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
 377         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 378         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 379         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 380         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 381         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 382         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 383         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 384         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 385         ARM64_FTR_END,
 386 };
 387
 388 /* Table for a single 32bit feature value */
 389 static const struct arm64_ftr_bits ftr_single32[] = {
 390         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
 391         ARM64_FTR_END,
 392 };
 393
 394 static const struct arm64_ftr_bits ftr_raz[] = {
 395         ARM64_FTR_END,
 396 };
 397
 398 #define ARM64_FTR_REG(id, table) {              \
 399         .sys_id = id,                           \
 400         .reg =  &(struct arm64_ftr_reg){        \
 401                 .name = #id,                    \
 402                 .ftr_bits = &((table)[0]),      \
 403         }}
 404
 405 static const struct __ftr_reg_entry {
 406         u32                     sys_id;
 407         struct arm64_ftr_reg    *reg;
 408 } arm64_ftr_regs[] = {
 409
 410         /* Op1 = 0, CRn = 0, CRm = 1 */
 411         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 412         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
 413         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
 414         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 415         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 416         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 417         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 418
 419         /* Op1 = 0, CRn = 0, CRm = 2 */
 420         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 421         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 422         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 423         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 424         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
 425         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 426         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 427         ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
 428
 429         /* Op1 = 0, CRn = 0, CRm = 3 */
 430         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 431         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 432         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 433
 434         /* Op1 = 0, CRn = 0, CRm = 4 */
 435         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 436         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
 437         ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
 438
 439         /* Op1 = 0, CRn = 0, CRm = 5 */
 440         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 441         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
 442
 443         /* Op1 = 0, CRn = 0, CRm = 6 */
 444         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 445         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
 446
 447         /* Op1 = 0, CRn = 0, CRm = 7 */
 448         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 449         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 450         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
 451
 452         /* Op1 = 0, CRn = 1, CRm = 2 */
 453         ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
 454
 455         /* Op1 = 3, CRn = 0, CRm = 0 */
 456         { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
 457         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 458
 459         /* Op1 = 3, CRn = 14, CRm = 0 */
 460         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
 461 };
 462
 463 static int search_cmp_ftr_reg(const void *id, const void *regp)
 464 {
 465         return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
 466 }
 467
 468 /*
 469  * get_arm64_ftr_reg - Lookup a feature register entry using its
 470  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 471  * ascending order of sys_id , we use binary search to find a matching
 472  * entry.
 473  *
 474  * returns - Upon success,  matching ftr_reg entry for id.
 475  *         - NULL on failure. It is upto the caller to decide
 476  *           the impact of a failure.
 477  */
 478 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 479 {
 480         const struct __ftr_reg_entry *ret;
 481
 482         ret = bsearch((const void *)(unsigned long)sys_id,
 483                         arm64_ftr_regs,
 484                         ARRAY_SIZE(arm64_ftr_regs),
 485                         sizeof(arm64_ftr_regs[0]),
 486                         search_cmp_ftr_reg);
 487         if (ret)
 488                 return ret->reg;
 489         return NULL;
 490 }
 491
 492 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
 493                                s64 ftr_val)
 494 {
 495         u64 mask = arm64_ftr_mask(ftrp);
 496
 497         reg &= ~mask;
 498         reg |= (ftr_val << ftrp->shift) & mask;
 499         return reg;
 500 }
 501
 502 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
 503                                 s64 cur)
 504 {
 505         s64 ret = 0;
 506
 507         switch (ftrp->type) {
 508         case FTR_EXACT:
 509                 ret = ftrp->safe_val;
 510                 break;
 511         case FTR_LOWER_SAFE:
 512                 ret = new < cur ? new : cur;
 513                 break;
 514         case FTR_HIGHER_OR_ZERO_SAFE:
 515                 if (!cur || !new)
 516                         break;
 517                 /* Fallthrough */
 518         case FTR_HIGHER_SAFE:
 519                 ret = new > cur ? new : cur;
 520                 break;
 521         default:
 522                 BUG();
 523         }
 524
 525         return ret;
 526 }
 527
 528 static void __init sort_ftr_regs(void)
 529 {
 530         int i;
 531
 532         /* Check that the array is sorted so that we can do the binary search */
 533         for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
 534                 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
 535 }
 536
 537 /*
 538  * Initialise the CPU feature register from Boot CPU values.
 539  * Also initiliases the strict_mask for the register.
 540  * Any bits that are not covered by an arm64_ftr_bits entry are considered
 541  * RES0 for the system-wide value, and must strictly match.
 542  */
 543 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 544 {
 545         u64 val = 0;
 546         u64 strict_mask = ~0x0ULL;
 547         u64 user_mask = 0;
 548         u64 valid_mask = 0;
 549
 550         const struct arm64_ftr_bits *ftrp;
 551         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 552
 553         BUG_ON(!reg);
 554
 555         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 556                 u64 ftr_mask = arm64_ftr_mask(ftrp);
 557                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 558
 559                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 560
 561                 valid_mask |= ftr_mask;
 562                 if (!ftrp->strict)
 563                         strict_mask &= ~ftr_mask;
 564                 if (ftrp->visible)
 565                         user_mask |= ftr_mask;
 566                 else
 567                         reg->user_val = arm64_ftr_set_value(ftrp,
 568                                                             reg->user_val,
 569                                                             ftrp->safe_val);
 570         }
 571
 572         val &= valid_mask;
 573
 574         reg->sys_val = val;
 575         reg->strict_mask = strict_mask;
 576         reg->user_mask = user_mask;
 577 }
 578
 579 extern const struct arm64_cpu_capabilities arm64_errata[];
 580 static const struct arm64_cpu_capabilities arm64_features[];
 581
 582 static void __init
 583 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
 584 {
 585         for (; caps->matches; caps++) {
 586                 if (WARN(caps->capability >= ARM64_NCAPS,
 587                         "Invalid capability %d\n", caps->capability))
 588                         continue;
 589                 if (WARN(cpu_hwcaps_ptrs[caps->capability],
 590                         "Duplicate entry for capability %d\n",
 591                         caps->capability))
 592                         continue;
 593                 cpu_hwcaps_ptrs[caps->capability] = caps;
 594         }
 595 }
 596
 597 static void __init init_cpu_hwcaps_indirect_list(void)
 598 {
 599         init_cpu_hwcaps_indirect_list_from_array(arm64_features);
 600         init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
 601 }
 602
 603 static void __init setup_boot_cpu_capabilities(void);
 604
 605 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 606 {
 607         /* Before we start using the tables, make sure it is sorted */
 608         sort_ftr_regs();
 609
 610         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 611         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 612         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 613         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 614         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 615         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 616         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 617         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 618         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 619         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
 620         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 621         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 622         init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
 623
 624         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 625                 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 626                 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 627                 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 628                 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 629                 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 630                 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 631                 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 632                 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6);
 633                 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 634                 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 635                 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 636                 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 637                 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 638                 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 639                 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 640                 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 641                 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 642         }
 643
 644         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 645                 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
 646                 sve_init_vq_map();
 647         }
 648
 649         /*
 650          * Initialize the indirect array of CPU hwcaps capabilities pointers
 651          * before we handle the boot CPU below.
 652          */
 653         init_cpu_hwcaps_indirect_list();
 654
 655         /*
 656          * Detect and enable early CPU capabilities based on the boot CPU,
 657          * after we have initialised the CPU feature infrastructure.
 658          */
 659         setup_boot_cpu_capabilities();
 660 }
 661
 662 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 663 {
 664         const struct arm64_ftr_bits *ftrp;
 665
 666         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 667                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 668                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 669
 670                 if (ftr_cur == ftr_new)
 671                         continue;
 672                 /* Find a safe value */
 673                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 674                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 675         }
 676
 677 }
 678
 679 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 680 {
 681         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 682
 683         BUG_ON(!regp);
 684         update_cpu_ftr_reg(regp, val);
 685         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 686                 return 0;
 687         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 688                         regp->name, boot, cpu, val);
 689         return 1;
 690 }
 691
 692 /*
 693  * Update system wide CPU feature registers with the values from a
 694  * non-boot CPU. Also performs SANITY checks to make sure that there
 695  * aren't any insane variations from that of the boot CPU.
 696  */
 697 void update_cpu_features(int cpu,
 698                          struct cpuinfo_arm64 *info,
 699                          struct cpuinfo_arm64 *boot)
 700 {
 701         int taint = 0;
 702
 703         /*
 704          * The kernel can handle differing I-cache policies, but otherwise
 705          * caches should look identical. Userspace JITs will make use of
 706          * *minLine.
 707          */
 708         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 709                                       info->reg_ctr, boot->reg_ctr);
 710
 711         /*
 712          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 713          * could result in too much or too little memory being zeroed if a
 714          * process is preempted and migrated between CPUs.
 715          */
 716         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 717                                       info->reg_dczid, boot->reg_dczid);
 718
 719         /* If different, timekeeping will be broken (especially with KVM) */
 720         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 721                                       info->reg_cntfrq, boot->reg_cntfrq);
 722
 723         /*
 724          * The kernel uses self-hosted debug features and expects CPUs to
 725          * support identical debug features. We presently need CTX_CMPs, WRPs,
 726          * and BRPs to be identical.
 727          * ID_AA64DFR1 is currently RES0.
 728          */
 729         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 730                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 731         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 732                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 733         /*
 734          * Even in big.LITTLE, processors should be identical instruction-set
 735          * wise.
 736          */
 737         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 738                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 739         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 740                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 741
 742         /*
 743          * Differing PARange support is fine as long as all peripherals and
 744          * memory are mapped within the minimum PARange of all CPUs.
 745          * Linux should not care about secure memory.
 746          */
 747         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 748                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 749         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 750                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 751         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
 752                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
 753
 754         /*
 755          * EL3 is not our concern.
 756          */
 757         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 758                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 759         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 760                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 761
 762         taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
 763                                       info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
 764
 765         /*
 766          * If we have AArch32, we care about 32-bit features for compat.
 767          * If the system doesn't support AArch32, don't update them.
 768          */
 769         if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 770                 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 771
 772                 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 773                                         info->reg_id_dfr0, boot->reg_id_dfr0);
 774                 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 775                                         info->reg_id_isar0, boot->reg_id_isar0);
 776                 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 777                                         info->reg_id_isar1, boot->reg_id_isar1);
 778                 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 779                                         info->reg_id_isar2, boot->reg_id_isar2);
 780                 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 781                                         info->reg_id_isar3, boot->reg_id_isar3);
 782                 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 783                                         info->reg_id_isar4, boot->reg_id_isar4);
 784                 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 785                                         info->reg_id_isar5, boot->reg_id_isar5);
 786                 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu,
 787                                         info->reg_id_isar6, boot->reg_id_isar6);
 788
 789                 /*
 790                  * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 791                  * ACTLR formats could differ across CPUs and therefore would have to
 792                  * be trapped for virtualization anyway.
 793                  */
 794                 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 795                                         info->reg_id_mmfr0, boot->reg_id_mmfr0);
 796                 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 797                                         info->reg_id_mmfr1, boot->reg_id_mmfr1);
 798                 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 799                                         info->reg_id_mmfr2, boot->reg_id_mmfr2);
 800                 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 801                                         info->reg_id_mmfr3, boot->reg_id_mmfr3);
 802                 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 803                                         info->reg_id_pfr0, boot->reg_id_pfr0);
 804                 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 805                                         info->reg_id_pfr1, boot->reg_id_pfr1);
 806                 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 807                                         info->reg_mvfr0, boot->reg_mvfr0);
 808                 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 809                                         info->reg_mvfr1, boot->reg_mvfr1);
 810                 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 811                                         info->reg_mvfr2, boot->reg_mvfr2);
 812         }
 813
 814         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 815                 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
 816                                         info->reg_zcr, boot->reg_zcr);
 817
 818                 /* Probe vector lengths, unless we already gave up on SVE */
 819                 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 820                     !system_capabilities_finalized())
 821                         sve_update_vq_map();
 822         }
 823
 824         /*
 825          * Mismatched CPU features are a recipe for disaster. Don't even
 826          * pretend to support them.
 827          */
 828         if (taint) {
 829                 pr_warn_once("Unsupported CPU feature variation detected.\n");
 830                 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
 831         }
 832 }
 833
 834 u64 read_sanitised_ftr_reg(u32 id)
 835 {
 836         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 837
 838         /* We shouldn't get a request for an unsupported register */
 839         BUG_ON(!regp);
 840         return regp->sys_val;
 841 }
 842
 843 #define read_sysreg_case(r)     \
 844         case r:         return read_sysreg_s(r)
 845
 846 /*
 847  * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
 848  * Read the system register on the current CPU
 849  */
 850 static u64 __read_sysreg_by_encoding(u32 sys_id)
 851 {
 852         switch (sys_id) {
 853         read_sysreg_case(SYS_ID_PFR0_EL1);
 854         read_sysreg_case(SYS_ID_PFR1_EL1);
 855         read_sysreg_case(SYS_ID_DFR0_EL1);
 856         read_sysreg_case(SYS_ID_MMFR0_EL1);
 857         read_sysreg_case(SYS_ID_MMFR1_EL1);
 858         read_sysreg_case(SYS_ID_MMFR2_EL1);
 859         read_sysreg_case(SYS_ID_MMFR3_EL1);
 860         read_sysreg_case(SYS_ID_ISAR0_EL1);
 861         read_sysreg_case(SYS_ID_ISAR1_EL1);
 862         read_sysreg_case(SYS_ID_ISAR2_EL1);
 863         read_sysreg_case(SYS_ID_ISAR3_EL1);
 864         read_sysreg_case(SYS_ID_ISAR4_EL1);
 865         read_sysreg_case(SYS_ID_ISAR5_EL1);
 866         read_sysreg_case(SYS_ID_ISAR6_EL1);
 867         read_sysreg_case(SYS_MVFR0_EL1);
 868         read_sysreg_case(SYS_MVFR1_EL1);
 869         read_sysreg_case(SYS_MVFR2_EL1);
 870
 871         read_sysreg_case(SYS_ID_AA64PFR0_EL1);
 872         read_sysreg_case(SYS_ID_AA64PFR1_EL1);
 873         read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
 874         read_sysreg_case(SYS_ID_AA64DFR0_EL1);
 875         read_sysreg_case(SYS_ID_AA64DFR1_EL1);
 876         read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
 877         read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
 878         read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
 879         read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
 880         read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
 881
 882         read_sysreg_case(SYS_CNTFRQ_EL0);
 883         read_sysreg_case(SYS_CTR_EL0);
 884         read_sysreg_case(SYS_DCZID_EL0);
 885
 886         default:
 887                 BUG();
 888                 return 0;
 889         }
 890 }
 891
 892 #include <linux/irqchip/arm-gic-v3.h>
 893
 894 static bool
 895 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
 896 {
 897         int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
 898
 899         return val >= entry->min_field_value;
 900 }
 901
 902 static bool
 903 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
 904 {
 905         u64 val;
 906
 907         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
 908         if (scope == SCOPE_SYSTEM)
 909                 val = read_sanitised_ftr_reg(entry->sys_reg);
 910         else
 911                 val = __read_sysreg_by_encoding(entry->sys_reg);
 912
 913         return feature_matches(val, entry);
 914 }
 915
 916 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
 917 {
 918         bool has_sre;
 919
 920         if (!has_cpuid_feature(entry, scope))
 921                 return false;
 922
 923         has_sre = gic_enable_sre();
 924         if (!has_sre)
 925                 pr_warn_once("%s present but disabled by higher exception level\n",
 926                              entry->desc);
 927
 928         return has_sre;
 929 }
 930
 931 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
 932 {
 933         u32 midr = read_cpuid_id();
 934
 935         /* Cavium ThunderX pass 1.x and 2.x */
 936         return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
 937                 MIDR_CPU_VAR_REV(0, 0),
 938                 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
 939 }
 940
 941 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
 942 {
 943         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
 944
 945         return cpuid_feature_extract_signed_field(pfr0,
 946                                         ID_AA64PFR0_FP_SHIFT) < 0;
 947 }
 948
 949 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
 950                           int scope)
 951 {
 952         u64 ctr;
 953
 954         if (scope == SCOPE_SYSTEM)
 955                 ctr = arm64_ftr_reg_ctrel0.sys_val;
 956         else
 957                 ctr = read_cpuid_effective_cachetype();
 958
 959         return ctr & BIT(CTR_IDC_SHIFT);
 960 }
 961
 962 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
 963 {
 964         /*
 965          * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
 966          * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
 967          * to the CTR_EL0 on this CPU and emulate it with the real/safe
 968          * value.
 969          */
 970         if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
 971                 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
 972 }
 973
 974 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
 975                           int scope)
 976 {
 977         u64 ctr;
 978
 979         if (scope == SCOPE_SYSTEM)
 980                 ctr = arm64_ftr_reg_ctrel0.sys_val;
 981         else
 982                 ctr = read_cpuid_cachetype();
 983
 984         return ctr & BIT(CTR_DIC_SHIFT);
 985 }
 986
 987 static bool __maybe_unused
 988 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
 989 {
 990         /*
 991          * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
 992          * may share TLB entries with a CPU stuck in the crashed
 993          * kernel.
 994          */
 995          if (is_kdump_kernel())
 996                 return false;
 997
 998         return has_cpuid_feature(entry, scope);
 999 }
1000
1001 /*
1002  * This check is triggered during the early boot before the cpufeature
1003  * is initialised. Checking the status on the local CPU allows the boot
1004  * CPU to detect the need for non-global mappings and thus avoiding a
1005  * pagetable re-write after all the CPUs are booted. This check will be
1006  * anyway run on individual CPUs, allowing us to get the consistent
1007  * state once the SMP CPUs are up and thus make the switch to non-global
1008  * mappings if required.
1009  */
1010 bool kaslr_requires_kpti(void)
1011 {
1012         if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE))
1013                 return false;
1014
1015         /*
1016          * E0PD does a similar job to KPTI so can be used instead
1017          * where available.
1018          */
1019         if (IS_ENABLED(CONFIG_ARM64_E0PD)) {
1020                 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1);
1021                 if (cpuid_feature_extract_unsigned_field(mmfr2,
1022                                                 ID_AA64MMFR2_E0PD_SHIFT))
1023                         return false;
1024         }
1025
1026         /*
1027          * Systems affected by Cavium erratum 24756 are incompatible
1028          * with KPTI.
1029          */
1030         if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) {
1031                 extern const struct midr_range cavium_erratum_27456_cpus[];
1032
1033                 if (is_midr_in_range_list(read_cpuid_id(),
1034                                           cavium_erratum_27456_cpus))
1035                         return false;
1036         }
1037
1038         return kaslr_offset() > 0;
1039 }
1040
1041 static bool __meltdown_safe = true;
1042 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
1043
1044 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
1045                                 int scope)
1046 {
1047         /* List of CPUs that are not vulnerable and don't need KPTI */
1048         static const struct midr_range kpti_safe_list[] = {
1049                 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
1050                 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
1051                 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
1052                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
1053                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
1054                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1055                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
1056                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
1057                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
1058                 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
1059                 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
1060                 { /* sentinel */ }
1061         };
1062         char const *str = "kpti command line option";
1063         bool meltdown_safe;
1064
1065         meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
1066
1067         /* Defer to CPU feature registers */
1068         if (has_cpuid_feature(entry, scope))
1069                 meltdown_safe = true;
1070
1071         if (!meltdown_safe)
1072                 __meltdown_safe = false;
1073
1074         /*
1075          * For reasons that aren't entirely clear, enabling KPTI on Cavium
1076          * ThunderX leads to apparent I-cache corruption of kernel text, which
1077          * ends as well as you might imagine. Don't even try.
1078          */
1079         if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1080                 str = "ARM64_WORKAROUND_CAVIUM_27456";
1081                 __kpti_forced = -1;
1082         }
1083
1084         /* Useful for KASLR robustness */
1085         if (kaslr_requires_kpti()) {
1086                 if (!__kpti_forced) {
1087                         str = "KASLR";
1088                         __kpti_forced = 1;
1089                 }
1090         }
1091
1092         if (cpu_mitigations_off() && !__kpti_forced) {
1093                 str = "mitigations=off";
1094                 __kpti_forced = -1;
1095         }
1096
1097         if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1098                 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1099                 return false;
1100         }
1101
1102         /* Forced? */
1103         if (__kpti_forced) {
1104                 pr_info_once("kernel page table isolation forced %s by %s\n",
1105                              __kpti_forced > 0 ? "ON" : "OFF", str);
1106                 return __kpti_forced > 0;
1107         }
1108
1109         return !meltdown_safe;
1110 }
1111
1112 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1113 static void
1114 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1115 {
1116         typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1117         extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1118         kpti_remap_fn *remap_fn;
1119
1120         int cpu = smp_processor_id();
1121
1122         /*
1123          * We don't need to rewrite the page-tables if either we've done
1124          * it already or we have KASLR enabled and therefore have not
1125          * created any global mappings at all.
1126          */
1127         if (arm64_use_ng_mappings)
1128                 return;
1129
1130         remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
1131
1132         cpu_install_idmap();
1133         remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1134         cpu_uninstall_idmap();
1135
1136         if (!cpu)
1137                 arm64_use_ng_mappings = true;
1138
1139         return;
1140 }
1141 #else
1142 static void
1143 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1144 {
1145 }
1146 #endif  /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1147
1148 static int __init parse_kpti(char *str)
1149 {
1150         bool enabled;
1151         int ret = strtobool(str, &enabled);
1152
1153         if (ret)
1154                 return ret;
1155
1156         __kpti_forced = enabled ? 1 : -1;
1157         return 0;
1158 }
1159 early_param("kpti", parse_kpti);
1160
1161 #ifdef CONFIG_ARM64_HW_AFDBM
1162 static inline void __cpu_enable_hw_dbm(void)
1163 {
1164         u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1165
1166         write_sysreg(tcr, tcr_el1);
1167         isb();
1168 }
1169
1170 static bool cpu_has_broken_dbm(void)
1171 {
1172         /* List of CPUs which have broken DBM support. */
1173         static const struct midr_range cpus[] = {
1174 #ifdef CONFIG_ARM64_ERRATUM_1024718
1175                 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0),  // A55 r0p0 -r1p0
1176 #endif
1177                 {},
1178         };
1179
1180         return is_midr_in_range_list(read_cpuid_id(), cpus);
1181 }
1182
1183 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1184 {
1185         return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1186                !cpu_has_broken_dbm();
1187 }
1188
1189 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1190 {
1191         if (cpu_can_use_dbm(cap))
1192                 __cpu_enable_hw_dbm();
1193 }
1194
1195 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1196                        int __unused)
1197 {
1198         static bool detected = false;
1199         /*
1200          * DBM is a non-conflicting feature. i.e, the kernel can safely
1201          * run a mix of CPUs with and without the feature. So, we
1202          * unconditionally enable the capability to allow any late CPU
1203          * to use the feature. We only enable the control bits on the
1204          * CPU, if it actually supports.
1205          *
1206          * We have to make sure we print the "feature" detection only
1207          * when at least one CPU actually uses it. So check if this CPU
1208          * can actually use it and print the message exactly once.
1209          *
1210          * This is safe as all CPUs (including secondary CPUs - due to the
1211          * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1212          * goes through the "matches" check exactly once. Also if a CPU
1213          * matches the criteria, it is guaranteed that the CPU will turn
1214          * the DBM on, as the capability is unconditionally enabled.
1215          */
1216         if (!detected && cpu_can_use_dbm(cap)) {
1217                 detected = true;
1218                 pr_info("detected: Hardware dirty bit management\n");
1219         }
1220
1221         return true;
1222 }
1223
1224 #endif
1225
1226 #ifdef CONFIG_ARM64_AMU_EXTN
1227
1228 /*
1229  * The "amu_cpus" cpumask only signals that the CPU implementation for the
1230  * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide
1231  * information regarding all the events that it supports. When a CPU bit is
1232  * set in the cpumask, the user of this feature can only rely on the presence
1233  * of the 4 fixed counters for that CPU. But this does not guarantee that the
1234  * counters are enabled or access to these counters is enabled by code
1235  * executed at higher exception levels (firmware).
1236  */
1237 static struct cpumask amu_cpus __read_mostly;
1238
1239 bool cpu_has_amu_feat(int cpu)
1240 {
1241         return cpumask_test_cpu(cpu, &amu_cpus);
1242 }
1243
1244 /* Initialize the use of AMU counters for frequency invariance */
1245 extern void init_cpu_freq_invariance_counters(void);
1246
1247 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
1248 {
1249         if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) {
1250                 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n",
1251                         smp_processor_id());
1252                 cpumask_set_cpu(smp_processor_id(), &amu_cpus);
1253                 init_cpu_freq_invariance_counters();
1254         }
1255 }
1256
1257 static bool has_amu(const struct arm64_cpu_capabilities *cap,
1258                     int __unused)
1259 {
1260         /*
1261          * The AMU extension is a non-conflicting feature: the kernel can
1262          * safely run a mix of CPUs with and without support for the
1263          * activity monitors extension. Therefore, unconditionally enable
1264          * the capability to allow any late CPU to use the feature.
1265          *
1266          * With this feature unconditionally enabled, the cpu_enable
1267          * function will be called for all CPUs that match the criteria,
1268          * including secondary and hotplugged, marking this feature as
1269          * present on that respective CPU. The enable function will also
1270          * print a detection message.
1271          */
1272
1273         return true;
1274 }
1275 #endif
1276
1277 #ifdef CONFIG_ARM64_VHE
1278 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1279 {
1280         return is_kernel_in_hyp_mode();
1281 }
1282
1283 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1284 {
1285         /*
1286          * Copy register values that aren't redirected by hardware.
1287          *
1288          * Before code patching, we only set tpidr_el1, all CPUs need to copy
1289          * this value to tpidr_el2 before we patch the code. Once we've done
1290          * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1291          * do anything here.
1292          */
1293         if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1294                 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1295 }
1296 #endif
1297
1298 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1299 {
1300         u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1301
1302         /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1303         WARN_ON(val & (7 << 27 | 7 << 21));
1304 }
1305
1306 #ifdef CONFIG_ARM64_SSBD
1307 static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
1308 {
1309         if (user_mode(regs))
1310                 return 1;
1311
1312         if (instr & BIT(PSTATE_Imm_shift))
1313                 regs->pstate |= PSR_SSBS_BIT;
1314         else
1315                 regs->pstate &= ~PSR_SSBS_BIT;
1316
1317         arm64_skip_faulting_instruction(regs, 4);
1318         return 0;
1319 }
1320
1321 static struct undef_hook ssbs_emulation_hook = {
1322         .instr_mask     = ~(1U << PSTATE_Imm_shift),
1323         .instr_val      = 0xd500401f | PSTATE_SSBS,
1324         .fn             = ssbs_emulation_handler,
1325 };
1326
1327 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
1328 {
1329         static bool undef_hook_registered = false;
1330         static DEFINE_RAW_SPINLOCK(hook_lock);
1331
1332         raw_spin_lock(&hook_lock);
1333         if (!undef_hook_registered) {
1334                 register_undef_hook(&ssbs_emulation_hook);
1335                 undef_hook_registered = true;
1336         }
1337         raw_spin_unlock(&hook_lock);
1338
1339         if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
1340                 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
1341                 arm64_set_ssbd_mitigation(false);
1342         } else {
1343                 arm64_set_ssbd_mitigation(true);
1344         }
1345 }
1346 #endif /* CONFIG_ARM64_SSBD */
1347
1348 #ifdef CONFIG_ARM64_PAN
1349 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1350 {
1351         /*
1352          * We modify PSTATE. This won't work from irq context as the PSTATE
1353          * is discarded once we return from the exception.
1354          */
1355         WARN_ON_ONCE(in_interrupt());
1356
1357         sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1358         asm(SET_PSTATE_PAN(1));
1359 }
1360 #endif /* CONFIG_ARM64_PAN */
1361
1362 #ifdef CONFIG_ARM64_RAS_EXTN
1363 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1364 {
1365         /* Firmware may have left a deferred SError in this register. */
1366         write_sysreg_s(0, SYS_DISR_EL1);
1367 }
1368 #endif /* CONFIG_ARM64_RAS_EXTN */
1369
1370 #ifdef CONFIG_ARM64_PTR_AUTH
1371 static void cpu_enable_address_auth(struct arm64_cpu_capabilities const *cap)
1372 {
1373         sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ENIA | SCTLR_ELx_ENIB |
1374                                        SCTLR_ELx_ENDA | SCTLR_ELx_ENDB);
1375 }
1376 #endif /* CONFIG_ARM64_PTR_AUTH */
1377
1378 #ifdef CONFIG_ARM64_E0PD
1379 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
1380 {
1381         if (this_cpu_has_cap(ARM64_HAS_E0PD))
1382                 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
1383 }
1384 #endif /* CONFIG_ARM64_E0PD */
1385
1386 #ifdef CONFIG_ARM64_PSEUDO_NMI
1387 static bool enable_pseudo_nmi;
1388
1389 static int __init early_enable_pseudo_nmi(char *p)
1390 {
1391         return strtobool(p, &enable_pseudo_nmi);
1392 }
1393 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1394
1395 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1396                                    int scope)
1397 {
1398         return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
1399 }
1400 #endif
1401
1402 static const struct arm64_cpu_capabilities arm64_features[] = {
1403         {
1404                 .desc = "GIC system register CPU interface",
1405                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1406                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1407                 .matches = has_useable_gicv3_cpuif,
1408                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1409                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1410                 .sign = FTR_UNSIGNED,
1411                 .min_field_value = 1,
1412         },
1413 #ifdef CONFIG_ARM64_PAN
1414         {
1415                 .desc = "Privileged Access Never",
1416                 .capability = ARM64_HAS_PAN,
1417                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1418                 .matches = has_cpuid_feature,
1419                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1420                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1421                 .sign = FTR_UNSIGNED,
1422                 .min_field_value = 1,
1423                 .cpu_enable = cpu_enable_pan,
1424         },
1425 #endif /* CONFIG_ARM64_PAN */
1426 #ifdef CONFIG_ARM64_LSE_ATOMICS
1427         {
1428                 .desc = "LSE atomic instructions",
1429                 .capability = ARM64_HAS_LSE_ATOMICS,
1430                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1431                 .matches = has_cpuid_feature,
1432                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1433                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1434                 .sign = FTR_UNSIGNED,
1435                 .min_field_value = 2,
1436         },
1437 #endif /* CONFIG_ARM64_LSE_ATOMICS */
1438         {
1439                 .desc = "Software prefetching using PRFM",
1440                 .capability = ARM64_HAS_NO_HW_PREFETCH,
1441                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1442                 .matches = has_no_hw_prefetch,
1443         },
1444 #ifdef CONFIG_ARM64_UAO
1445         {
1446                 .desc = "User Access Override",
1447                 .capability = ARM64_HAS_UAO,
1448                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1449                 .matches = has_cpuid_feature,
1450                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1451                 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1452                 .min_field_value = 1,
1453                 /*
1454                  * We rely on stop_machine() calling uao_thread_switch() to set
1455                  * UAO immediately after patching.
1456                  */
1457         },
1458 #endif /* CONFIG_ARM64_UAO */
1459 #ifdef CONFIG_ARM64_PAN
1460         {
1461                 .capability = ARM64_ALT_PAN_NOT_UAO,
1462                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1463                 .matches = cpufeature_pan_not_uao,
1464         },
1465 #endif /* CONFIG_ARM64_PAN */
1466 #ifdef CONFIG_ARM64_VHE
1467         {
1468                 .desc = "Virtualization Host Extensions",
1469                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1470                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1471                 .matches = runs_at_el2,
1472                 .cpu_enable = cpu_copy_el2regs,
1473         },
1474 #endif  /* CONFIG_ARM64_VHE */
1475         {
1476                 .desc = "32-bit EL0 Support",
1477                 .capability = ARM64_HAS_32BIT_EL0,
1478                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1479                 .matches = has_cpuid_feature,
1480                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1481                 .sign = FTR_UNSIGNED,
1482                 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1483                 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1484         },
1485         {
1486                 .desc = "Kernel page table isolation (KPTI)",
1487                 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1488                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1489                 /*
1490                  * The ID feature fields below are used to indicate that
1491                  * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1492                  * more details.
1493                  */
1494                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1495                 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1496                 .min_field_value = 1,
1497                 .matches = unmap_kernel_at_el0,
1498                 .cpu_enable = kpti_install_ng_mappings,
1499         },
1500         {
1501                 /* FP/SIMD is not implemented */
1502                 .capability = ARM64_HAS_NO_FPSIMD,
1503                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1504                 .min_field_value = 0,
1505                 .matches = has_no_fpsimd,
1506         },
1507 #ifdef CONFIG_ARM64_PMEM
1508         {
1509                 .desc = "Data cache clean to Point of Persistence",
1510                 .capability = ARM64_HAS_DCPOP,
1511                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1512                 .matches = has_cpuid_feature,
1513                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1514                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1515                 .min_field_value = 1,
1516         },
1517         {
1518                 .desc = "Data cache clean to Point of Deep Persistence",
1519                 .capability = ARM64_HAS_DCPODP,
1520                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1521                 .matches = has_cpuid_feature,
1522                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1523                 .sign = FTR_UNSIGNED,
1524                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1525                 .min_field_value = 2,
1526         },
1527 #endif
1528 #ifdef CONFIG_ARM64_SVE
1529         {
1530                 .desc = "Scalable Vector Extension",
1531                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1532                 .capability = ARM64_SVE,
1533                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1534                 .sign = FTR_UNSIGNED,
1535                 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1536                 .min_field_value = ID_AA64PFR0_SVE,
1537                 .matches = has_cpuid_feature,
1538                 .cpu_enable = sve_kernel_enable,
1539         },
1540 #endif /* CONFIG_ARM64_SVE */
1541 #ifdef CONFIG_ARM64_RAS_EXTN
1542         {
1543                 .desc = "RAS Extension Support",
1544                 .capability = ARM64_HAS_RAS_EXTN,
1545                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1546                 .matches = has_cpuid_feature,
1547                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1548                 .sign = FTR_UNSIGNED,
1549                 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1550                 .min_field_value = ID_AA64PFR0_RAS_V1,
1551                 .cpu_enable = cpu_clear_disr,
1552         },
1553 #endif /* CONFIG_ARM64_RAS_EXTN */
1554 #ifdef CONFIG_ARM64_AMU_EXTN
1555         {
1556                 /*
1557                  * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y.
1558                  * Therefore, don't provide .desc as we don't want the detection
1559                  * message to be shown until at least one CPU is detected to
1560                  * support the feature.
1561                  */
1562                 .capability = ARM64_HAS_AMU_EXTN,
1563                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1564                 .matches = has_amu,
1565                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1566                 .sign = FTR_UNSIGNED,
1567                 .field_pos = ID_AA64PFR0_AMU_SHIFT,
1568                 .min_field_value = ID_AA64PFR0_AMU,
1569                 .cpu_enable = cpu_amu_enable,
1570         },
1571 #endif /* CONFIG_ARM64_AMU_EXTN */
1572         {
1573                 .desc = "Data cache clean to the PoU not required for I/D coherence",
1574                 .capability = ARM64_HAS_CACHE_IDC,
1575                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1576                 .matches = has_cache_idc,
1577                 .cpu_enable = cpu_emulate_effective_ctr,
1578         },
1579         {
1580                 .desc = "Instruction cache invalidation not required for I/D coherence",
1581                 .capability = ARM64_HAS_CACHE_DIC,
1582                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1583                 .matches = has_cache_dic,
1584         },
1585         {
1586                 .desc = "Stage-2 Force Write-Back",
1587                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1588                 .capability = ARM64_HAS_STAGE2_FWB,
1589                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1590                 .sign = FTR_UNSIGNED,
1591                 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
1592                 .min_field_value = 1,
1593                 .matches = has_cpuid_feature,
1594                 .cpu_enable = cpu_has_fwb,
1595         },
1596 #ifdef CONFIG_ARM64_HW_AFDBM
1597         {
1598                 /*
1599                  * Since we turn this on always, we don't want the user to
1600                  * think that the feature is available when it may not be.
1601                  * So hide the description.
1602                  *
1603                  * .desc = "Hardware pagetable Dirty Bit Management",
1604                  *
1605                  */
1606                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1607                 .capability = ARM64_HW_DBM,
1608                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1609                 .sign = FTR_UNSIGNED,
1610                 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
1611                 .min_field_value = 2,
1612                 .matches = has_hw_dbm,
1613                 .cpu_enable = cpu_enable_hw_dbm,
1614         },
1615 #endif
1616         {
1617                 .desc = "CRC32 instructions",
1618                 .capability = ARM64_HAS_CRC32,
1619                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1620                 .matches = has_cpuid_feature,
1621                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1622                 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
1623                 .min_field_value = 1,
1624         },
1625 #ifdef CONFIG_ARM64_SSBD
1626         {
1627                 .desc = "Speculative Store Bypassing Safe (SSBS)",
1628                 .capability = ARM64_SSBS,
1629                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1630                 .matches = has_cpuid_feature,
1631                 .sys_reg = SYS_ID_AA64PFR1_EL1,
1632                 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
1633                 .sign = FTR_UNSIGNED,
1634                 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
1635                 .cpu_enable = cpu_enable_ssbs,
1636         },
1637 #endif
1638 #ifdef CONFIG_ARM64_CNP
1639         {
1640                 .desc = "Common not Private translations",
1641                 .capability = ARM64_HAS_CNP,
1642                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1643                 .matches = has_useable_cnp,
1644                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1645                 .sign = FTR_UNSIGNED,
1646                 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
1647                 .min_field_value = 1,
1648                 .cpu_enable = cpu_enable_cnp,
1649         },
1650 #endif
1651         {
1652                 .desc = "Speculation barrier (SB)",
1653                 .capability = ARM64_HAS_SB,
1654                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1655                 .matches = has_cpuid_feature,
1656                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1657                 .field_pos = ID_AA64ISAR1_SB_SHIFT,
1658                 .sign = FTR_UNSIGNED,
1659                 .min_field_value = 1,
1660         },
1661 #ifdef CONFIG_ARM64_PTR_AUTH
1662         {
1663                 .desc = "Address authentication (architected algorithm)",
1664                 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
1665                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1666                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1667                 .sign = FTR_UNSIGNED,
1668                 .field_pos = ID_AA64ISAR1_APA_SHIFT,
1669                 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
1670                 .matches = has_cpuid_feature,
1671                 .cpu_enable = cpu_enable_address_auth,
1672         },
1673         {
1674                 .desc = "Address authentication (IMP DEF algorithm)",
1675                 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
1676                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1677                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1678                 .sign = FTR_UNSIGNED,
1679                 .field_pos = ID_AA64ISAR1_API_SHIFT,
1680                 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
1681                 .matches = has_cpuid_feature,
1682                 .cpu_enable = cpu_enable_address_auth,
1683         },
1684         {
1685                 .desc = "Generic authentication (architected algorithm)",
1686                 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
1687                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1688                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1689                 .sign = FTR_UNSIGNED,
1690                 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
1691                 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
1692                 .matches = has_cpuid_feature,
1693         },
1694         {
1695                 .desc = "Generic authentication (IMP DEF algorithm)",
1696                 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
1697                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1698                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1699                 .sign = FTR_UNSIGNED,
1700                 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
1701                 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
1702                 .matches = has_cpuid_feature,
1703         },
1704 #endif /* CONFIG_ARM64_PTR_AUTH */
1705 #ifdef CONFIG_ARM64_PSEUDO_NMI
1706         {
1707                 /*
1708                  * Depends on having GICv3
1709                  */
1710                 .desc = "IRQ priority masking",
1711                 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
1712                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1713                 .matches = can_use_gic_priorities,
1714                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1715                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1716                 .sign = FTR_UNSIGNED,
1717                 .min_field_value = 1,
1718         },
1719 #endif
1720 #ifdef CONFIG_ARM64_E0PD
1721         {
1722                 .desc = "E0PD",
1723                 .capability = ARM64_HAS_E0PD,
1724                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1725                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1726                 .sign = FTR_UNSIGNED,
1727                 .field_pos = ID_AA64MMFR2_E0PD_SHIFT,
1728                 .matches = has_cpuid_feature,
1729                 .min_field_value = 1,
1730                 .cpu_enable = cpu_enable_e0pd,
1731         },
1732 #endif
1733 #ifdef CONFIG_ARCH_RANDOM
1734         {
1735                 .desc = "Random Number Generator",
1736                 .capability = ARM64_HAS_RNG,
1737                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1738                 .matches = has_cpuid_feature,
1739                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1740                 .field_pos = ID_AA64ISAR0_RNDR_SHIFT,
1741                 .sign = FTR_UNSIGNED,
1742                 .min_field_value = 1,
1743         },
1744 #endif
1745         {},
1746 };
1747
1748 #define HWCAP_CPUID_MATCH(reg, field, s, min_value)                             \
1749                 .matches = has_cpuid_feature,                                   \
1750                 .sys_reg = reg,                                                 \
1751                 .field_pos = field,                                             \
1752                 .sign = s,                                                      \
1753                 .min_field_value = min_value,
1754
1755 #define __HWCAP_CAP(name, cap_type, cap)                                        \
1756                 .desc = name,                                                   \
1757                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,                            \
1758                 .hwcap_type = cap_type,                                         \
1759                 .hwcap = cap,                                                   \
1760
1761 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap)                      \
1762         {                                                                       \
1763                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1764                 HWCAP_CPUID_MATCH(reg, field, s, min_value)                     \
1765         }
1766
1767 #define HWCAP_MULTI_CAP(list, cap_type, cap)                                    \
1768         {                                                                       \
1769                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1770                 .matches = cpucap_multi_entry_cap_matches,                      \
1771                 .match_list = list,                                             \
1772         }
1773
1774 #define HWCAP_CAP_MATCH(match, cap_type, cap)                                   \
1775         {                                                                       \
1776                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1777                 .matches = match,                                               \
1778         }
1779
1780 #ifdef CONFIG_ARM64_PTR_AUTH
1781 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
1782         {
1783                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
1784                                   FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
1785         },
1786         {
1787                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
1788                                   FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
1789         },
1790         {},
1791 };
1792
1793 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
1794         {
1795                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
1796                                   FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
1797         },
1798         {
1799                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
1800                                   FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
1801         },
1802         {},
1803 };
1804 #endif
1805
1806 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
1807         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
1808         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
1809         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
1810         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
1811         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
1812         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
1813         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
1814         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
1815         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
1816         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
1817         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
1818         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
1819         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
1820         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
1821         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
1822         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG),
1823         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
1824         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
1825         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
1826         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
1827         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
1828         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
1829         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
1830         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
1831         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
1832         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
1833         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
1834         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
1835         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
1836         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16),
1837         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH),
1838         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM),
1839         HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
1840 #ifdef CONFIG_ARM64_SVE
1841         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
1842         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
1843         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
1844         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
1845         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
1846         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
1847         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
1848         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
1849         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
1850         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
1851         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
1852 #endif
1853         HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
1854 #ifdef CONFIG_ARM64_PTR_AUTH
1855         HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
1856         HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
1857 #endif
1858         {},
1859 };
1860
1861 #ifdef CONFIG_COMPAT
1862 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
1863 {
1864         /*
1865          * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
1866          * in line with that of arm32 as in vfp_init(). We make sure that the
1867          * check is future proof, by making sure value is non-zero.
1868          */
1869         u32 mvfr1;
1870
1871         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1872         if (scope == SCOPE_SYSTEM)
1873                 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
1874         else
1875                 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
1876
1877         return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
1878                 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
1879                 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
1880 }
1881 #endif
1882
1883 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
1884 #ifdef CONFIG_COMPAT
1885         HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
1886         HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
1887         /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
1888         HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
1889         HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
1890         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1891         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1892         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1893         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1894         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
1895 #endif
1896         {},
1897 };
1898
1899 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1900 {
1901         switch (cap->hwcap_type) {
1902         case CAP_HWCAP:
1903                 cpu_set_feature(cap->hwcap);
1904                 break;
1905 #ifdef CONFIG_COMPAT
1906         case CAP_COMPAT_HWCAP:
1907                 compat_elf_hwcap |= (u32)cap->hwcap;
1908                 break;
1909         case CAP_COMPAT_HWCAP2:
1910                 compat_elf_hwcap2 |= (u32)cap->hwcap;
1911                 break;
1912 #endif
1913         default:
1914                 WARN_ON(1);
1915                 break;
1916         }
1917 }
1918
1919 /* Check if we have a particular HWCAP enabled */
1920 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1921 {
1922         bool rc;
1923
1924         switch (cap->hwcap_type) {
1925         case CAP_HWCAP:
1926                 rc = cpu_have_feature(cap->hwcap);
1927                 break;
1928 #ifdef CONFIG_COMPAT
1929         case CAP_COMPAT_HWCAP:
1930                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1931                 break;
1932         case CAP_COMPAT_HWCAP2:
1933                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1934                 break;
1935 #endif
1936         default:
1937                 WARN_ON(1);
1938                 rc = false;
1939         }
1940
1941         return rc;
1942 }
1943
1944 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
1945 {
1946         /* We support emulation of accesses to CPU ID feature registers */
1947         cpu_set_named_feature(CPUID);
1948         for (; hwcaps->matches; hwcaps++)
1949                 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
1950                         cap_set_elf_hwcap(hwcaps);
1951 }
1952
1953 static void update_cpu_capabilities(u16 scope_mask)
1954 {
1955         int i;
1956         const struct arm64_cpu_capabilities *caps;
1957
1958         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1959         for (i = 0; i < ARM64_NCAPS; i++) {
1960                 caps = cpu_hwcaps_ptrs[i];
1961                 if (!caps || !(caps->type & scope_mask) ||
1962                     cpus_have_cap(caps->capability) ||
1963                     !caps->matches(caps, cpucap_default_scope(caps)))
1964                         continue;
1965
1966                 if (caps->desc)
1967                         pr_info("detected: %s\n", caps->desc);
1968                 cpus_set_cap(caps->capability);
1969
1970                 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
1971                         set_bit(caps->capability, boot_capabilities);
1972         }
1973 }
1974
1975 /*
1976  * Enable all the available capabilities on this CPU. The capabilities
1977  * with BOOT_CPU scope are handled separately and hence skipped here.
1978  */
1979 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
1980 {
1981         int i;
1982         u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
1983
1984         for_each_available_cap(i) {
1985                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
1986
1987                 if (WARN_ON(!cap))
1988                         continue;
1989
1990                 if (!(cap->type & non_boot_scope))
1991                         continue;
1992
1993                 if (cap->cpu_enable)
1994                         cap->cpu_enable(cap);
1995         }
1996         return 0;
1997 }
1998
1999 /*
2000  * Run through the enabled capabilities and enable() it on all active
2001  * CPUs
2002  */
2003 static void __init enable_cpu_capabilities(u16 scope_mask)
2004 {
2005         int i;
2006         const struct arm64_cpu_capabilities *caps;
2007         bool boot_scope;
2008
2009         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2010         boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
2011
2012         for (i = 0; i < ARM64_NCAPS; i++) {
2013                 unsigned int num;
2014
2015                 caps = cpu_hwcaps_ptrs[i];
2016                 if (!caps || !(caps->type & scope_mask))
2017                         continue;
2018                 num = caps->capability;
2019                 if (!cpus_have_cap(num))
2020                         continue;
2021
2022                 /* Ensure cpus_have_const_cap(num) works */
2023                 static_branch_enable(&cpu_hwcap_keys[num]);
2024
2025                 if (boot_scope && caps->cpu_enable)
2026                         /*
2027                          * Capabilities with SCOPE_BOOT_CPU scope are finalised
2028                          * before any secondary CPU boots. Thus, each secondary
2029                          * will enable the capability as appropriate via
2030                          * check_local_cpu_capabilities(). The only exception is
2031                          * the boot CPU, for which the capability must be
2032                          * enabled here. This approach avoids costly
2033                          * stop_machine() calls for this case.
2034                          */
2035                         caps->cpu_enable(caps);
2036         }
2037
2038         /*
2039          * For all non-boot scope capabilities, use stop_machine()
2040          * as it schedules the work allowing us to modify PSTATE,
2041          * instead of on_each_cpu() which uses an IPI, giving us a
2042          * PSTATE that disappears when we return.
2043          */
2044         if (!boot_scope)
2045                 stop_machine(cpu_enable_non_boot_scope_capabilities,
2046                              NULL, cpu_online_mask);
2047 }
2048
2049 /*
2050  * Run through the list of capabilities to check for conflicts.
2051  * If the system has already detected a capability, take necessary
2052  * action on this CPU.
2053  *
2054  * Returns "false" on conflicts.
2055  */
2056 static bool verify_local_cpu_caps(u16 scope_mask)
2057 {
2058         int i;
2059         bool cpu_has_cap, system_has_cap;
2060         const struct arm64_cpu_capabilities *caps;
2061
2062         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2063
2064         for (i = 0; i < ARM64_NCAPS; i++) {
2065                 caps = cpu_hwcaps_ptrs[i];
2066                 if (!caps || !(caps->type & scope_mask))
2067                         continue;
2068
2069                 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
2070                 system_has_cap = cpus_have_cap(caps->capability);
2071
2072                 if (system_has_cap) {
2073                         /*
2074                          * Check if the new CPU misses an advertised feature,
2075                          * which is not safe to miss.
2076                          */
2077                         if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
2078                                 break;
2079                         /*
2080                          * We have to issue cpu_enable() irrespective of
2081                          * whether the CPU has it or not, as it is enabeld
2082                          * system wide. It is upto the call back to take
2083                          * appropriate action on this CPU.
2084                          */
2085                         if (caps->cpu_enable)
2086                                 caps->cpu_enable(caps);
2087                 } else {
2088                         /*
2089                          * Check if the CPU has this capability if it isn't
2090                          * safe to have when the system doesn't.
2091                          */
2092                         if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
2093                                 break;
2094                 }
2095         }
2096
2097         if (i < ARM64_NCAPS) {
2098                 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
2099                         smp_processor_id(), caps->capability,
2100                         caps->desc, system_has_cap, cpu_has_cap);
2101                 return false;
2102         }
2103
2104         return true;
2105 }
2106
2107 /*
2108  * Check for CPU features that are used in early boot
2109  * based on the Boot CPU value.
2110  */
2111 static void check_early_cpu_features(void)
2112 {
2113         verify_cpu_asid_bits();
2114         /*
2115          * Early features are used by the kernel already. If there
2116          * is a conflict, we cannot proceed further.
2117          */
2118         if (!verify_local_cpu_caps(SCOPE_BOOT_CPU))
2119                 cpu_panic_kernel();
2120 }
2121
2122 static void
2123 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
2124 {
2125
2126         for (; caps->matches; caps++)
2127                 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
2128                         pr_crit("CPU%d: missing HWCAP: %s\n",
2129                                         smp_processor_id(), caps->desc);
2130                         cpu_die_early();
2131                 }
2132 }
2133
2134 static void verify_sve_features(void)
2135 {
2136         u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
2137         u64 zcr = read_zcr_features();
2138
2139         unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
2140         unsigned int len = zcr & ZCR_ELx_LEN_MASK;
2141
2142         if (len < safe_len || sve_verify_vq_map()) {
2143                 pr_crit("CPU%d: SVE: vector length support mismatch\n",
2144                         smp_processor_id());
2145                 cpu_die_early();
2146         }
2147
2148         /* Add checks on other ZCR bits here if necessary */
2149 }
2150
2151
2152 /*
2153  * Run through the enabled system capabilities and enable() it on this CPU.
2154  * The capabilities were decided based on the available CPUs at the boot time.
2155  * Any new CPU should match the system wide status of the capability. If the
2156  * new CPU doesn't have a capability which the system now has enabled, we
2157  * cannot do anything to fix it up and could cause unexpected failures. So
2158  * we park the CPU.
2159  */
2160 static void verify_local_cpu_capabilities(void)
2161 {
2162         /*
2163          * The capabilities with SCOPE_BOOT_CPU are checked from
2164          * check_early_cpu_features(), as they need to be verified
2165          * on all secondary CPUs.
2166          */
2167         if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU))
2168                 cpu_die_early();
2169
2170         verify_local_elf_hwcaps(arm64_elf_hwcaps);
2171
2172         if (system_supports_32bit_el0())
2173                 verify_local_elf_hwcaps(compat_elf_hwcaps);
2174
2175         if (system_supports_sve())
2176                 verify_sve_features();
2177 }
2178
2179 void check_local_cpu_capabilities(void)
2180 {
2181         /*
2182          * All secondary CPUs should conform to the early CPU features
2183          * in use by the kernel based on boot CPU.
2184          */
2185         check_early_cpu_features();
2186
2187         /*
2188          * If we haven't finalised the system capabilities, this CPU gets
2189          * a chance to update the errata work arounds and local features.
2190          * Otherwise, this CPU should verify that it has all the system
2191          * advertised capabilities.
2192          */
2193         if (!system_capabilities_finalized())
2194                 update_cpu_capabilities(SCOPE_LOCAL_CPU);
2195         else
2196                 verify_local_cpu_capabilities();
2197 }
2198
2199 static void __init setup_boot_cpu_capabilities(void)
2200 {
2201         /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
2202         update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
2203         /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
2204         enable_cpu_capabilities(SCOPE_BOOT_CPU);
2205 }
2206
2207 bool this_cpu_has_cap(unsigned int n)
2208 {
2209         if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
2210                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2211
2212                 if (cap)
2213                         return cap->matches(cap, SCOPE_LOCAL_CPU);
2214         }
2215
2216         return false;
2217 }
2218
2219 void cpu_set_feature(unsigned int num)
2220 {
2221         WARN_ON(num >= MAX_CPU_FEATURES);
2222         elf_hwcap |= BIT(num);
2223 }
2224 EXPORT_SYMBOL_GPL(cpu_set_feature);
2225
2226 bool cpu_have_feature(unsigned int num)
2227 {
2228         WARN_ON(num >= MAX_CPU_FEATURES);
2229         return elf_hwcap & BIT(num);
2230 }
2231 EXPORT_SYMBOL_GPL(cpu_have_feature);
2232
2233 unsigned long cpu_get_elf_hwcap(void)
2234 {
2235         /*
2236          * We currently only populate the first 32 bits of AT_HWCAP. Please
2237          * note that for userspace compatibility we guarantee that bits 62
2238          * and 63 will always be returned as 0.
2239          */
2240         return lower_32_bits(elf_hwcap);
2241 }
2242
2243 unsigned long cpu_get_elf_hwcap2(void)
2244 {
2245         return upper_32_bits(elf_hwcap);
2246 }
2247
2248 static void __init setup_system_capabilities(void)
2249 {
2250         /*
2251          * We have finalised the system-wide safe feature
2252          * registers, finalise the capabilities that depend
2253          * on it. Also enable all the available capabilities,
2254          * that are not enabled already.
2255          */
2256         update_cpu_capabilities(SCOPE_SYSTEM);
2257         enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2258 }
2259
2260 void __init setup_cpu_features(void)
2261 {
2262         u32 cwg;
2263
2264         setup_system_capabilities();
2265         setup_elf_hwcaps(arm64_elf_hwcaps);
2266
2267         if (system_supports_32bit_el0())
2268                 setup_elf_hwcaps(compat_elf_hwcaps);
2269
2270         if (system_uses_ttbr0_pan())
2271                 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
2272
2273         sve_setup();
2274         minsigstksz_setup();
2275
2276         /* Advertise that we have computed the system capabilities */
2277         finalize_system_capabilities();
2278
2279         /*
2280          * Check for sane CTR_EL0.CWG value.
2281          */
2282         cwg = cache_type_cwg();
2283         if (!cwg)
2284                 pr_warn("No Cache Writeback Granule information, assuming %d\n",
2285                         ARCH_DMA_MINALIGN);
2286 }
2287
2288 static bool __maybe_unused
2289 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
2290 {
2291         return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
2292 }
2293
2294 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
2295 {
2296         cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
2297 }
2298
2299 /*
2300  * We emulate only the following system register space.
2301  * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
2302  * See Table C5-6 System instruction encodings for System register accesses,
2303  * ARMv8 ARM(ARM DDI 0487A.f) for more details.
2304  */
2305 static inline bool __attribute_const__ is_emulated(u32 id)
2306 {
2307         return (sys_reg_Op0(id) == 0x3 &&
2308                 sys_reg_CRn(id) == 0x0 &&
2309                 sys_reg_Op1(id) == 0x0 &&
2310                 (sys_reg_CRm(id) == 0 ||
2311                  ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
2312 }
2313
2314 /*
2315  * With CRm == 0, reg should be one of :
2316  * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
2317  */
2318 static inline int emulate_id_reg(u32 id, u64 *valp)
2319 {
2320         switch (id) {
2321         case SYS_MIDR_EL1:
2322                 *valp = read_cpuid_id();
2323                 break;
2324         case SYS_MPIDR_EL1:
2325                 *valp = SYS_MPIDR_SAFE_VAL;
2326                 break;
2327         case SYS_REVIDR_EL1:
2328                 /* IMPLEMENTATION DEFINED values are emulated with 0 */
2329                 *valp = 0;
2330                 break;
2331         default:
2332                 return -EINVAL;
2333         }
2334
2335         return 0;
2336 }
2337
2338 static int emulate_sys_reg(u32 id, u64 *valp)
2339 {
2340         struct arm64_ftr_reg *regp;
2341
2342         if (!is_emulated(id))
2343                 return -EINVAL;
2344
2345         if (sys_reg_CRm(id) == 0)
2346                 return emulate_id_reg(id, valp);
2347
2348         regp = get_arm64_ftr_reg(id);
2349         if (regp)
2350                 *valp = arm64_ftr_reg_user_value(regp);
2351         else
2352                 /*
2353                  * The untracked registers are either IMPLEMENTATION DEFINED
2354                  * (e.g, ID_AFR0_EL1) or reserved RAZ.
2355                  */
2356                 *valp = 0;
2357         return 0;
2358 }
2359
2360 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
2361 {
2362         int rc;
2363         u64 val;
2364
2365         rc = emulate_sys_reg(sys_reg, &val);
2366         if (!rc) {
2367                 pt_regs_write_reg(regs, rt, val);
2368                 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
2369         }
2370         return rc;
2371 }
2372
2373 static int emulate_mrs(struct pt_regs *regs, u32 insn)
2374 {
2375         u32 sys_reg, rt;
2376
2377         /*
2378          * sys_reg values are defined as used in mrs/msr instruction.
2379          * shift the imm value to get the encoding.
2380          */
2381         sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
2382         rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
2383         return do_emulate_mrs(regs, sys_reg, rt);
2384 }
2385
2386 static struct undef_hook mrs_hook = {
2387         .instr_mask = 0xfff00000,
2388         .instr_val  = 0xd5300000,
2389         .pstate_mask = PSR_AA32_MODE_MASK,
2390         .pstate_val = PSR_MODE_EL0t,
2391         .fn = emulate_mrs,
2392 };
2393
2394 static int __init enable_mrs_emulation(void)
2395 {
2396         register_undef_hook(&mrs_hook);
2397         return 0;
2398 }
2399
2400 core_initcall(enable_mrs_emulation);
2401
2402 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
2403                           char *buf)
2404 {
2405         if (__meltdown_safe)
2406                 return sprintf(buf, "Not affected\n");
2407
2408         if (arm64_kernel_unmapped_at_el0())
2409                 return sprintf(buf, "Mitigation: PTI\n");
2410
2411         return sprintf(buf, "Vulnerable\n");
2412 }