1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012 ARM Ltd.
5 #ifndef __ASM_PGTABLE_H
6 #define __ASM_PGTABLE_H
9 #include <asm/proc-fns.h>
11 #include <asm/memory.h>
13 #include <asm/pgtable-hwdef.h>
14 #include <asm/pgtable-prot.h>
15 #include <asm/tlbflush.h>
20 * VMALLOC_START: beginning of the kernel vmalloc space
21 * VMALLOC_END: extends to the available space below vmemmap, PCI I/O space
24 #define VMALLOC_START (MODULES_END)
25 #define VMALLOC_END (VMEMMAP_START - SZ_256M)
27 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT))
31 #include <asm/cmpxchg.h>
32 #include <asm/fixmap.h>
33 #include <linux/mmdebug.h>
34 #include <linux/mm_types.h>
35 #include <linux/sched.h>
37 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
38 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
40 /* Set stride and tlb_level in flush_*_tlb_range */
41 #define flush_pmd_tlb_range(vma, addr, end) \
42 __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2)
43 #define flush_pud_tlb_range(vma, addr, end) \
44 __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1)
45 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
48 * Outside of a few very special situations (e.g. hibernation), we always
49 * use broadcast TLB invalidation instructions, therefore a spurious page
50 * fault on one CPU which has been handled concurrently by another CPU
51 * does not need to perform additional invalidation.
53 #define flush_tlb_fix_spurious_fault(vma, address) do { } while (0)
56 * ZERO_PAGE is a global shared page that is always zero: used
57 * for zero-mapped memory areas etc..
59 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
60 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page))
62 #define pte_ERROR(e) \
63 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e))
66 * Macros to convert between a physical address and its placement in a
67 * page table entry, taking care of 52-bit addresses.
69 #ifdef CONFIG_ARM64_PA_BITS_52
70 #define __pte_to_phys(pte) \
71 ((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36))
72 #define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK)
74 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK)
75 #define __phys_to_pte_val(phys) (phys)
78 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT)
79 #define pfn_pte(pfn,prot) \
80 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
82 #define pte_none(pte) (!pte_val(pte))
83 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
84 #define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
87 * The following only work if pte_present(). Undefined behaviour otherwise.
89 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
90 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF))
91 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL))
92 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
93 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN))
94 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT))
95 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP))
96 #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \
97 PTE_ATTRINDX(MT_NORMAL_TAGGED))
99 #define pte_cont_addr_end(addr, end) \
100 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \
101 (__boundary - 1 < (end) - 1) ? __boundary : (end); \
104 #define pmd_cont_addr_end(addr, end) \
105 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \
106 (__boundary - 1 < (end) - 1) ? __boundary : (end); \
109 #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY))
110 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY))
111 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte))
113 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID))
115 * Execute-only user mappings do not have the PTE_USER bit set. All valid
116 * kernel mappings have the PTE_UXN bit set.
118 #define pte_valid_not_user(pte) \
119 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN))
121 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending
122 * so that we don't erroneously return false for pages that have been
123 * remapped as PROT_NONE but are yet to be flushed from the TLB.
124 * Note that we can't make any assumptions based on the state of the access
125 * flag, since ptep_clear_flush_young() elides a DSB when invalidating the
128 #define pte_accessible(mm, pte) \
129 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte))
132 * p??_access_permitted() is true for valid user mappings (PTE_USER
133 * bit set, subject to the write permission check). For execute-only
134 * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits
135 * not set) must return false. PROT_NONE mappings do not have the
138 #define pte_access_permitted(pte, write) \
139 (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte)))
140 #define pmd_access_permitted(pmd, write) \
141 (pte_access_permitted(pmd_pte(pmd), (write)))
142 #define pud_access_permitted(pud, write) \
143 (pte_access_permitted(pud_pte(pud), (write)))
145 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
147 pte_val(pte) &= ~pgprot_val(prot);
151 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
153 pte_val(pte) |= pgprot_val(prot);
157 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot)
159 pmd_val(pmd) &= ~pgprot_val(prot);
163 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot)
165 pmd_val(pmd) |= pgprot_val(prot);
169 static inline pte_t pte_mkwrite(pte_t pte)
171 pte = set_pte_bit(pte, __pgprot(PTE_WRITE));
172 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
176 static inline pte_t pte_mkclean(pte_t pte)
178 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY));
179 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
184 static inline pte_t pte_mkdirty(pte_t pte)
186 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY));
189 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
194 static inline pte_t pte_wrprotect(pte_t pte)
197 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY
198 * clear), set the PTE_DIRTY bit.
200 if (pte_hw_dirty(pte))
201 pte = pte_mkdirty(pte);
203 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE));
204 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
208 static inline pte_t pte_mkold(pte_t pte)
210 return clear_pte_bit(pte, __pgprot(PTE_AF));
213 static inline pte_t pte_mkyoung(pte_t pte)
215 return set_pte_bit(pte, __pgprot(PTE_AF));
218 static inline pte_t pte_mkspecial(pte_t pte)
220 return set_pte_bit(pte, __pgprot(PTE_SPECIAL));
223 static inline pte_t pte_mkcont(pte_t pte)
225 pte = set_pte_bit(pte, __pgprot(PTE_CONT));
226 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE));
229 static inline pte_t pte_mknoncont(pte_t pte)
231 return clear_pte_bit(pte, __pgprot(PTE_CONT));
234 static inline pte_t pte_mkpresent(pte_t pte)
236 return set_pte_bit(pte, __pgprot(PTE_VALID));
239 static inline pmd_t pmd_mkcont(pmd_t pmd)
241 return __pmd(pmd_val(pmd) | PMD_SECT_CONT);
244 static inline pte_t pte_mkdevmap(pte_t pte)
246 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL));
249 static inline void set_pte(pte_t *ptep, pte_t pte)
251 WRITE_ONCE(*ptep, pte);
254 * Only if the new pte is valid and kernel, otherwise TLB maintenance
255 * or update_mmu_cache() have the necessary barriers.
257 if (pte_valid_not_user(pte)) {
263 extern void __sync_icache_dcache(pte_t pteval);
266 * PTE bits configuration in the presence of hardware Dirty Bit Management
267 * (PTE_WRITE == PTE_DBM):
269 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw)
275 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via
276 * the page fault mechanism. Checking the dirty status of a pte becomes:
278 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)
281 static inline void __check_racy_pte_update(struct mm_struct *mm, pte_t *ptep,
286 if (!IS_ENABLED(CONFIG_DEBUG_VM))
289 old_pte = READ_ONCE(*ptep);
291 if (!pte_valid(old_pte) || !pte_valid(pte))
293 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1)
297 * Check for potential race with hardware updates of the pte
298 * (ptep_set_access_flags safely changes valid ptes without going
299 * through an invalid entry).
301 VM_WARN_ONCE(!pte_young(pte),
302 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx",
303 __func__, pte_val(old_pte), pte_val(pte));
304 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte),
305 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx",
306 __func__, pte_val(old_pte), pte_val(pte));
309 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
310 pte_t *ptep, pte_t pte)
312 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte))
313 __sync_icache_dcache(pte);
316 * If the PTE would provide user space access to the tags associated
317 * with it then ensure that the MTE tags are synchronised. Although
318 * pte_access_permitted() returns false for exec only mappings, they
319 * don't expose tags (instruction fetches don't check tags).
321 if (system_supports_mte() && pte_access_permitted(pte, false) &&
323 pte_t old_pte = READ_ONCE(*ptep);
325 * We only need to synchronise if the new PTE has tags enabled
326 * or if swapping in (in which case another mapping may have
327 * set tags in the past even if this PTE isn't tagged).
328 * (!pte_none() && !pte_present()) is an open coded version of
331 if (pte_tagged(pte) || (!pte_none(old_pte) && !pte_present(old_pte)))
332 mte_sync_tags(old_pte, pte);
335 __check_racy_pte_update(mm, ptep, pte);
341 * Huge pte definitions.
343 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
346 * Hugetlb definitions.
348 #define HUGE_MAX_HSTATE 4
349 #define HPAGE_SHIFT PMD_SHIFT
350 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
351 #define HPAGE_MASK (~(HPAGE_SIZE - 1))
352 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
354 static inline pte_t pgd_pte(pgd_t pgd)
356 return __pte(pgd_val(pgd));
359 static inline pte_t p4d_pte(p4d_t p4d)
361 return __pte(p4d_val(p4d));
364 static inline pte_t pud_pte(pud_t pud)
366 return __pte(pud_val(pud));
369 static inline pud_t pte_pud(pte_t pte)
371 return __pud(pte_val(pte));
374 static inline pmd_t pud_pmd(pud_t pud)
376 return __pmd(pud_val(pud));
379 static inline pte_t pmd_pte(pmd_t pmd)
381 return __pte(pmd_val(pmd));
384 static inline pmd_t pte_pmd(pte_t pte)
386 return __pmd(pte_val(pte));
389 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot)
391 return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT);
394 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot)
396 return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT);
399 #ifdef CONFIG_NUMA_BALANCING
401 * See the comment in include/linux/pgtable.h
403 static inline int pte_protnone(pte_t pte)
405 return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE;
408 static inline int pmd_protnone(pmd_t pmd)
410 return pte_protnone(pmd_pte(pmd));
414 #define pmd_present_invalid(pmd) (!!(pmd_val(pmd) & PMD_PRESENT_INVALID))
416 static inline int pmd_present(pmd_t pmd)
418 return pte_present(pmd_pte(pmd)) || pmd_present_invalid(pmd);
425 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
426 static inline int pmd_trans_huge(pmd_t pmd)
428 return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT);
430 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
432 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
433 #define pmd_young(pmd) pte_young(pmd_pte(pmd))
434 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd))
435 #define pmd_cont(pmd) pte_cont(pmd_pte(pmd))
436 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
437 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
438 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
439 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
440 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
441 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
443 static inline pmd_t pmd_mkinvalid(pmd_t pmd)
445 pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID));
446 pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID));
451 #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd))
453 #define pmd_write(pmd) pte_write(pmd_pte(pmd))
455 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
457 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
458 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd))
460 static inline pmd_t pmd_mkdevmap(pmd_t pmd)
462 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP)));
465 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd))
466 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys)
467 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT)
468 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
469 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
471 #define pud_young(pud) pte_young(pud_pte(pud))
472 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud)))
473 #define pud_write(pud) pte_write(pud_pte(pud))
475 #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT))
477 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud))
478 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys)
479 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT)
480 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
482 #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd))
483 #define set_pud_at(mm, addr, pudp, pud) set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud))
485 #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d))
486 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys)
488 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd))
489 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys)
491 #define __pgprot_modify(prot,mask,bits) \
492 __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
494 #define pgprot_nx(prot) \
495 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN)
498 * Mark the prot value as uncacheable and unbufferable.
500 #define pgprot_noncached(prot) \
501 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
502 #define pgprot_writecombine(prot) \
503 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
504 #define pgprot_device(prot) \
505 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
506 #define pgprot_tagged(prot) \
507 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED))
508 #define pgprot_mhp pgprot_tagged
510 * DMA allocations for non-coherent devices use what the Arm architecture calls
511 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses
512 * and merging of writes. This is different from "Device-nGnR[nE]" memory which
513 * is intended for MMIO and thus forbids speculation, preserves access size,
514 * requires strict alignment and can also force write responses to come from the
517 #define pgprot_dmacoherent(prot) \
518 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \
519 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
521 #define __HAVE_PHYS_MEM_ACCESS_PROT
523 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
524 unsigned long size, pgprot_t vma_prot);
526 #define pmd_none(pmd) (!pmd_val(pmd))
528 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
530 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
532 #define pmd_leaf(pmd) pmd_sect(pmd)
533 #define pmd_bad(pmd) (!pmd_table(pmd))
535 #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE)
536 #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE)
538 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3
539 static inline bool pud_sect(pud_t pud) { return false; }
540 static inline bool pud_table(pud_t pud) { return true; }
542 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
544 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
548 extern pgd_t init_pg_dir[PTRS_PER_PGD];
549 extern pgd_t init_pg_end[];
550 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
551 extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
552 extern pgd_t idmap_pg_end[];
553 extern pgd_t tramp_pg_dir[PTRS_PER_PGD];
554 extern pgd_t reserved_pg_dir[PTRS_PER_PGD];
556 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd);
558 static inline bool in_swapper_pgdir(void *addr)
560 return ((unsigned long)addr & PAGE_MASK) ==
561 ((unsigned long)swapper_pg_dir & PAGE_MASK);
564 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
566 #ifdef __PAGETABLE_PMD_FOLDED
567 if (in_swapper_pgdir(pmdp)) {
568 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd)));
571 #endif /* __PAGETABLE_PMD_FOLDED */
573 WRITE_ONCE(*pmdp, pmd);
575 if (pmd_valid(pmd)) {
581 static inline void pmd_clear(pmd_t *pmdp)
583 set_pmd(pmdp, __pmd(0));
586 static inline phys_addr_t pmd_page_paddr(pmd_t pmd)
588 return __pmd_to_phys(pmd);
591 static inline unsigned long pmd_page_vaddr(pmd_t pmd)
593 return (unsigned long)__va(pmd_page_paddr(pmd));
596 /* Find an entry in the third-level page table. */
597 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t))
599 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr))
600 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr))
601 #define pte_clear_fixmap() clear_fixmap(FIX_PTE)
603 #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd))
605 /* use ONLY for statically allocated translation tables */
606 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr))))
609 * Conversion functions: convert a page and protection to a page entry,
610 * and a page entry and page directory to the page they refer to.
612 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
614 #if CONFIG_PGTABLE_LEVELS > 2
616 #define pmd_ERROR(e) \
617 pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e))
619 #define pud_none(pud) (!pud_val(pud))
620 #define pud_bad(pud) (!pud_table(pud))
621 #define pud_present(pud) pte_present(pud_pte(pud))
622 #define pud_leaf(pud) pud_sect(pud)
623 #define pud_valid(pud) pte_valid(pud_pte(pud))
625 static inline void set_pud(pud_t *pudp, pud_t pud)
627 #ifdef __PAGETABLE_PUD_FOLDED
628 if (in_swapper_pgdir(pudp)) {
629 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud)));
632 #endif /* __PAGETABLE_PUD_FOLDED */
634 WRITE_ONCE(*pudp, pud);
636 if (pud_valid(pud)) {
642 static inline void pud_clear(pud_t *pudp)
644 set_pud(pudp, __pud(0));
647 static inline phys_addr_t pud_page_paddr(pud_t pud)
649 return __pud_to_phys(pud);
652 static inline unsigned long pud_page_vaddr(pud_t pud)
654 return (unsigned long)__va(pud_page_paddr(pud));
657 /* Find an entry in the second-level page table. */
658 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t))
660 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr))
661 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr))
662 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD)
664 #define pud_page(pud) phys_to_page(__pud_to_phys(pud))
666 /* use ONLY for statically allocated translation tables */
667 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr))))
671 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; })
673 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */
674 #define pmd_set_fixmap(addr) NULL
675 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp)
676 #define pmd_clear_fixmap()
678 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir)
680 #endif /* CONFIG_PGTABLE_LEVELS > 2 */
682 #if CONFIG_PGTABLE_LEVELS > 3
684 #define pud_ERROR(e) \
685 pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e))
687 #define p4d_none(p4d) (!p4d_val(p4d))
688 #define p4d_bad(p4d) (!(p4d_val(p4d) & 2))
689 #define p4d_present(p4d) (p4d_val(p4d))
691 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d)
693 if (in_swapper_pgdir(p4dp)) {
694 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d)));
698 WRITE_ONCE(*p4dp, p4d);
703 static inline void p4d_clear(p4d_t *p4dp)
705 set_p4d(p4dp, __p4d(0));
708 static inline phys_addr_t p4d_page_paddr(p4d_t p4d)
710 return __p4d_to_phys(p4d);
713 static inline unsigned long p4d_page_vaddr(p4d_t p4d)
715 return (unsigned long)__va(p4d_page_paddr(p4d));
718 /* Find an entry in the frst-level page table. */
719 #define pud_offset_phys(dir, addr) (p4d_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t))
721 #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr))
722 #define pud_set_fixmap_offset(p4d, addr) pud_set_fixmap(pud_offset_phys(p4d, addr))
723 #define pud_clear_fixmap() clear_fixmap(FIX_PUD)
725 #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d)))
727 /* use ONLY for statically allocated translation tables */
728 #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr))))
732 #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;})
733 #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;})
735 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */
736 #define pud_set_fixmap(addr) NULL
737 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp)
738 #define pud_clear_fixmap()
740 #define pud_offset_kimg(dir,addr) ((pud_t *)dir)
742 #endif /* CONFIG_PGTABLE_LEVELS > 3 */
744 #define pgd_ERROR(e) \
745 pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e))
747 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr))
748 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD)
750 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
753 * Normal and Normal-Tagged are two different memory types and indices
754 * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK.
756 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
757 PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP |
759 /* preserve the hardware dirty information */
760 if (pte_hw_dirty(pte))
761 pte = pte_mkdirty(pte);
762 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
766 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
768 return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
771 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
772 extern int ptep_set_access_flags(struct vm_area_struct *vma,
773 unsigned long address, pte_t *ptep,
774 pte_t entry, int dirty);
776 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
777 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
778 static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
779 unsigned long address, pmd_t *pmdp,
780 pmd_t entry, int dirty)
782 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty);
785 static inline int pud_devmap(pud_t pud)
790 static inline int pgd_devmap(pgd_t pgd)
797 * Atomic pte/pmd modifications.
799 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
800 static inline int __ptep_test_and_clear_young(pte_t *ptep)
804 pte = READ_ONCE(*ptep);
807 pte = pte_mkold(pte);
808 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
809 pte_val(old_pte), pte_val(pte));
810 } while (pte_val(pte) != pte_val(old_pte));
812 return pte_young(pte);
815 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
816 unsigned long address,
819 return __ptep_test_and_clear_young(ptep);
822 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
823 static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
824 unsigned long address, pte_t *ptep)
826 int young = ptep_test_and_clear_young(vma, address, ptep);
830 * We can elide the trailing DSB here since the worst that can
831 * happen is that a CPU continues to use the young entry in its
832 * TLB and we mistakenly reclaim the associated page. The
833 * window for such an event is bounded by the next
834 * context-switch, which provides a DSB to complete the TLB
837 flush_tlb_page_nosync(vma, address);
843 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
844 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
845 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
846 unsigned long address,
849 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp);
851 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
853 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
854 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
855 unsigned long address, pte_t *ptep)
857 return __pte(xchg_relaxed(&pte_val(*ptep), 0));
860 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
861 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
862 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
863 unsigned long address, pmd_t *pmdp)
865 return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp));
867 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
870 * ptep_set_wrprotect - mark read-only while trasferring potential hardware
871 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit.
873 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
874 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
878 pte = READ_ONCE(*ptep);
881 pte = pte_wrprotect(pte);
882 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
883 pte_val(old_pte), pte_val(pte));
884 } while (pte_val(pte) != pte_val(old_pte));
887 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
888 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
889 static inline void pmdp_set_wrprotect(struct mm_struct *mm,
890 unsigned long address, pmd_t *pmdp)
892 ptep_set_wrprotect(mm, address, (pte_t *)pmdp);
895 #define pmdp_establish pmdp_establish
896 static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
897 unsigned long address, pmd_t *pmdp, pmd_t pmd)
899 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd)));
904 * Encode and decode a swap entry:
905 * bits 0-1: present (must be zero)
906 * bits 2-7: swap type
907 * bits 8-57: swap offset
908 * bit 58: PTE_PROT_NONE (must be zero)
910 #define __SWP_TYPE_SHIFT 2
911 #define __SWP_TYPE_BITS 6
912 #define __SWP_OFFSET_BITS 50
913 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
914 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
915 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
917 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
918 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
919 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
921 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
922 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
924 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
925 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) })
926 #define __swp_entry_to_pmd(swp) __pmd((swp).val)
927 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
930 * Ensure that there are not more swap files than can be encoded in the kernel
933 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
935 extern int kern_addr_valid(unsigned long addr);
937 #ifdef CONFIG_ARM64_MTE
939 #define __HAVE_ARCH_PREPARE_TO_SWAP
940 static inline int arch_prepare_to_swap(struct page *page)
942 if (system_supports_mte())
943 return mte_save_tags(page);
947 #define __HAVE_ARCH_SWAP_INVALIDATE
948 static inline void arch_swap_invalidate_page(int type, pgoff_t offset)
950 if (system_supports_mte())
951 mte_invalidate_tags(type, offset);
954 static inline void arch_swap_invalidate_area(int type)
956 if (system_supports_mte())
957 mte_invalidate_tags_area(type);
960 #define __HAVE_ARCH_SWAP_RESTORE
961 static inline void arch_swap_restore(swp_entry_t entry, struct page *page)
963 if (system_supports_mte() && mte_restore_tags(entry, page))
964 set_bit(PG_mte_tagged, &page->flags);
967 #endif /* CONFIG_ARM64_MTE */
970 * On AArch64, the cache coherency is handled via the set_pte_at() function.
972 static inline void update_mmu_cache(struct vm_area_struct *vma,
973 unsigned long addr, pte_t *ptep)
976 * We don't do anything here, so there's a very small chance of
977 * us retaking a user fault which we just fixed up. The alternative
978 * is doing a dsb(ishst), but that penalises the fastpath.
982 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
984 #ifdef CONFIG_ARM64_PA_BITS_52
985 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52)
987 #define phys_to_ttbr(addr) (addr)
991 * On arm64 without hardware Access Flag, copying from user will fail because
992 * the pte is old and cannot be marked young. So we always end up with zeroed
993 * page after fork() + CoW for pfn mappings. We don't always have a
994 * hardware-managed access flag on arm64.
996 static inline bool arch_faults_on_old_pte(void)
998 WARN_ON(preemptible());
1000 return !cpu_has_hw_af();
1002 #define arch_faults_on_old_pte arch_faults_on_old_pte
1005 * Experimentally, it's cheap to set the access flag in hardware and we
1006 * benefit from prefaulting mappings as 'old' to start with.
1008 static inline bool arch_wants_old_prefaulted_pte(void)
1010 return !arch_faults_on_old_pte();
1012 #define arch_wants_old_prefaulted_pte arch_wants_old_prefaulted_pte
1014 static inline pgprot_t arch_filter_pgprot(pgprot_t prot)
1016 if (cpus_have_const_cap(ARM64_HAS_EPAN))
1019 if (pgprot_val(prot) != pgprot_val(PAGE_EXECONLY))
1022 return PAGE_READONLY_EXEC;
1026 #endif /* !__ASSEMBLY__ */
1028 #endif /* __ASM_PGTABLE_H */