1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012 ARM Ltd.
5 #ifndef __ASM_PGTABLE_H
6 #define __ASM_PGTABLE_H
9 #include <asm/proc-fns.h>
11 #include <asm/memory.h>
13 #include <asm/pgtable-hwdef.h>
14 #include <asm/pgtable-prot.h>
15 #include <asm/tlbflush.h>
20 * VMALLOC_START: beginning of the kernel vmalloc space
21 * VMALLOC_END: extends to the available space below vmemmap
23 #define VMALLOC_START (MODULES_END)
24 #if VA_BITS == VA_BITS_MIN
25 #define VMALLOC_END (VMEMMAP_START - SZ_8M)
27 #define VMEMMAP_UNUSED_NPAGES ((_PAGE_OFFSET(vabits_actual) - PAGE_OFFSET) >> PAGE_SHIFT)
28 #define VMALLOC_END (VMEMMAP_START + VMEMMAP_UNUSED_NPAGES * sizeof(struct page) - SZ_8M)
31 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT))
35 #include <asm/cmpxchg.h>
36 #include <asm/fixmap.h>
37 #include <linux/mmdebug.h>
38 #include <linux/mm_types.h>
39 #include <linux/sched.h>
40 #include <linux/page_table_check.h>
42 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
43 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
45 /* Set stride and tlb_level in flush_*_tlb_range */
46 #define flush_pmd_tlb_range(vma, addr, end) \
47 __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2)
48 #define flush_pud_tlb_range(vma, addr, end) \
49 __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1)
50 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
52 static inline bool arch_thp_swp_supported(void)
54 return !system_supports_mte();
56 #define arch_thp_swp_supported arch_thp_swp_supported
59 * Outside of a few very special situations (e.g. hibernation), we always
60 * use broadcast TLB invalidation instructions, therefore a spurious page
61 * fault on one CPU which has been handled concurrently by another CPU
62 * does not need to perform additional invalidation.
64 #define flush_tlb_fix_spurious_fault(vma, address, ptep) do { } while (0)
67 * ZERO_PAGE is a global shared page that is always zero: used
68 * for zero-mapped memory areas etc..
70 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
71 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page))
73 #define pte_ERROR(e) \
74 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e))
77 * Macros to convert between a physical address and its placement in a
78 * page table entry, taking care of 52-bit addresses.
80 #ifdef CONFIG_ARM64_PA_BITS_52
81 static inline phys_addr_t __pte_to_phys(pte_t pte)
83 return (pte_val(pte) & PTE_ADDR_LOW) |
84 ((pte_val(pte) & PTE_ADDR_HIGH) << PTE_ADDR_HIGH_SHIFT);
86 static inline pteval_t __phys_to_pte_val(phys_addr_t phys)
88 return (phys | (phys >> PTE_ADDR_HIGH_SHIFT)) & PTE_ADDR_MASK;
91 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK)
92 #define __phys_to_pte_val(phys) (phys)
95 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT)
96 #define pfn_pte(pfn,prot) \
97 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
99 #define pte_none(pte) (!pte_val(pte))
100 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
101 #define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
104 * The following only work if pte_present(). Undefined behaviour otherwise.
106 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
107 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF))
108 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL))
109 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
110 #define pte_rdonly(pte) (!!(pte_val(pte) & PTE_RDONLY))
111 #define pte_user(pte) (!!(pte_val(pte) & PTE_USER))
112 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN))
113 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT))
114 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP))
115 #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \
116 PTE_ATTRINDX(MT_NORMAL_TAGGED))
118 #define pte_cont_addr_end(addr, end) \
119 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \
120 (__boundary - 1 < (end) - 1) ? __boundary : (end); \
123 #define pmd_cont_addr_end(addr, end) \
124 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \
125 (__boundary - 1 < (end) - 1) ? __boundary : (end); \
128 #define pte_hw_dirty(pte) (pte_write(pte) && !pte_rdonly(pte))
129 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY))
130 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte))
132 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID))
134 * Execute-only user mappings do not have the PTE_USER bit set. All valid
135 * kernel mappings have the PTE_UXN bit set.
137 #define pte_valid_not_user(pte) \
138 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN))
140 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending
141 * so that we don't erroneously return false for pages that have been
142 * remapped as PROT_NONE but are yet to be flushed from the TLB.
143 * Note that we can't make any assumptions based on the state of the access
144 * flag, since ptep_clear_flush_young() elides a DSB when invalidating the
147 #define pte_accessible(mm, pte) \
148 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte))
151 * p??_access_permitted() is true for valid user mappings (PTE_USER
152 * bit set, subject to the write permission check). For execute-only
153 * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits
154 * not set) must return false. PROT_NONE mappings do not have the
157 #define pte_access_permitted(pte, write) \
158 (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte)))
159 #define pmd_access_permitted(pmd, write) \
160 (pte_access_permitted(pmd_pte(pmd), (write)))
161 #define pud_access_permitted(pud, write) \
162 (pte_access_permitted(pud_pte(pud), (write)))
164 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
166 pte_val(pte) &= ~pgprot_val(prot);
170 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
172 pte_val(pte) |= pgprot_val(prot);
176 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot)
178 pmd_val(pmd) &= ~pgprot_val(prot);
182 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot)
184 pmd_val(pmd) |= pgprot_val(prot);
188 static inline pte_t pte_mkwrite_novma(pte_t pte)
190 pte = set_pte_bit(pte, __pgprot(PTE_WRITE));
191 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
195 static inline pte_t pte_mkclean(pte_t pte)
197 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY));
198 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
203 static inline pte_t pte_mkdirty(pte_t pte)
205 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY));
208 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
213 static inline pte_t pte_wrprotect(pte_t pte)
216 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY
217 * clear), set the PTE_DIRTY bit.
219 if (pte_hw_dirty(pte))
220 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY));
222 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE));
223 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
227 static inline pte_t pte_mkold(pte_t pte)
229 return clear_pte_bit(pte, __pgprot(PTE_AF));
232 static inline pte_t pte_mkyoung(pte_t pte)
234 return set_pte_bit(pte, __pgprot(PTE_AF));
237 static inline pte_t pte_mkspecial(pte_t pte)
239 return set_pte_bit(pte, __pgprot(PTE_SPECIAL));
242 static inline pte_t pte_mkcont(pte_t pte)
244 pte = set_pte_bit(pte, __pgprot(PTE_CONT));
245 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE));
248 static inline pte_t pte_mknoncont(pte_t pte)
250 return clear_pte_bit(pte, __pgprot(PTE_CONT));
253 static inline pte_t pte_mkpresent(pte_t pte)
255 return set_pte_bit(pte, __pgprot(PTE_VALID));
258 static inline pmd_t pmd_mkcont(pmd_t pmd)
260 return __pmd(pmd_val(pmd) | PMD_SECT_CONT);
263 static inline pte_t pte_mkdevmap(pte_t pte)
265 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL));
268 static inline void set_pte(pte_t *ptep, pte_t pte)
270 WRITE_ONCE(*ptep, pte);
273 * Only if the new pte is valid and kernel, otherwise TLB maintenance
274 * or update_mmu_cache() have the necessary barriers.
276 if (pte_valid_not_user(pte)) {
282 extern void __sync_icache_dcache(pte_t pteval);
283 bool pgattr_change_is_safe(u64 old, u64 new);
286 * PTE bits configuration in the presence of hardware Dirty Bit Management
287 * (PTE_WRITE == PTE_DBM):
289 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw)
295 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via
296 * the page fault mechanism. Checking the dirty status of a pte becomes:
298 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)
301 static inline void __check_safe_pte_update(struct mm_struct *mm, pte_t *ptep,
306 if (!IS_ENABLED(CONFIG_DEBUG_VM))
309 old_pte = READ_ONCE(*ptep);
311 if (!pte_valid(old_pte) || !pte_valid(pte))
313 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1)
317 * Check for potential race with hardware updates of the pte
318 * (ptep_set_access_flags safely changes valid ptes without going
319 * through an invalid entry).
321 VM_WARN_ONCE(!pte_young(pte),
322 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx",
323 __func__, pte_val(old_pte), pte_val(pte));
324 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte),
325 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx",
326 __func__, pte_val(old_pte), pte_val(pte));
327 VM_WARN_ONCE(!pgattr_change_is_safe(pte_val(old_pte), pte_val(pte)),
328 "%s: unsafe attribute change: 0x%016llx -> 0x%016llx",
329 __func__, pte_val(old_pte), pte_val(pte));
332 static inline void __sync_cache_and_tags(pte_t pte, unsigned int nr_pages)
334 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte))
335 __sync_icache_dcache(pte);
338 * If the PTE would provide user space access to the tags associated
339 * with it then ensure that the MTE tags are synchronised. Although
340 * pte_access_permitted() returns false for exec only mappings, they
341 * don't expose tags (instruction fetches don't check tags).
343 if (system_supports_mte() && pte_access_permitted(pte, false) &&
344 !pte_special(pte) && pte_tagged(pte))
345 mte_sync_tags(pte, nr_pages);
348 static inline void set_ptes(struct mm_struct *mm,
349 unsigned long __always_unused addr,
350 pte_t *ptep, pte_t pte, unsigned int nr)
352 page_table_check_ptes_set(mm, ptep, pte, nr);
353 __sync_cache_and_tags(pte, nr);
356 __check_safe_pte_update(mm, ptep, pte);
361 pte_val(pte) += PAGE_SIZE;
364 #define set_ptes set_ptes
367 * Huge pte definitions.
369 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
372 * Hugetlb definitions.
374 #define HUGE_MAX_HSTATE 4
375 #define HPAGE_SHIFT PMD_SHIFT
376 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
377 #define HPAGE_MASK (~(HPAGE_SIZE - 1))
378 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
380 static inline pte_t pgd_pte(pgd_t pgd)
382 return __pte(pgd_val(pgd));
385 static inline pte_t p4d_pte(p4d_t p4d)
387 return __pte(p4d_val(p4d));
390 static inline pte_t pud_pte(pud_t pud)
392 return __pte(pud_val(pud));
395 static inline pud_t pte_pud(pte_t pte)
397 return __pud(pte_val(pte));
400 static inline pmd_t pud_pmd(pud_t pud)
402 return __pmd(pud_val(pud));
405 static inline pte_t pmd_pte(pmd_t pmd)
407 return __pte(pmd_val(pmd));
410 static inline pmd_t pte_pmd(pte_t pte)
412 return __pmd(pte_val(pte));
415 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot)
417 return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT);
420 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot)
422 return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT);
425 static inline pte_t pte_swp_mkexclusive(pte_t pte)
427 return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE));
430 static inline int pte_swp_exclusive(pte_t pte)
432 return pte_val(pte) & PTE_SWP_EXCLUSIVE;
435 static inline pte_t pte_swp_clear_exclusive(pte_t pte)
437 return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE));
441 * Select all bits except the pfn
443 static inline pgprot_t pte_pgprot(pte_t pte)
445 unsigned long pfn = pte_pfn(pte);
447 return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte));
450 #ifdef CONFIG_NUMA_BALANCING
452 * See the comment in include/linux/pgtable.h
454 static inline int pte_protnone(pte_t pte)
456 return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE;
459 static inline int pmd_protnone(pmd_t pmd)
461 return pte_protnone(pmd_pte(pmd));
465 #define pmd_present_invalid(pmd) (!!(pmd_val(pmd) & PMD_PRESENT_INVALID))
467 static inline int pmd_present(pmd_t pmd)
469 return pte_present(pmd_pte(pmd)) || pmd_present_invalid(pmd);
476 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
477 static inline int pmd_trans_huge(pmd_t pmd)
479 return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT);
481 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
483 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
484 #define pmd_young(pmd) pte_young(pmd_pte(pmd))
485 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd))
486 #define pmd_user(pmd) pte_user(pmd_pte(pmd))
487 #define pmd_user_exec(pmd) pte_user_exec(pmd_pte(pmd))
488 #define pmd_cont(pmd) pte_cont(pmd_pte(pmd))
489 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
490 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
491 #define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd)))
492 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
493 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
494 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
496 static inline pmd_t pmd_mkinvalid(pmd_t pmd)
498 pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID));
499 pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID));
504 #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd))
506 #define pmd_write(pmd) pte_write(pmd_pte(pmd))
508 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
510 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
511 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd))
513 static inline pmd_t pmd_mkdevmap(pmd_t pmd)
515 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP)));
518 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd))
519 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys)
520 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT)
521 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
522 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
524 #define pud_young(pud) pte_young(pud_pte(pud))
525 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud)))
526 #define pud_write(pud) pte_write(pud_pte(pud))
528 #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT))
530 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud))
531 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys)
532 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT)
533 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
535 static inline void __set_pte_at(struct mm_struct *mm,
536 unsigned long __always_unused addr,
537 pte_t *ptep, pte_t pte, unsigned int nr)
539 __sync_cache_and_tags(pte, nr);
540 __check_safe_pte_update(mm, ptep, pte);
544 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
545 pmd_t *pmdp, pmd_t pmd)
547 page_table_check_pmd_set(mm, pmdp, pmd);
548 return __set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd),
549 PMD_SIZE >> PAGE_SHIFT);
552 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr,
553 pud_t *pudp, pud_t pud)
555 page_table_check_pud_set(mm, pudp, pud);
556 return __set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud),
557 PUD_SIZE >> PAGE_SHIFT);
560 #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d))
561 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys)
563 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd))
564 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys)
566 #define __pgprot_modify(prot,mask,bits) \
567 __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
569 #define pgprot_nx(prot) \
570 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN)
573 * Mark the prot value as uncacheable and unbufferable.
575 #define pgprot_noncached(prot) \
576 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
577 #define pgprot_writecombine(prot) \
578 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
579 #define pgprot_device(prot) \
580 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
581 #define pgprot_tagged(prot) \
582 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED))
583 #define pgprot_mhp pgprot_tagged
585 * DMA allocations for non-coherent devices use what the Arm architecture calls
586 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses
587 * and merging of writes. This is different from "Device-nGnR[nE]" memory which
588 * is intended for MMIO and thus forbids speculation, preserves access size,
589 * requires strict alignment and can also force write responses to come from the
592 #define pgprot_dmacoherent(prot) \
593 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \
594 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
596 #define __HAVE_PHYS_MEM_ACCESS_PROT
598 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
599 unsigned long size, pgprot_t vma_prot);
601 #define pmd_none(pmd) (!pmd_val(pmd))
603 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
605 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
607 #define pmd_leaf(pmd) (pmd_present(pmd) && !pmd_table(pmd))
608 #define pmd_bad(pmd) (!pmd_table(pmd))
610 #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE)
611 #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE)
613 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3
614 static inline bool pud_sect(pud_t pud) { return false; }
615 static inline bool pud_table(pud_t pud) { return true; }
617 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
619 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
623 extern pgd_t init_pg_dir[PTRS_PER_PGD];
624 extern pgd_t init_pg_end[];
625 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
626 extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
627 extern pgd_t tramp_pg_dir[PTRS_PER_PGD];
628 extern pgd_t reserved_pg_dir[PTRS_PER_PGD];
630 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd);
632 static inline bool in_swapper_pgdir(void *addr)
634 return ((unsigned long)addr & PAGE_MASK) ==
635 ((unsigned long)swapper_pg_dir & PAGE_MASK);
638 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
640 #ifdef __PAGETABLE_PMD_FOLDED
641 if (in_swapper_pgdir(pmdp)) {
642 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd)));
645 #endif /* __PAGETABLE_PMD_FOLDED */
647 WRITE_ONCE(*pmdp, pmd);
649 if (pmd_valid(pmd)) {
655 static inline void pmd_clear(pmd_t *pmdp)
657 set_pmd(pmdp, __pmd(0));
660 static inline phys_addr_t pmd_page_paddr(pmd_t pmd)
662 return __pmd_to_phys(pmd);
665 static inline unsigned long pmd_page_vaddr(pmd_t pmd)
667 return (unsigned long)__va(pmd_page_paddr(pmd));
670 /* Find an entry in the third-level page table. */
671 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t))
673 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr))
674 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr))
675 #define pte_clear_fixmap() clear_fixmap(FIX_PTE)
677 #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd))
679 /* use ONLY for statically allocated translation tables */
680 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr))))
683 * Conversion functions: convert a page and protection to a page entry,
684 * and a page entry and page directory to the page they refer to.
686 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
688 #if CONFIG_PGTABLE_LEVELS > 2
690 #define pmd_ERROR(e) \
691 pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e))
693 #define pud_none(pud) (!pud_val(pud))
694 #define pud_bad(pud) (!pud_table(pud))
695 #define pud_present(pud) pte_present(pud_pte(pud))
696 #define pud_leaf(pud) (pud_present(pud) && !pud_table(pud))
697 #define pud_valid(pud) pte_valid(pud_pte(pud))
698 #define pud_user(pud) pte_user(pud_pte(pud))
699 #define pud_user_exec(pud) pte_user_exec(pud_pte(pud))
701 static inline void set_pud(pud_t *pudp, pud_t pud)
703 #ifdef __PAGETABLE_PUD_FOLDED
704 if (in_swapper_pgdir(pudp)) {
705 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud)));
708 #endif /* __PAGETABLE_PUD_FOLDED */
710 WRITE_ONCE(*pudp, pud);
712 if (pud_valid(pud)) {
718 static inline void pud_clear(pud_t *pudp)
720 set_pud(pudp, __pud(0));
723 static inline phys_addr_t pud_page_paddr(pud_t pud)
725 return __pud_to_phys(pud);
728 static inline pmd_t *pud_pgtable(pud_t pud)
730 return (pmd_t *)__va(pud_page_paddr(pud));
733 /* Find an entry in the second-level page table. */
734 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t))
736 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr))
737 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr))
738 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD)
740 #define pud_page(pud) phys_to_page(__pud_to_phys(pud))
742 /* use ONLY for statically allocated translation tables */
743 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr))))
747 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; })
748 #define pud_user_exec(pud) pud_user(pud) /* Always 0 with folding */
750 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */
751 #define pmd_set_fixmap(addr) NULL
752 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp)
753 #define pmd_clear_fixmap()
755 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir)
757 #endif /* CONFIG_PGTABLE_LEVELS > 2 */
759 #if CONFIG_PGTABLE_LEVELS > 3
761 #define pud_ERROR(e) \
762 pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e))
764 #define p4d_none(p4d) (!p4d_val(p4d))
765 #define p4d_bad(p4d) (!(p4d_val(p4d) & 2))
766 #define p4d_present(p4d) (p4d_val(p4d))
768 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d)
770 if (in_swapper_pgdir(p4dp)) {
771 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d)));
775 WRITE_ONCE(*p4dp, p4d);
780 static inline void p4d_clear(p4d_t *p4dp)
782 set_p4d(p4dp, __p4d(0));
785 static inline phys_addr_t p4d_page_paddr(p4d_t p4d)
787 return __p4d_to_phys(p4d);
790 static inline pud_t *p4d_pgtable(p4d_t p4d)
792 return (pud_t *)__va(p4d_page_paddr(p4d));
795 /* Find an entry in the first-level page table. */
796 #define pud_offset_phys(dir, addr) (p4d_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t))
798 #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr))
799 #define pud_set_fixmap_offset(p4d, addr) pud_set_fixmap(pud_offset_phys(p4d, addr))
800 #define pud_clear_fixmap() clear_fixmap(FIX_PUD)
802 #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d)))
804 /* use ONLY for statically allocated translation tables */
805 #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr))))
809 #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;})
810 #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;})
812 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */
813 #define pud_set_fixmap(addr) NULL
814 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp)
815 #define pud_clear_fixmap()
817 #define pud_offset_kimg(dir,addr) ((pud_t *)dir)
819 #endif /* CONFIG_PGTABLE_LEVELS > 3 */
821 #define pgd_ERROR(e) \
822 pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e))
824 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr))
825 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD)
827 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
830 * Normal and Normal-Tagged are two different memory types and indices
831 * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK.
833 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
834 PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP |
836 /* preserve the hardware dirty information */
837 if (pte_hw_dirty(pte))
838 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY));
840 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
842 * If we end up clearing hw dirtiness for a sw-dirty PTE, set hardware
845 if (pte_sw_dirty(pte))
846 pte = pte_mkdirty(pte);
850 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
852 return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
855 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
856 extern int ptep_set_access_flags(struct vm_area_struct *vma,
857 unsigned long address, pte_t *ptep,
858 pte_t entry, int dirty);
860 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
861 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
862 static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
863 unsigned long address, pmd_t *pmdp,
864 pmd_t entry, int dirty)
866 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty);
869 static inline int pud_devmap(pud_t pud)
874 static inline int pgd_devmap(pgd_t pgd)
880 #ifdef CONFIG_PAGE_TABLE_CHECK
881 static inline bool pte_user_accessible_page(pte_t pte)
883 return pte_present(pte) && (pte_user(pte) || pte_user_exec(pte));
886 static inline bool pmd_user_accessible_page(pmd_t pmd)
888 return pmd_leaf(pmd) && !pmd_present_invalid(pmd) && (pmd_user(pmd) || pmd_user_exec(pmd));
891 static inline bool pud_user_accessible_page(pud_t pud)
893 return pud_leaf(pud) && (pud_user(pud) || pud_user_exec(pud));
898 * Atomic pte/pmd modifications.
900 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
901 static inline int __ptep_test_and_clear_young(pte_t *ptep)
905 pte = READ_ONCE(*ptep);
908 pte = pte_mkold(pte);
909 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
910 pte_val(old_pte), pte_val(pte));
911 } while (pte_val(pte) != pte_val(old_pte));
913 return pte_young(pte);
916 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
917 unsigned long address,
920 return __ptep_test_and_clear_young(ptep);
923 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
924 static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
925 unsigned long address, pte_t *ptep)
927 int young = ptep_test_and_clear_young(vma, address, ptep);
931 * We can elide the trailing DSB here since the worst that can
932 * happen is that a CPU continues to use the young entry in its
933 * TLB and we mistakenly reclaim the associated page. The
934 * window for such an event is bounded by the next
935 * context-switch, which provides a DSB to complete the TLB
938 flush_tlb_page_nosync(vma, address);
944 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
945 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
946 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
947 unsigned long address,
950 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp);
952 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
954 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
955 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
956 unsigned long address, pte_t *ptep)
958 pte_t pte = __pte(xchg_relaxed(&pte_val(*ptep), 0));
960 page_table_check_pte_clear(mm, pte);
965 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
966 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
967 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
968 unsigned long address, pmd_t *pmdp)
970 pmd_t pmd = __pmd(xchg_relaxed(&pmd_val(*pmdp), 0));
972 page_table_check_pmd_clear(mm, pmd);
976 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
979 * ptep_set_wrprotect - mark read-only while trasferring potential hardware
980 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit.
982 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
983 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
987 pte = READ_ONCE(*ptep);
990 pte = pte_wrprotect(pte);
991 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
992 pte_val(old_pte), pte_val(pte));
993 } while (pte_val(pte) != pte_val(old_pte));
996 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
997 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
998 static inline void pmdp_set_wrprotect(struct mm_struct *mm,
999 unsigned long address, pmd_t *pmdp)
1001 ptep_set_wrprotect(mm, address, (pte_t *)pmdp);
1004 #define pmdp_establish pmdp_establish
1005 static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
1006 unsigned long address, pmd_t *pmdp, pmd_t pmd)
1008 page_table_check_pmd_set(vma->vm_mm, pmdp, pmd);
1009 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd)));
1014 * Encode and decode a swap entry:
1015 * bits 0-1: present (must be zero)
1016 * bits 2: remember PG_anon_exclusive
1017 * bits 3-7: swap type
1018 * bits 8-57: swap offset
1019 * bit 58: PTE_PROT_NONE (must be zero)
1021 #define __SWP_TYPE_SHIFT 3
1022 #define __SWP_TYPE_BITS 5
1023 #define __SWP_OFFSET_BITS 50
1024 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
1025 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
1026 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
1028 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
1029 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
1030 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
1032 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
1033 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
1035 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
1036 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) })
1037 #define __swp_entry_to_pmd(swp) __pmd((swp).val)
1038 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
1041 * Ensure that there are not more swap files than can be encoded in the kernel
1044 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
1046 #ifdef CONFIG_ARM64_MTE
1048 #define __HAVE_ARCH_PREPARE_TO_SWAP
1049 static inline int arch_prepare_to_swap(struct page *page)
1051 if (system_supports_mte())
1052 return mte_save_tags(page);
1056 #define __HAVE_ARCH_SWAP_INVALIDATE
1057 static inline void arch_swap_invalidate_page(int type, pgoff_t offset)
1059 if (system_supports_mte())
1060 mte_invalidate_tags(type, offset);
1063 static inline void arch_swap_invalidate_area(int type)
1065 if (system_supports_mte())
1066 mte_invalidate_tags_area(type);
1069 #define __HAVE_ARCH_SWAP_RESTORE
1070 static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio)
1072 if (system_supports_mte())
1073 mte_restore_tags(entry, &folio->page);
1076 #endif /* CONFIG_ARM64_MTE */
1079 * On AArch64, the cache coherency is handled via the set_pte_at() function.
1081 static inline void update_mmu_cache_range(struct vm_fault *vmf,
1082 struct vm_area_struct *vma, unsigned long addr, pte_t *ptep,
1086 * We don't do anything here, so there's a very small chance of
1087 * us retaking a user fault which we just fixed up. The alternative
1088 * is doing a dsb(ishst), but that penalises the fastpath.
1092 #define update_mmu_cache(vma, addr, ptep) \
1093 update_mmu_cache_range(NULL, vma, addr, ptep, 1)
1094 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
1096 #ifdef CONFIG_ARM64_PA_BITS_52
1097 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52)
1099 #define phys_to_ttbr(addr) (addr)
1103 * On arm64 without hardware Access Flag, copying from user will fail because
1104 * the pte is old and cannot be marked young. So we always end up with zeroed
1105 * page after fork() + CoW for pfn mappings. We don't always have a
1106 * hardware-managed access flag on arm64.
1108 #define arch_has_hw_pte_young cpu_has_hw_af
1111 * Experimentally, it's cheap to set the access flag in hardware and we
1112 * benefit from prefaulting mappings as 'old' to start with.
1114 #define arch_wants_old_prefaulted_pte cpu_has_hw_af
1116 static inline bool pud_sect_supported(void)
1118 return PAGE_SIZE == SZ_4K;
1122 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
1123 #define ptep_modify_prot_start ptep_modify_prot_start
1124 extern pte_t ptep_modify_prot_start(struct vm_area_struct *vma,
1125 unsigned long addr, pte_t *ptep);
1127 #define ptep_modify_prot_commit ptep_modify_prot_commit
1128 extern void ptep_modify_prot_commit(struct vm_area_struct *vma,
1129 unsigned long addr, pte_t *ptep,
1130 pte_t old_pte, pte_t new_pte);
1131 #endif /* !__ASSEMBLY__ */
1133 #endif /* __ASM_PGTABLE_H */