2 * Copyright (C) 2012 ARM Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 #ifndef __ASM_PGTABLE_HWDEF_H
17 #define __ASM_PGTABLE_HWDEF_H
19 #include <asm/memory.h>
22 * Number of page-table levels required to address 'va_bits' wide
23 * address, without section mapping. We resolve the top (va_bits - PAGE_SHIFT)
24 * bits with (PAGE_SHIFT - 3) bits at each page table level. Hence:
26 * levels = DIV_ROUND_UP((va_bits - PAGE_SHIFT), (PAGE_SHIFT - 3))
28 * where DIV_ROUND_UP(n, d) => (((n) + (d) - 1) / (d))
30 * We cannot include linux/kernel.h which defines DIV_ROUND_UP here
31 * due to build issues. So we open code DIV_ROUND_UP here:
33 * ((((va_bits) - PAGE_SHIFT) + (PAGE_SHIFT - 3) - 1) / (PAGE_SHIFT - 3))
35 * which gets simplified as :
37 #define ARM64_HW_PGTABLE_LEVELS(va_bits) (((va_bits) - 4) / (PAGE_SHIFT - 3))
40 * Size mapped by an entry at level n ( 0 <= n <= 3)
41 * We map (PAGE_SHIFT - 3) at all translation levels and PAGE_SHIFT bits
42 * in the final page. The maximum number of translation levels supported by
43 * the architecture is 4. Hence, starting at at level n, we have further
44 * ((4 - n) - 1) levels of translation excluding the offset within the page.
45 * So, the total number of bits mapped by an entry at level n is :
47 * ((4 - n) - 1) * (PAGE_SHIFT - 3) + PAGE_SHIFT
49 * Rearranging it a bit we get :
50 * (4 - n) * (PAGE_SHIFT - 3) + 3
52 #define ARM64_HW_PGTABLE_LEVEL_SHIFT(n) ((PAGE_SHIFT - 3) * (4 - (n)) + 3)
54 #define PTRS_PER_PTE (1 << (PAGE_SHIFT - 3))
57 * PMD_SHIFT determines the size a level 2 page table entry can map.
59 #if CONFIG_PGTABLE_LEVELS > 2
60 #define PMD_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(2)
61 #define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)
62 #define PMD_MASK (~(PMD_SIZE-1))
63 #define PTRS_PER_PMD PTRS_PER_PTE
67 * PUD_SHIFT determines the size a level 1 page table entry can map.
69 #if CONFIG_PGTABLE_LEVELS > 3
70 #define PUD_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(1)
71 #define PUD_SIZE (_AC(1, UL) << PUD_SHIFT)
72 #define PUD_MASK (~(PUD_SIZE-1))
73 #define PTRS_PER_PUD PTRS_PER_PTE
77 * PGDIR_SHIFT determines the size a top-level page table entry can map
78 * (depending on the configuration, this level can be 0, 1 or 2).
80 #define PGDIR_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - CONFIG_PGTABLE_LEVELS)
81 #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
82 #define PGDIR_MASK (~(PGDIR_SIZE-1))
83 #ifdef CONFIG_ARM64_USER_VA_BITS_52
84 #define PTRS_PER_PGD (1 << (52 - PGDIR_SHIFT))
86 #define PTRS_PER_PGD (1 << (VA_BITS - PGDIR_SHIFT))
90 * Section address mask and size definitions.
92 #define SECTION_SHIFT PMD_SHIFT
93 #define SECTION_SIZE (_AC(1, UL) << SECTION_SHIFT)
94 #define SECTION_MASK (~(SECTION_SIZE-1))
97 * Contiguous page definitions.
99 #ifdef CONFIG_ARM64_64K_PAGES
100 #define CONT_PTE_SHIFT 5
101 #define CONT_PMD_SHIFT 5
102 #elif defined(CONFIG_ARM64_16K_PAGES)
103 #define CONT_PTE_SHIFT 7
104 #define CONT_PMD_SHIFT 5
106 #define CONT_PTE_SHIFT 4
107 #define CONT_PMD_SHIFT 4
110 #define CONT_PTES (1 << CONT_PTE_SHIFT)
111 #define CONT_PTE_SIZE (CONT_PTES * PAGE_SIZE)
112 #define CONT_PTE_MASK (~(CONT_PTE_SIZE - 1))
113 #define CONT_PMDS (1 << CONT_PMD_SHIFT)
114 #define CONT_PMD_SIZE (CONT_PMDS * PMD_SIZE)
115 #define CONT_PMD_MASK (~(CONT_PMD_SIZE - 1))
116 /* the the numerical offset of the PTE within a range of CONT_PTES */
117 #define CONT_RANGE_OFFSET(addr) (((addr)>>PAGE_SHIFT)&(CONT_PTES-1))
120 * Hardware page table definitions.
122 * Level 1 descriptor (PUD).
124 #define PUD_TYPE_TABLE (_AT(pudval_t, 3) << 0)
125 #define PUD_TABLE_BIT (_AT(pudval_t, 1) << 1)
126 #define PUD_TYPE_MASK (_AT(pudval_t, 3) << 0)
127 #define PUD_TYPE_SECT (_AT(pudval_t, 1) << 0)
130 * Level 2 descriptor (PMD).
132 #define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0)
133 #define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0)
134 #define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0)
135 #define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0)
136 #define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1)
141 #define PMD_SECT_VALID (_AT(pmdval_t, 1) << 0)
142 #define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */
143 #define PMD_SECT_RDONLY (_AT(pmdval_t, 1) << 7) /* AP[2] */
144 #define PMD_SECT_S (_AT(pmdval_t, 3) << 8)
145 #define PMD_SECT_AF (_AT(pmdval_t, 1) << 10)
146 #define PMD_SECT_NG (_AT(pmdval_t, 1) << 11)
147 #define PMD_SECT_CONT (_AT(pmdval_t, 1) << 52)
148 #define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53)
149 #define PMD_SECT_UXN (_AT(pmdval_t, 1) << 54)
152 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
154 #define PMD_ATTRINDX(t) (_AT(pmdval_t, (t)) << 2)
155 #define PMD_ATTRINDX_MASK (_AT(pmdval_t, 7) << 2)
158 * Level 3 descriptor (PTE).
160 #define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0)
161 #define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0)
162 #define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0)
163 #define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1)
164 #define PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */
165 #define PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */
166 #define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */
167 #define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */
168 #define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */
169 #define PTE_DBM (_AT(pteval_t, 1) << 51) /* Dirty Bit Management */
170 #define PTE_CONT (_AT(pteval_t, 1) << 52) /* Contiguous range */
171 #define PTE_PXN (_AT(pteval_t, 1) << 53) /* Privileged XN */
172 #define PTE_UXN (_AT(pteval_t, 1) << 54) /* User XN */
173 #define PTE_HYP_XN (_AT(pteval_t, 1) << 54) /* HYP XN */
175 #define PTE_ADDR_LOW (((_AT(pteval_t, 1) << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT)
176 #ifdef CONFIG_ARM64_PA_BITS_52
177 #define PTE_ADDR_HIGH (_AT(pteval_t, 0xf) << 12)
178 #define PTE_ADDR_MASK (PTE_ADDR_LOW | PTE_ADDR_HIGH)
180 #define PTE_ADDR_MASK PTE_ADDR_LOW
184 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
186 #define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2)
187 #define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2)
190 * 2nd stage PTE definitions
192 #define PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[2:1] */
193 #define PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */
194 #define PTE_S2_XN (_AT(pteval_t, 2) << 53) /* XN[1:0] */
196 #define PMD_S2_RDONLY (_AT(pmdval_t, 1) << 6) /* HAP[2:1] */
197 #define PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */
198 #define PMD_S2_XN (_AT(pmdval_t, 2) << 53) /* XN[1:0] */
201 * Memory Attribute override for Stage-2 (MemAttr[3:0])
203 #define PTE_S2_MEMATTR(t) (_AT(pteval_t, (t)) << 2)
204 #define PTE_S2_MEMATTR_MASK (_AT(pteval_t, 0xf) << 2)
207 * EL2/HYP PTE/PMD definitions
209 #define PMD_HYP PMD_SECT_USER
210 #define PTE_HYP PTE_USER
213 * Highest possible physical address supported.
215 #define PHYS_MASK_SHIFT (CONFIG_ARM64_PA_BITS)
216 #define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)
218 #define TTBR_CNP_BIT (UL(1) << 0)
223 #define TCR_T0SZ_OFFSET 0
224 #define TCR_T1SZ_OFFSET 16
225 #define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_T0SZ_OFFSET)
226 #define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_T1SZ_OFFSET)
227 #define TCR_TxSZ(x) (TCR_T0SZ(x) | TCR_T1SZ(x))
228 #define TCR_TxSZ_WIDTH 6
229 #define TCR_T0SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)
231 #define TCR_EPD0_SHIFT 7
232 #define TCR_EPD0_MASK (UL(1) << TCR_EPD0_SHIFT)
233 #define TCR_IRGN0_SHIFT 8
234 #define TCR_IRGN0_MASK (UL(3) << TCR_IRGN0_SHIFT)
235 #define TCR_IRGN0_NC (UL(0) << TCR_IRGN0_SHIFT)
236 #define TCR_IRGN0_WBWA (UL(1) << TCR_IRGN0_SHIFT)
237 #define TCR_IRGN0_WT (UL(2) << TCR_IRGN0_SHIFT)
238 #define TCR_IRGN0_WBnWA (UL(3) << TCR_IRGN0_SHIFT)
240 #define TCR_EPD1_SHIFT 23
241 #define TCR_EPD1_MASK (UL(1) << TCR_EPD1_SHIFT)
242 #define TCR_IRGN1_SHIFT 24
243 #define TCR_IRGN1_MASK (UL(3) << TCR_IRGN1_SHIFT)
244 #define TCR_IRGN1_NC (UL(0) << TCR_IRGN1_SHIFT)
245 #define TCR_IRGN1_WBWA (UL(1) << TCR_IRGN1_SHIFT)
246 #define TCR_IRGN1_WT (UL(2) << TCR_IRGN1_SHIFT)
247 #define TCR_IRGN1_WBnWA (UL(3) << TCR_IRGN1_SHIFT)
249 #define TCR_IRGN_NC (TCR_IRGN0_NC | TCR_IRGN1_NC)
250 #define TCR_IRGN_WBWA (TCR_IRGN0_WBWA | TCR_IRGN1_WBWA)
251 #define TCR_IRGN_WT (TCR_IRGN0_WT | TCR_IRGN1_WT)
252 #define TCR_IRGN_WBnWA (TCR_IRGN0_WBnWA | TCR_IRGN1_WBnWA)
253 #define TCR_IRGN_MASK (TCR_IRGN0_MASK | TCR_IRGN1_MASK)
256 #define TCR_ORGN0_SHIFT 10
257 #define TCR_ORGN0_MASK (UL(3) << TCR_ORGN0_SHIFT)
258 #define TCR_ORGN0_NC (UL(0) << TCR_ORGN0_SHIFT)
259 #define TCR_ORGN0_WBWA (UL(1) << TCR_ORGN0_SHIFT)
260 #define TCR_ORGN0_WT (UL(2) << TCR_ORGN0_SHIFT)
261 #define TCR_ORGN0_WBnWA (UL(3) << TCR_ORGN0_SHIFT)
263 #define TCR_ORGN1_SHIFT 26
264 #define TCR_ORGN1_MASK (UL(3) << TCR_ORGN1_SHIFT)
265 #define TCR_ORGN1_NC (UL(0) << TCR_ORGN1_SHIFT)
266 #define TCR_ORGN1_WBWA (UL(1) << TCR_ORGN1_SHIFT)
267 #define TCR_ORGN1_WT (UL(2) << TCR_ORGN1_SHIFT)
268 #define TCR_ORGN1_WBnWA (UL(3) << TCR_ORGN1_SHIFT)
270 #define TCR_ORGN_NC (TCR_ORGN0_NC | TCR_ORGN1_NC)
271 #define TCR_ORGN_WBWA (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)
272 #define TCR_ORGN_WT (TCR_ORGN0_WT | TCR_ORGN1_WT)
273 #define TCR_ORGN_WBnWA (TCR_ORGN0_WBnWA | TCR_ORGN1_WBnWA)
274 #define TCR_ORGN_MASK (TCR_ORGN0_MASK | TCR_ORGN1_MASK)
276 #define TCR_SH0_SHIFT 12
277 #define TCR_SH0_MASK (UL(3) << TCR_SH0_SHIFT)
278 #define TCR_SH0_INNER (UL(3) << TCR_SH0_SHIFT)
280 #define TCR_SH1_SHIFT 28
281 #define TCR_SH1_MASK (UL(3) << TCR_SH1_SHIFT)
282 #define TCR_SH1_INNER (UL(3) << TCR_SH1_SHIFT)
283 #define TCR_SHARED (TCR_SH0_INNER | TCR_SH1_INNER)
285 #define TCR_TG0_SHIFT 14
286 #define TCR_TG0_MASK (UL(3) << TCR_TG0_SHIFT)
287 #define TCR_TG0_4K (UL(0) << TCR_TG0_SHIFT)
288 #define TCR_TG0_64K (UL(1) << TCR_TG0_SHIFT)
289 #define TCR_TG0_16K (UL(2) << TCR_TG0_SHIFT)
291 #define TCR_TG1_SHIFT 30
292 #define TCR_TG1_MASK (UL(3) << TCR_TG1_SHIFT)
293 #define TCR_TG1_16K (UL(1) << TCR_TG1_SHIFT)
294 #define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT)
295 #define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT)
297 #define TCR_IPS_SHIFT 32
298 #define TCR_IPS_MASK (UL(7) << TCR_IPS_SHIFT)
299 #define TCR_A1 (UL(1) << 22)
300 #define TCR_ASID16 (UL(1) << 36)
301 #define TCR_TBI0 (UL(1) << 37)
302 #define TCR_HA (UL(1) << 39)
303 #define TCR_HD (UL(1) << 40)
304 #define TCR_NFD1 (UL(1) << 54)
309 #ifdef CONFIG_ARM64_PA_BITS_52
311 * This should be GENMASK_ULL(47, 2).
312 * TTBR_ELx[1] is RES0 in this configuration.
314 #define TTBR_BADDR_MASK_52 (((UL(1) << 46) - 1) << 2)
317 #ifdef CONFIG_ARM64_USER_VA_BITS_52
318 /* Must be at least 64-byte aligned to prevent corruption of the TTBR */
319 #define TTBR1_BADDR_4852_OFFSET (((UL(1) << (52 - PGDIR_SHIFT)) - \
320 (UL(1) << (48 - PGDIR_SHIFT))) * 8)