1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2020 ARM Ltd.
5 #ifndef __ASM_MTE_KASAN_H
6 #define __ASM_MTE_KASAN_H
8 #include <asm/mte-def.h>
12 #include <linux/types.h>
14 #ifdef CONFIG_ARM64_MTE
17 * These functions are meant to be only used from KASAN runtime through
18 * the arch_*() interface defined in asm/memory.h.
19 * These functions don't include system_supports_mte() checks,
20 * as KASAN only calls them when MTE is supported and enabled.
23 static inline u8 mte_get_ptr_tag(void *ptr)
25 /* Note: The format of KASAN tags is 0xF<x> */
26 u8 tag = 0xF0 | (u8)(((u64)(ptr)) >> MTE_TAG_SHIFT);
31 /* Get allocation tag for the address. */
32 static inline u8 mte_get_mem_tag(void *addr)
34 asm(__MTE_PREAMBLE "ldg %0, [%0]"
37 return mte_get_ptr_tag(addr);
40 /* Generate a random tag. */
41 static inline u8 mte_get_random_tag(void)
45 asm(__MTE_PREAMBLE "irg %0, %0"
48 return mte_get_ptr_tag(addr);
51 static inline u64 __stg_post(u64 p)
53 asm volatile(__MTE_PREAMBLE "stg %0, [%0], #16"
60 static inline u64 __stzg_post(u64 p)
62 asm volatile(__MTE_PREAMBLE "stzg %0, [%0], #16"
69 static inline void __dc_gva(u64 p)
71 asm volatile(__MTE_PREAMBLE "dc gva, %0" : : "r"(p) : "memory");
74 static inline void __dc_gzva(u64 p)
76 asm volatile(__MTE_PREAMBLE "dc gzva, %0" : : "r"(p) : "memory");
80 * Assign allocation tags for a region of memory based on the pointer tag.
81 * Note: The address must be non-NULL and MTE_GRANULE_SIZE aligned and
82 * size must be MTE_GRANULE_SIZE aligned.
84 static inline void mte_set_mem_tag_range(void *addr, size_t size, u8 tag,
87 u64 curr, mask, dczid_bs, end1, end2, end3;
89 /* Read DC G(Z)VA block size from the system register. */
90 dczid_bs = 4ul << (read_cpuid(DCZID_EL0) & 0xf);
92 curr = (u64)__tag_set(addr, tag);
94 /* STG/STZG up to the end of the first block. */
97 /* DC GVA / GZVA in [end1, end2) */
101 * The following code uses STG on the first DC GVA block even if the
102 * start address is aligned - it appears to be faster than an alignment
103 * check + conditional branch. Also, if the range size is at least 2 DC
104 * GVA blocks, the first two loops can use post-condition to save one
107 #define SET_MEMTAG_RANGE(stg_post, dc_gva) \
109 if (size >= 2 * dczid_bs) { \
111 curr = stg_post(curr); \
112 } while (curr < end1); \
117 } while (curr < end2); \
120 while (curr < end3) \
121 curr = stg_post(curr); \
125 SET_MEMTAG_RANGE(__stzg_post, __dc_gzva);
127 SET_MEMTAG_RANGE(__stg_post, __dc_gva);
128 #undef SET_MEMTAG_RANGE
131 void mte_enable_kernel_sync(void);
132 void mte_enable_kernel_async(void);
133 void mte_init_tags(u64 max_tag);
135 void mte_set_report_once(bool state);
136 bool mte_report_once(void);
138 #else /* CONFIG_ARM64_MTE */
140 static inline u8 mte_get_ptr_tag(void *ptr)
145 static inline u8 mte_get_mem_tag(void *addr)
150 static inline u8 mte_get_random_tag(void)
155 static inline void mte_set_mem_tag_range(void *addr, size_t size,
160 static inline void mte_enable_kernel_sync(void)
164 static inline void mte_enable_kernel_async(void)
168 static inline void mte_init_tags(u64 max_tag)
172 static inline void mte_set_report_once(bool state)
176 static inline bool mte_report_once(void)
181 #endif /* CONFIG_ARM64_MTE */
183 #endif /* __ASSEMBLY__ */
185 #endif /* __ASM_MTE_KASAN_H */