arch/arm64/include/asm/kvm_host.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2012,2013 - ARM Ltd
   4  * Author: Marc Zyngier <marc.zyngier@arm.com>
   5  *
   6  * Derived from arch/arm/include/asm/kvm_host.h:
   7  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
   8  * Author: Christoffer Dall <c.dall@virtualopensystems.com>
   9  */
  10
  11 #ifndef __ARM64_KVM_HOST_H__
  12 #define __ARM64_KVM_HOST_H__
  13
  14 #include <linux/arm-smccc.h>
  15 #include <linux/bitmap.h>
  16 #include <linux/types.h>
  17 #include <linux/jump_label.h>
  18 #include <linux/kvm_types.h>
  19 #include <linux/maple_tree.h>
  20 #include <linux/percpu.h>
  21 #include <linux/psci.h>
  22 #include <asm/arch_gicv3.h>
  23 #include <asm/barrier.h>
  24 #include <asm/cpufeature.h>
  25 #include <asm/cputype.h>
  26 #include <asm/daifflags.h>
  27 #include <asm/fpsimd.h>
  28 #include <asm/kvm.h>
  29 #include <asm/kvm_asm.h>
  30
  31 #define __KVM_HAVE_ARCH_INTC_INITIALIZED
  32
  33 #define KVM_HALT_POLL_NS_DEFAULT 500000
  34
  35 #include <kvm/arm_vgic.h>
  36 #include <kvm/arm_arch_timer.h>
  37 #include <kvm/arm_pmu.h>
  38
  39 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
  40
  41 #define KVM_VCPU_MAX_FEATURES 7
  42 #define KVM_VCPU_VALID_FEATURES (BIT(KVM_VCPU_MAX_FEATURES) - 1)
  43
  44 #define KVM_REQ_SLEEP \
  45         KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
  46 #define KVM_REQ_IRQ_PENDING     KVM_ARCH_REQ(1)
  47 #define KVM_REQ_VCPU_RESET      KVM_ARCH_REQ(2)
  48 #define KVM_REQ_RECORD_STEAL    KVM_ARCH_REQ(3)
  49 #define KVM_REQ_RELOAD_GICv4    KVM_ARCH_REQ(4)
  50 #define KVM_REQ_RELOAD_PMU      KVM_ARCH_REQ(5)
  51 #define KVM_REQ_SUSPEND         KVM_ARCH_REQ(6)
  52
  53 #define KVM_DIRTY_LOG_MANUAL_CAPS   (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \
  54                                      KVM_DIRTY_LOG_INITIALLY_SET)
  55
  56 #define KVM_HAVE_MMU_RWLOCK
  57
  58 /*
  59  * Mode of operation configurable with kvm-arm.mode early param.
  60  * See Documentation/admin-guide/kernel-parameters.txt for more information.
  61  */
  62 enum kvm_mode {
  63         KVM_MODE_DEFAULT,
  64         KVM_MODE_PROTECTED,
  65         KVM_MODE_NV,
  66         KVM_MODE_NONE,
  67 };
  68 #ifdef CONFIG_KVM
  69 enum kvm_mode kvm_get_mode(void);
  70 #else
  71 static inline enum kvm_mode kvm_get_mode(void) { return KVM_MODE_NONE; };
  72 #endif
  73
  74 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
  75
  76 extern unsigned int __ro_after_init kvm_sve_max_vl;
  77 int __init kvm_arm_init_sve(void);
  78
  79 u32 __attribute_const__ kvm_target_cpu(void);
  80 int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
  81 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu);
  82
  83 struct kvm_hyp_memcache {
  84         phys_addr_t head;
  85         unsigned long nr_pages;
  86 };
  87
  88 static inline void push_hyp_memcache(struct kvm_hyp_memcache *mc,
  89                                      phys_addr_t *p,
  90                                      phys_addr_t (*to_pa)(void *virt))
  91 {
  92         *p = mc->head;
  93         mc->head = to_pa(p);
  94         mc->nr_pages++;
  95 }
  96
  97 static inline void *pop_hyp_memcache(struct kvm_hyp_memcache *mc,
  98                                      void *(*to_va)(phys_addr_t phys))
  99 {
 100         phys_addr_t *p = to_va(mc->head);
 101
 102         if (!mc->nr_pages)
 103                 return NULL;
 104
 105         mc->head = *p;
 106         mc->nr_pages--;
 107
 108         return p;
 109 }
 110
 111 static inline int __topup_hyp_memcache(struct kvm_hyp_memcache *mc,
 112                                        unsigned long min_pages,
 113                                        void *(*alloc_fn)(void *arg),
 114                                        phys_addr_t (*to_pa)(void *virt),
 115                                        void *arg)
 116 {
 117         while (mc->nr_pages < min_pages) {
 118                 phys_addr_t *p = alloc_fn(arg);
 119
 120                 if (!p)
 121                         return -ENOMEM;
 122                 push_hyp_memcache(mc, p, to_pa);
 123         }
 124
 125         return 0;
 126 }
 127
 128 static inline void __free_hyp_memcache(struct kvm_hyp_memcache *mc,
 129                                        void (*free_fn)(void *virt, void *arg),
 130                                        void *(*to_va)(phys_addr_t phys),
 131                                        void *arg)
 132 {
 133         while (mc->nr_pages)
 134                 free_fn(pop_hyp_memcache(mc, to_va), arg);
 135 }
 136
 137 void free_hyp_memcache(struct kvm_hyp_memcache *mc);
 138 int topup_hyp_memcache(struct kvm_hyp_memcache *mc, unsigned long min_pages);
 139
 140 struct kvm_vmid {
 141         atomic64_t id;
 142 };
 143
 144 struct kvm_s2_mmu {
 145         struct kvm_vmid vmid;
 146
 147         /*
 148          * stage2 entry level table
 149          *
 150          * Two kvm_s2_mmu structures in the same VM can point to the same
 151          * pgd here.  This happens when running a guest using a
 152          * translation regime that isn't affected by its own stage-2
 153          * translation, such as a non-VHE hypervisor running at vEL2, or
 154          * for vEL1/EL0 with vHCR_EL2.VM == 0.  In that case, we use the
 155          * canonical stage-2 page tables.
 156          */
 157         phys_addr_t     pgd_phys;
 158         struct kvm_pgtable *pgt;
 159
 160         /* The last vcpu id that ran on each physical CPU */
 161         int __percpu *last_vcpu_ran;
 162
 163         struct kvm_arch *arch;
 164 };
 165
 166 struct kvm_arch_memory_slot {
 167 };
 168
 169 /**
 170  * struct kvm_smccc_features: Descriptor of the hypercall services exposed to the guests
 171  *
 172  * @std_bmap: Bitmap of standard secure service calls
 173  * @std_hyp_bmap: Bitmap of standard hypervisor service calls
 174  * @vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls
 175  */
 176 struct kvm_smccc_features {
 177         unsigned long std_bmap;
 178         unsigned long std_hyp_bmap;
 179         unsigned long vendor_hyp_bmap;
 180 };
 181
 182 typedef unsigned int pkvm_handle_t;
 183
 184 struct kvm_protected_vm {
 185         pkvm_handle_t handle;
 186         struct kvm_hyp_memcache teardown_mc;
 187 };
 188
 189 struct kvm_arch {
 190         struct kvm_s2_mmu mmu;
 191
 192         /* VTCR_EL2 value for this VM */
 193         u64    vtcr;
 194
 195         /* Interrupt controller */
 196         struct vgic_dist        vgic;
 197
 198         /* Timers */
 199         struct arch_timer_vm_data timer_data;
 200
 201         /* Mandated version of PSCI */
 202         u32 psci_version;
 203
 204         /* Protects VM-scoped configuration data */
 205         struct mutex config_lock;
 206
 207         /*
 208          * If we encounter a data abort without valid instruction syndrome
 209          * information, report this to user space.  User space can (and
 210          * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is
 211          * supported.
 212          */
 213 #define KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER      0
 214         /* Memory Tagging Extension enabled for the guest */
 215 #define KVM_ARCH_FLAG_MTE_ENABLED                       1
 216         /* At least one vCPU has ran in the VM */
 217 #define KVM_ARCH_FLAG_HAS_RAN_ONCE                      2
 218         /* The vCPU feature set for the VM is configured */
 219 #define KVM_ARCH_FLAG_VCPU_FEATURES_CONFIGURED          3
 220         /* PSCI SYSTEM_SUSPEND enabled for the guest */
 221 #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED            4
 222         /* VM counter offset */
 223 #define KVM_ARCH_FLAG_VM_COUNTER_OFFSET                 5
 224         /* Timer PPIs made immutable */
 225 #define KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE              6
 226         /* SMCCC filter initialized for the VM */
 227 #define KVM_ARCH_FLAG_SMCCC_FILTER_CONFIGURED           7
 228         unsigned long flags;
 229
 230         /* VM-wide vCPU feature set */
 231         DECLARE_BITMAP(vcpu_features, KVM_VCPU_MAX_FEATURES);
 232
 233         /*
 234          * VM-wide PMU filter, implemented as a bitmap and big enough for
 235          * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+).
 236          */
 237         unsigned long *pmu_filter;
 238         struct arm_pmu *arm_pmu;
 239
 240         cpumask_var_t supported_cpus;
 241
 242         u8 pfr0_csv2;
 243         u8 pfr0_csv3;
 244         struct {
 245                 u8 imp:4;
 246                 u8 unimp:4;
 247         } dfr0_pmuver;
 248
 249         /* Hypercall features firmware registers' descriptor */
 250         struct kvm_smccc_features smccc_feat;
 251         struct maple_tree smccc_filter;
 252
 253         /*
 254          * For an untrusted host VM, 'pkvm.handle' is used to lookup
 255          * the associated pKVM instance in the hypervisor.
 256          */
 257         struct kvm_protected_vm pkvm;
 258 };
 259
 260 struct kvm_vcpu_fault_info {
 261         u64 esr_el2;            /* Hyp Syndrom Register */
 262         u64 far_el2;            /* Hyp Fault Address Register */
 263         u64 hpfar_el2;          /* Hyp IPA Fault Address Register */
 264         u64 disr_el1;           /* Deferred [SError] Status Register */
 265 };
 266
 267 enum vcpu_sysreg {
 268         __INVALID_SYSREG__,   /* 0 is reserved as an invalid value */
 269         MPIDR_EL1,      /* MultiProcessor Affinity Register */
 270         CLIDR_EL1,      /* Cache Level ID Register */
 271         CSSELR_EL1,     /* Cache Size Selection Register */
 272         SCTLR_EL1,      /* System Control Register */
 273         ACTLR_EL1,      /* Auxiliary Control Register */
 274         CPACR_EL1,      /* Coprocessor Access Control */
 275         ZCR_EL1,        /* SVE Control */
 276         TTBR0_EL1,      /* Translation Table Base Register 0 */
 277         TTBR1_EL1,      /* Translation Table Base Register 1 */
 278         TCR_EL1,        /* Translation Control Register */
 279         ESR_EL1,        /* Exception Syndrome Register */
 280         AFSR0_EL1,      /* Auxiliary Fault Status Register 0 */
 281         AFSR1_EL1,      /* Auxiliary Fault Status Register 1 */
 282         FAR_EL1,        /* Fault Address Register */
 283         MAIR_EL1,       /* Memory Attribute Indirection Register */
 284         VBAR_EL1,       /* Vector Base Address Register */
 285         CONTEXTIDR_EL1, /* Context ID Register */
 286         TPIDR_EL0,      /* Thread ID, User R/W */
 287         TPIDRRO_EL0,    /* Thread ID, User R/O */
 288         TPIDR_EL1,      /* Thread ID, Privileged */
 289         AMAIR_EL1,      /* Aux Memory Attribute Indirection Register */
 290         CNTKCTL_EL1,    /* Timer Control Register (EL1) */
 291         PAR_EL1,        /* Physical Address Register */
 292         MDSCR_EL1,      /* Monitor Debug System Control Register */
 293         MDCCINT_EL1,    /* Monitor Debug Comms Channel Interrupt Enable Reg */
 294         OSLSR_EL1,      /* OS Lock Status Register */
 295         DISR_EL1,       /* Deferred Interrupt Status Register */
 296
 297         /* Performance Monitors Registers */
 298         PMCR_EL0,       /* Control Register */
 299         PMSELR_EL0,     /* Event Counter Selection Register */
 300         PMEVCNTR0_EL0,  /* Event Counter Register (0-30) */
 301         PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
 302         PMCCNTR_EL0,    /* Cycle Counter Register */
 303         PMEVTYPER0_EL0, /* Event Type Register (0-30) */
 304         PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
 305         PMCCFILTR_EL0,  /* Cycle Count Filter Register */
 306         PMCNTENSET_EL0, /* Count Enable Set Register */
 307         PMINTENSET_EL1, /* Interrupt Enable Set Register */
 308         PMOVSSET_EL0,   /* Overflow Flag Status Set Register */
 309         PMUSERENR_EL0,  /* User Enable Register */
 310
 311         /* Pointer Authentication Registers in a strict increasing order. */
 312         APIAKEYLO_EL1,
 313         APIAKEYHI_EL1,
 314         APIBKEYLO_EL1,
 315         APIBKEYHI_EL1,
 316         APDAKEYLO_EL1,
 317         APDAKEYHI_EL1,
 318         APDBKEYLO_EL1,
 319         APDBKEYHI_EL1,
 320         APGAKEYLO_EL1,
 321         APGAKEYHI_EL1,
 322
 323         ELR_EL1,
 324         SP_EL1,
 325         SPSR_EL1,
 326
 327         CNTVOFF_EL2,
 328         CNTV_CVAL_EL0,
 329         CNTV_CTL_EL0,
 330         CNTP_CVAL_EL0,
 331         CNTP_CTL_EL0,
 332
 333         /* Memory Tagging Extension registers */
 334         RGSR_EL1,       /* Random Allocation Tag Seed Register */
 335         GCR_EL1,        /* Tag Control Register */
 336         TFSR_EL1,       /* Tag Fault Status Register (EL1) */
 337         TFSRE0_EL1,     /* Tag Fault Status Register (EL0) */
 338
 339         /* 32bit specific registers. */
 340         DACR32_EL2,     /* Domain Access Control Register */
 341         IFSR32_EL2,     /* Instruction Fault Status Register */
 342         FPEXC32_EL2,    /* Floating-Point Exception Control Register */
 343         DBGVCR32_EL2,   /* Debug Vector Catch Register */
 344
 345         /* EL2 registers */
 346         VPIDR_EL2,      /* Virtualization Processor ID Register */
 347         VMPIDR_EL2,     /* Virtualization Multiprocessor ID Register */
 348         SCTLR_EL2,      /* System Control Register (EL2) */
 349         ACTLR_EL2,      /* Auxiliary Control Register (EL2) */
 350         HCR_EL2,        /* Hypervisor Configuration Register */
 351         MDCR_EL2,       /* Monitor Debug Configuration Register (EL2) */
 352         CPTR_EL2,       /* Architectural Feature Trap Register (EL2) */
 353         HSTR_EL2,       /* Hypervisor System Trap Register */
 354         HACR_EL2,       /* Hypervisor Auxiliary Control Register */
 355         TTBR0_EL2,      /* Translation Table Base Register 0 (EL2) */
 356         TTBR1_EL2,      /* Translation Table Base Register 1 (EL2) */
 357         TCR_EL2,        /* Translation Control Register (EL2) */
 358         VTTBR_EL2,      /* Virtualization Translation Table Base Register */
 359         VTCR_EL2,       /* Virtualization Translation Control Register */
 360         SPSR_EL2,       /* EL2 saved program status register */
 361         ELR_EL2,        /* EL2 exception link register */
 362         AFSR0_EL2,      /* Auxiliary Fault Status Register 0 (EL2) */
 363         AFSR1_EL2,      /* Auxiliary Fault Status Register 1 (EL2) */
 364         ESR_EL2,        /* Exception Syndrome Register (EL2) */
 365         FAR_EL2,        /* Fault Address Register (EL2) */
 366         HPFAR_EL2,      /* Hypervisor IPA Fault Address Register */
 367         MAIR_EL2,       /* Memory Attribute Indirection Register (EL2) */
 368         AMAIR_EL2,      /* Auxiliary Memory Attribute Indirection Register (EL2) */
 369         VBAR_EL2,       /* Vector Base Address Register (EL2) */
 370         RVBAR_EL2,      /* Reset Vector Base Address Register */
 371         CONTEXTIDR_EL2, /* Context ID Register (EL2) */
 372         TPIDR_EL2,      /* EL2 Software Thread ID Register */
 373         CNTHCTL_EL2,    /* Counter-timer Hypervisor Control register */
 374         SP_EL2,         /* EL2 Stack Pointer */
 375         CNTHP_CTL_EL2,
 376         CNTHP_CVAL_EL2,
 377         CNTHV_CTL_EL2,
 378         CNTHV_CVAL_EL2,
 379
 380         NR_SYS_REGS     /* Nothing after this line! */
 381 };
 382
 383 struct kvm_cpu_context {
 384         struct user_pt_regs regs;       /* sp = sp_el0 */
 385
 386         u64     spsr_abt;
 387         u64     spsr_und;
 388         u64     spsr_irq;
 389         u64     spsr_fiq;
 390
 391         struct user_fpsimd_state fp_regs;
 392
 393         u64 sys_regs[NR_SYS_REGS];
 394
 395         struct kvm_vcpu *__hyp_running_vcpu;
 396 };
 397
 398 struct kvm_host_data {
 399         struct kvm_cpu_context host_ctxt;
 400 };
 401
 402 struct kvm_host_psci_config {
 403         /* PSCI version used by host. */
 404         u32 version;
 405
 406         /* Function IDs used by host if version is v0.1. */
 407         struct psci_0_1_function_ids function_ids_0_1;
 408
 409         bool psci_0_1_cpu_suspend_implemented;
 410         bool psci_0_1_cpu_on_implemented;
 411         bool psci_0_1_cpu_off_implemented;
 412         bool psci_0_1_migrate_implemented;
 413 };
 414
 415 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config);
 416 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config)
 417
 418 extern s64 kvm_nvhe_sym(hyp_physvirt_offset);
 419 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset)
 420
 421 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS];
 422 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map)
 423
 424 struct vcpu_reset_state {
 425         unsigned long   pc;
 426         unsigned long   r0;
 427         bool            be;
 428         bool            reset;
 429 };
 430
 431 struct kvm_vcpu_arch {
 432         struct kvm_cpu_context ctxt;
 433
 434         /*
 435          * Guest floating point state
 436          *
 437          * The architecture has two main floating point extensions,
 438          * the original FPSIMD and SVE.  These have overlapping
 439          * register views, with the FPSIMD V registers occupying the
 440          * low 128 bits of the SVE Z registers.  When the core
 441          * floating point code saves the register state of a task it
 442          * records which view it saved in fp_type.
 443          */
 444         void *sve_state;
 445         enum fp_type fp_type;
 446         unsigned int sve_max_vl;
 447         u64 svcr;
 448
 449         /* Stage 2 paging state used by the hardware on next switch */
 450         struct kvm_s2_mmu *hw_mmu;
 451
 452         /* Values of trap registers for the guest. */
 453         u64 hcr_el2;
 454         u64 mdcr_el2;
 455         u64 cptr_el2;
 456
 457         /* Values of trap registers for the host before guest entry. */
 458         u64 mdcr_el2_host;
 459
 460         /* Exception Information */
 461         struct kvm_vcpu_fault_info fault;
 462
 463         /* Ownership of the FP regs */
 464         enum {
 465                 FP_STATE_FREE,
 466                 FP_STATE_HOST_OWNED,
 467                 FP_STATE_GUEST_OWNED,
 468         } fp_state;
 469
 470         /* Configuration flags, set once and for all before the vcpu can run */
 471         u8 cflags;
 472
 473         /* Input flags to the hypervisor code, potentially cleared after use */
 474         u8 iflags;
 475
 476         /* State flags for kernel bookkeeping, unused by the hypervisor code */
 477         u8 sflags;
 478
 479         /*
 480          * Don't run the guest (internal implementation need).
 481          *
 482          * Contrary to the flags above, this is set/cleared outside of
 483          * a vcpu context, and thus cannot be mixed with the flags
 484          * themselves (or the flag accesses need to be made atomic).
 485          */
 486         bool pause;
 487
 488         /*
 489          * We maintain more than a single set of debug registers to support
 490          * debugging the guest from the host and to maintain separate host and
 491          * guest state during world switches. vcpu_debug_state are the debug
 492          * registers of the vcpu as the guest sees them.  host_debug_state are
 493          * the host registers which are saved and restored during
 494          * world switches. external_debug_state contains the debug
 495          * values we want to debug the guest. This is set via the
 496          * KVM_SET_GUEST_DEBUG ioctl.
 497          *
 498          * debug_ptr points to the set of debug registers that should be loaded
 499          * onto the hardware when running the guest.
 500          */
 501         struct kvm_guest_debug_arch *debug_ptr;
 502         struct kvm_guest_debug_arch vcpu_debug_state;
 503         struct kvm_guest_debug_arch external_debug_state;
 504
 505         struct user_fpsimd_state *host_fpsimd_state;    /* hyp VA */
 506         struct task_struct *parent_task;
 507
 508         struct {
 509                 /* {Break,watch}point registers */
 510                 struct kvm_guest_debug_arch regs;
 511                 /* Statistical profiling extension */
 512                 u64 pmscr_el1;
 513                 /* Self-hosted trace */
 514                 u64 trfcr_el1;
 515         } host_debug_state;
 516
 517         /* VGIC state */
 518         struct vgic_cpu vgic_cpu;
 519         struct arch_timer_cpu timer_cpu;
 520         struct kvm_pmu pmu;
 521
 522         /*
 523          * Guest registers we preserve during guest debugging.
 524          *
 525          * These shadow registers are updated by the kvm_handle_sys_reg
 526          * trap handler if the guest accesses or updates them while we
 527          * are using guest debug.
 528          */
 529         struct {
 530                 u32     mdscr_el1;
 531                 bool    pstate_ss;
 532         } guest_debug_preserved;
 533
 534         /* vcpu power state */
 535         struct kvm_mp_state mp_state;
 536         spinlock_t mp_state_lock;
 537
 538         /* Cache some mmu pages needed inside spinlock regions */
 539         struct kvm_mmu_memory_cache mmu_page_cache;
 540
 541         /* Target CPU and feature flags */
 542         int target;
 543         DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
 544
 545         /* Virtual SError ESR to restore when HCR_EL2.VSE is set */
 546         u64 vsesr_el2;
 547
 548         /* Additional reset state */
 549         struct vcpu_reset_state reset_state;
 550
 551         /* Guest PV state */
 552         struct {
 553                 u64 last_steal;
 554                 gpa_t base;
 555         } steal;
 556
 557         /* Per-vcpu CCSIDR override or NULL */
 558         u32 *ccsidr;
 559 };
 560
 561 /*
 562  * Each 'flag' is composed of a comma-separated triplet:
 563  *
 564  * - the flag-set it belongs to in the vcpu->arch structure
 565  * - the value for that flag
 566  * - the mask for that flag
 567  *
 568  *  __vcpu_single_flag() builds such a triplet for a single-bit flag.
 569  * unpack_vcpu_flag() extract the flag value from the triplet for
 570  * direct use outside of the flag accessors.
 571  */
 572 #define __vcpu_single_flag(_set, _f)    _set, (_f), (_f)
 573
 574 #define __unpack_flag(_set, _f, _m)     _f
 575 #define unpack_vcpu_flag(...)           __unpack_flag(__VA_ARGS__)
 576
 577 #define __build_check_flag(v, flagset, f, m)                    \
 578         do {                                                    \
 579                 typeof(v->arch.flagset) *_fset;                 \
 580                                                                 \
 581                 /* Check that the flags fit in the mask */      \
 582                 BUILD_BUG_ON(HWEIGHT(m) != HWEIGHT((f) | (m))); \
 583                 /* Check that the flags fit in the type */      \
 584                 BUILD_BUG_ON((sizeof(*_fset) * 8) <= __fls(m)); \
 585         } while (0)
 586
 587 #define __vcpu_get_flag(v, flagset, f, m)                       \
 588         ({                                                      \
 589                 __build_check_flag(v, flagset, f, m);           \
 590                                                                 \
 591                 READ_ONCE(v->arch.flagset) & (m);               \
 592         })
 593
 594 /*
 595  * Note that the set/clear accessors must be preempt-safe in order to
 596  * avoid nesting them with load/put which also manipulate flags...
 597  */
 598 #ifdef __KVM_NVHE_HYPERVISOR__
 599 /* the nVHE hypervisor is always non-preemptible */
 600 #define __vcpu_flags_preempt_disable()
 601 #define __vcpu_flags_preempt_enable()
 602 #else
 603 #define __vcpu_flags_preempt_disable()  preempt_disable()
 604 #define __vcpu_flags_preempt_enable()   preempt_enable()
 605 #endif
 606
 607 #define __vcpu_set_flag(v, flagset, f, m)                       \
 608         do {                                                    \
 609                 typeof(v->arch.flagset) *fset;                  \
 610                                                                 \
 611                 __build_check_flag(v, flagset, f, m);           \
 612                                                                 \
 613                 fset = &v->arch.flagset;                        \
 614                 __vcpu_flags_preempt_disable();                 \
 615                 if (HWEIGHT(m) > 1)                             \
 616                         *fset &= ~(m);                          \
 617                 *fset |= (f);                                   \
 618                 __vcpu_flags_preempt_enable();                  \
 619         } while (0)
 620
 621 #define __vcpu_clear_flag(v, flagset, f, m)                     \
 622         do {                                                    \
 623                 typeof(v->arch.flagset) *fset;                  \
 624                                                                 \
 625                 __build_check_flag(v, flagset, f, m);           \
 626                                                                 \
 627                 fset = &v->arch.flagset;                        \
 628                 __vcpu_flags_preempt_disable();                 \
 629                 *fset &= ~(m);                                  \
 630                 __vcpu_flags_preempt_enable();                  \
 631         } while (0)
 632
 633 #define vcpu_get_flag(v, ...)   __vcpu_get_flag((v), __VA_ARGS__)
 634 #define vcpu_set_flag(v, ...)   __vcpu_set_flag((v), __VA_ARGS__)
 635 #define vcpu_clear_flag(v, ...) __vcpu_clear_flag((v), __VA_ARGS__)
 636
 637 /* SVE exposed to guest */
 638 #define GUEST_HAS_SVE           __vcpu_single_flag(cflags, BIT(0))
 639 /* SVE config completed */
 640 #define VCPU_SVE_FINALIZED      __vcpu_single_flag(cflags, BIT(1))
 641 /* PTRAUTH exposed to guest */
 642 #define GUEST_HAS_PTRAUTH       __vcpu_single_flag(cflags, BIT(2))
 643
 644 /* Exception pending */
 645 #define PENDING_EXCEPTION       __vcpu_single_flag(iflags, BIT(0))
 646 /*
 647  * PC increment. Overlaps with EXCEPT_MASK on purpose so that it can't
 648  * be set together with an exception...
 649  */
 650 #define INCREMENT_PC            __vcpu_single_flag(iflags, BIT(1))
 651 /* Target EL/MODE (not a single flag, but let's abuse the macro) */
 652 #define EXCEPT_MASK             __vcpu_single_flag(iflags, GENMASK(3, 1))
 653
 654 /* Helpers to encode exceptions with minimum fuss */
 655 #define __EXCEPT_MASK_VAL       unpack_vcpu_flag(EXCEPT_MASK)
 656 #define __EXCEPT_SHIFT          __builtin_ctzl(__EXCEPT_MASK_VAL)
 657 #define __vcpu_except_flags(_f) iflags, (_f << __EXCEPT_SHIFT), __EXCEPT_MASK_VAL
 658
 659 /*
 660  * When PENDING_EXCEPTION is set, EXCEPT_MASK can take the following
 661  * values:
 662  *
 663  * For AArch32 EL1:
 664  */
 665 #define EXCEPT_AA32_UND         __vcpu_except_flags(0)
 666 #define EXCEPT_AA32_IABT        __vcpu_except_flags(1)
 667 #define EXCEPT_AA32_DABT        __vcpu_except_flags(2)
 668 /* For AArch64: */
 669 #define EXCEPT_AA64_EL1_SYNC    __vcpu_except_flags(0)
 670 #define EXCEPT_AA64_EL1_IRQ     __vcpu_except_flags(1)
 671 #define EXCEPT_AA64_EL1_FIQ     __vcpu_except_flags(2)
 672 #define EXCEPT_AA64_EL1_SERR    __vcpu_except_flags(3)
 673 /* For AArch64 with NV: */
 674 #define EXCEPT_AA64_EL2_SYNC    __vcpu_except_flags(4)
 675 #define EXCEPT_AA64_EL2_IRQ     __vcpu_except_flags(5)
 676 #define EXCEPT_AA64_EL2_FIQ     __vcpu_except_flags(6)
 677 #define EXCEPT_AA64_EL2_SERR    __vcpu_except_flags(7)
 678 /* Guest debug is live */
 679 #define DEBUG_DIRTY             __vcpu_single_flag(iflags, BIT(4))
 680 /* Save SPE context if active  */
 681 #define DEBUG_STATE_SAVE_SPE    __vcpu_single_flag(iflags, BIT(5))
 682 /* Save TRBE context if active  */
 683 #define DEBUG_STATE_SAVE_TRBE   __vcpu_single_flag(iflags, BIT(6))
 684 /* vcpu running in HYP context */
 685 #define VCPU_HYP_CONTEXT        __vcpu_single_flag(iflags, BIT(7))
 686
 687 /* SVE enabled for host EL0 */
 688 #define HOST_SVE_ENABLED        __vcpu_single_flag(sflags, BIT(0))
 689 /* SME enabled for EL0 */
 690 #define HOST_SME_ENABLED        __vcpu_single_flag(sflags, BIT(1))
 691 /* Physical CPU not in supported_cpus */
 692 #define ON_UNSUPPORTED_CPU      __vcpu_single_flag(sflags, BIT(2))
 693 /* WFIT instruction trapped */
 694 #define IN_WFIT                 __vcpu_single_flag(sflags, BIT(3))
 695 /* vcpu system registers loaded on physical CPU */
 696 #define SYSREGS_ON_CPU          __vcpu_single_flag(sflags, BIT(4))
 697 /* Software step state is Active-pending */
 698 #define DBG_SS_ACTIVE_PENDING   __vcpu_single_flag(sflags, BIT(5))
 699
 700
 701 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */
 702 #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) +      \
 703                              sve_ffr_offset((vcpu)->arch.sve_max_vl))
 704
 705 #define vcpu_sve_max_vq(vcpu)   sve_vq_from_vl((vcpu)->arch.sve_max_vl)
 706
 707 #define vcpu_sve_state_size(vcpu) ({                                    \
 708         size_t __size_ret;                                              \
 709         unsigned int __vcpu_vq;                                         \
 710                                                                         \
 711         if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) {          \
 712                 __size_ret = 0;                                         \
 713         } else {                                                        \
 714                 __vcpu_vq = vcpu_sve_max_vq(vcpu);                      \
 715                 __size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq);              \
 716         }                                                               \
 717                                                                         \
 718         __size_ret;                                                     \
 719 })
 720
 721 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \
 722                                  KVM_GUESTDBG_USE_SW_BP | \
 723                                  KVM_GUESTDBG_USE_HW | \
 724                                  KVM_GUESTDBG_SINGLESTEP)
 725
 726 #define vcpu_has_sve(vcpu) (system_supports_sve() &&                    \
 727                             vcpu_get_flag(vcpu, GUEST_HAS_SVE))
 728
 729 #ifdef CONFIG_ARM64_PTR_AUTH
 730 #define vcpu_has_ptrauth(vcpu)                                          \
 731         ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) ||                \
 732           cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) &&               \
 733           vcpu_get_flag(vcpu, GUEST_HAS_PTRAUTH))
 734 #else
 735 #define vcpu_has_ptrauth(vcpu)          false
 736 #endif
 737
 738 #define vcpu_on_unsupported_cpu(vcpu)                                   \
 739         vcpu_get_flag(vcpu, ON_UNSUPPORTED_CPU)
 740
 741 #define vcpu_set_on_unsupported_cpu(vcpu)                               \
 742         vcpu_set_flag(vcpu, ON_UNSUPPORTED_CPU)
 743
 744 #define vcpu_clear_on_unsupported_cpu(vcpu)                             \
 745         vcpu_clear_flag(vcpu, ON_UNSUPPORTED_CPU)
 746
 747 #define vcpu_gp_regs(v)         (&(v)->arch.ctxt.regs)
 748
 749 /*
 750  * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the
 751  * memory backed version of a register, and not the one most recently
 752  * accessed by a running VCPU.  For example, for userspace access or
 753  * for system registers that are never context switched, but only
 754  * emulated.
 755  */
 756 #define __ctxt_sys_reg(c,r)     (&(c)->sys_regs[(r)])
 757
 758 #define ctxt_sys_reg(c,r)       (*__ctxt_sys_reg(c,r))
 759
 760 #define __vcpu_sys_reg(v,r)     (ctxt_sys_reg(&(v)->arch.ctxt, (r)))
 761
 762 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg);
 763 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg);
 764
 765 static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val)
 766 {
 767         /*
 768          * *** VHE ONLY ***
 769          *
 770          * System registers listed in the switch are not saved on every
 771          * exit from the guest but are only saved on vcpu_put.
 772          *
 773          * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
 774          * should never be listed below, because the guest cannot modify its
 775          * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's
 776          * thread when emulating cross-VCPU communication.
 777          */
 778         if (!has_vhe())
 779                 return false;
 780
 781         switch (reg) {
 782         case SCTLR_EL1:         *val = read_sysreg_s(SYS_SCTLR_EL12);   break;
 783         case CPACR_EL1:         *val = read_sysreg_s(SYS_CPACR_EL12);   break;
 784         case TTBR0_EL1:         *val = read_sysreg_s(SYS_TTBR0_EL12);   break;
 785         case TTBR1_EL1:         *val = read_sysreg_s(SYS_TTBR1_EL12);   break;
 786         case TCR_EL1:           *val = read_sysreg_s(SYS_TCR_EL12);     break;
 787         case ESR_EL1:           *val = read_sysreg_s(SYS_ESR_EL12);     break;
 788         case AFSR0_EL1:         *val = read_sysreg_s(SYS_AFSR0_EL12);   break;
 789         case AFSR1_EL1:         *val = read_sysreg_s(SYS_AFSR1_EL12);   break;
 790         case FAR_EL1:           *val = read_sysreg_s(SYS_FAR_EL12);     break;
 791         case MAIR_EL1:          *val = read_sysreg_s(SYS_MAIR_EL12);    break;
 792         case VBAR_EL1:          *val = read_sysreg_s(SYS_VBAR_EL12);    break;
 793         case CONTEXTIDR_EL1:    *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break;
 794         case TPIDR_EL0:         *val = read_sysreg_s(SYS_TPIDR_EL0);    break;
 795         case TPIDRRO_EL0:       *val = read_sysreg_s(SYS_TPIDRRO_EL0);  break;
 796         case TPIDR_EL1:         *val = read_sysreg_s(SYS_TPIDR_EL1);    break;
 797         case AMAIR_EL1:         *val = read_sysreg_s(SYS_AMAIR_EL12);   break;
 798         case CNTKCTL_EL1:       *val = read_sysreg_s(SYS_CNTKCTL_EL12); break;
 799         case ELR_EL1:           *val = read_sysreg_s(SYS_ELR_EL12);     break;
 800         case PAR_EL1:           *val = read_sysreg_par();               break;
 801         case DACR32_EL2:        *val = read_sysreg_s(SYS_DACR32_EL2);   break;
 802         case IFSR32_EL2:        *val = read_sysreg_s(SYS_IFSR32_EL2);   break;
 803         case DBGVCR32_EL2:      *val = read_sysreg_s(SYS_DBGVCR32_EL2); break;
 804         default:                return false;
 805         }
 806
 807         return true;
 808 }
 809
 810 static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg)
 811 {
 812         /*
 813          * *** VHE ONLY ***
 814          *
 815          * System registers listed in the switch are not restored on every
 816          * entry to the guest but are only restored on vcpu_load.
 817          *
 818          * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
 819          * should never be listed below, because the MPIDR should only be set
 820          * once, before running the VCPU, and never changed later.
 821          */
 822         if (!has_vhe())
 823                 return false;
 824
 825         switch (reg) {
 826         case SCTLR_EL1:         write_sysreg_s(val, SYS_SCTLR_EL12);    break;
 827         case CPACR_EL1:         write_sysreg_s(val, SYS_CPACR_EL12);    break;
 828         case TTBR0_EL1:         write_sysreg_s(val, SYS_TTBR0_EL12);    break;
 829         case TTBR1_EL1:         write_sysreg_s(val, SYS_TTBR1_EL12);    break;
 830         case TCR_EL1:           write_sysreg_s(val, SYS_TCR_EL12);      break;
 831         case ESR_EL1:           write_sysreg_s(val, SYS_ESR_EL12);      break;
 832         case AFSR0_EL1:         write_sysreg_s(val, SYS_AFSR0_EL12);    break;
 833         case AFSR1_EL1:         write_sysreg_s(val, SYS_AFSR1_EL12);    break;
 834         case FAR_EL1:           write_sysreg_s(val, SYS_FAR_EL12);      break;
 835         case MAIR_EL1:          write_sysreg_s(val, SYS_MAIR_EL12);     break;
 836         case VBAR_EL1:          write_sysreg_s(val, SYS_VBAR_EL12);     break;
 837         case CONTEXTIDR_EL1:    write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break;
 838         case TPIDR_EL0:         write_sysreg_s(val, SYS_TPIDR_EL0);     break;
 839         case TPIDRRO_EL0:       write_sysreg_s(val, SYS_TPIDRRO_EL0);   break;
 840         case TPIDR_EL1:         write_sysreg_s(val, SYS_TPIDR_EL1);     break;
 841         case AMAIR_EL1:         write_sysreg_s(val, SYS_AMAIR_EL12);    break;
 842         case CNTKCTL_EL1:       write_sysreg_s(val, SYS_CNTKCTL_EL12);  break;
 843         case ELR_EL1:           write_sysreg_s(val, SYS_ELR_EL12);      break;
 844         case PAR_EL1:           write_sysreg_s(val, SYS_PAR_EL1);       break;
 845         case DACR32_EL2:        write_sysreg_s(val, SYS_DACR32_EL2);    break;
 846         case IFSR32_EL2:        write_sysreg_s(val, SYS_IFSR32_EL2);    break;
 847         case DBGVCR32_EL2:      write_sysreg_s(val, SYS_DBGVCR32_EL2);  break;
 848         default:                return false;
 849         }
 850
 851         return true;
 852 }
 853
 854 struct kvm_vm_stat {
 855         struct kvm_vm_stat_generic generic;
 856 };
 857
 858 struct kvm_vcpu_stat {
 859         struct kvm_vcpu_stat_generic generic;
 860         u64 hvc_exit_stat;
 861         u64 wfe_exit_stat;
 862         u64 wfi_exit_stat;
 863         u64 mmio_exit_user;
 864         u64 mmio_exit_kernel;
 865         u64 signal_exits;
 866         u64 exits;
 867 };
 868
 869 void kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
 870 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
 871 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
 872 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
 873 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
 874
 875 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu);
 876 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
 877
 878 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
 879                               struct kvm_vcpu_events *events);
 880
 881 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
 882                               struct kvm_vcpu_events *events);
 883
 884 #define KVM_ARCH_WANT_MMU_NOTIFIER
 885
 886 void kvm_arm_halt_guest(struct kvm *kvm);
 887 void kvm_arm_resume_guest(struct kvm *kvm);
 888
 889 #define vcpu_has_run_once(vcpu) !!rcu_access_pointer((vcpu)->pid)
 890
 891 #ifndef __KVM_NVHE_HYPERVISOR__
 892 #define kvm_call_hyp_nvhe(f, ...)                                               \
 893         ({                                                              \
 894                 struct arm_smccc_res res;                               \
 895                                                                         \
 896                 arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f),               \
 897                                   ##__VA_ARGS__, &res);                 \
 898                 WARN_ON(res.a0 != SMCCC_RET_SUCCESS);                   \
 899                                                                         \
 900                 res.a1;                                                 \
 901         })
 902
 903 /*
 904  * The couple of isb() below are there to guarantee the same behaviour
 905  * on VHE as on !VHE, where the eret to EL1 acts as a context
 906  * synchronization event.
 907  */
 908 #define kvm_call_hyp(f, ...)                                            \
 909         do {                                                            \
 910                 if (has_vhe()) {                                        \
 911                         f(__VA_ARGS__);                                 \
 912                         isb();                                          \
 913                 } else {                                                \
 914                         kvm_call_hyp_nvhe(f, ##__VA_ARGS__);            \
 915                 }                                                       \
 916         } while(0)
 917
 918 #define kvm_call_hyp_ret(f, ...)                                        \
 919         ({                                                              \
 920                 typeof(f(__VA_ARGS__)) ret;                             \
 921                                                                         \
 922                 if (has_vhe()) {                                        \
 923                         ret = f(__VA_ARGS__);                           \
 924                         isb();                                          \
 925                 } else {                                                \
 926                         ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__);      \
 927                 }                                                       \
 928                                                                         \
 929                 ret;                                                    \
 930         })
 931 #else /* __KVM_NVHE_HYPERVISOR__ */
 932 #define kvm_call_hyp(f, ...) f(__VA_ARGS__)
 933 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__)
 934 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__)
 935 #endif /* __KVM_NVHE_HYPERVISOR__ */
 936
 937 void force_vm_exit(const cpumask_t *mask);
 938
 939 int handle_exit(struct kvm_vcpu *vcpu, int exception_index);
 940 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index);
 941
 942 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu);
 943 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu);
 944 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu);
 945 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu);
 946 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu);
 947 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu);
 948 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu);
 949
 950 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu);
 951
 952 int __init kvm_sys_reg_table_init(void);
 953
 954 bool lock_all_vcpus(struct kvm *kvm);
 955 void unlock_all_vcpus(struct kvm *kvm);
 956
 957 /* MMIO helpers */
 958 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data);
 959 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len);
 960
 961 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu);
 962 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa);
 963
 964 /*
 965  * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event,
 966  * arrived in guest context.  For arm64, any event that arrives while a vCPU is
 967  * loaded is considered to be "in guest".
 968  */
 969 static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu)
 970 {
 971         return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu;
 972 }
 973
 974 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu);
 975 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu);
 976 void kvm_update_stolen_time(struct kvm_vcpu *vcpu);
 977
 978 bool kvm_arm_pvtime_supported(void);
 979 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu,
 980                             struct kvm_device_attr *attr);
 981 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu,
 982                             struct kvm_device_attr *attr);
 983 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu,
 984                             struct kvm_device_attr *attr);
 985
 986 extern unsigned int __ro_after_init kvm_arm_vmid_bits;
 987 int __init kvm_arm_vmid_alloc_init(void);
 988 void __init kvm_arm_vmid_alloc_free(void);
 989 void kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid);
 990 void kvm_arm_vmid_clear_active(void);
 991
 992 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch)
 993 {
 994         vcpu_arch->steal.base = INVALID_GPA;
 995 }
 996
 997 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch)
 998 {
 999         return (vcpu_arch->steal.base != INVALID_GPA);
1000 }
1001
1002 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome);
1003
1004 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
1005
1006 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data);
1007
1008 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt)
1009 {
1010         /* The host's MPIDR is immutable, so let's set it up at boot time */
1011         ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr();
1012 }
1013
1014 static inline bool kvm_system_needs_idmapped_vectors(void)
1015 {
1016         return cpus_have_const_cap(ARM64_SPECTRE_V3A);
1017 }
1018
1019 void kvm_arm_vcpu_ptrauth_trap(struct kvm_vcpu *vcpu);
1020
1021 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
1022 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
1023
1024 void kvm_arm_init_debug(void);
1025 void kvm_arm_vcpu_init_debug(struct kvm_vcpu *vcpu);
1026 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
1027 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
1028 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
1029
1030 #define kvm_vcpu_os_lock_enabled(vcpu)          \
1031         (!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & SYS_OSLSR_OSLK))
1032
1033 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
1034                                struct kvm_device_attr *attr);
1035 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
1036                                struct kvm_device_attr *attr);
1037 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
1038                                struct kvm_device_attr *attr);
1039
1040 int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm,
1041                                struct kvm_arm_copy_mte_tags *copy_tags);
1042 int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm,
1043                                     struct kvm_arm_counter_offset *offset);
1044
1045 /* Guest/host FPSIMD coordination helpers */
1046 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu);
1047 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu);
1048 void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu);
1049 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu);
1050 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu);
1051 void kvm_vcpu_unshare_task_fp(struct kvm_vcpu *vcpu);
1052
1053 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr)
1054 {
1055         return (!has_vhe() && attr->exclude_host);
1056 }
1057
1058 /* Flags for host debug state */
1059 void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu);
1060 void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu);
1061
1062 #ifdef CONFIG_KVM
1063 void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr);
1064 void kvm_clr_pmu_events(u32 clr);
1065 #else
1066 static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {}
1067 static inline void kvm_clr_pmu_events(u32 clr) {}
1068 #endif
1069
1070 void kvm_vcpu_load_sysregs_vhe(struct kvm_vcpu *vcpu);
1071 void kvm_vcpu_put_sysregs_vhe(struct kvm_vcpu *vcpu);
1072
1073 int __init kvm_set_ipa_limit(void);
1074
1075 #define __KVM_HAVE_ARCH_VM_ALLOC
1076 struct kvm *kvm_arch_alloc_vm(void);
1077
1078 static inline bool kvm_vm_is_protected(struct kvm *kvm)
1079 {
1080         return false;
1081 }
1082
1083 void kvm_init_protected_traps(struct kvm_vcpu *vcpu);
1084
1085 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature);
1086 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu);
1087
1088 #define kvm_arm_vcpu_sve_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_SVE_FINALIZED)
1089
1090 #define kvm_has_mte(kvm)                                        \
1091         (system_supports_mte() &&                               \
1092          test_bit(KVM_ARCH_FLAG_MTE_ENABLED, &(kvm)->arch.flags))
1093
1094 #define kvm_supports_32bit_el0()                                \
1095         (system_supports_32bit_el0() &&                         \
1096          !static_branch_unlikely(&arm64_mismatched_32bit_el0))
1097
1098 #define kvm_vm_has_ran_once(kvm)                                        \
1099         (test_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &(kvm)->arch.flags))
1100
1101 int kvm_trng_call(struct kvm_vcpu *vcpu);
1102 #ifdef CONFIG_KVM
1103 extern phys_addr_t hyp_mem_base;
1104 extern phys_addr_t hyp_mem_size;
1105 void __init kvm_hyp_reserve(void);
1106 #else
1107 static inline void kvm_hyp_reserve(void) { }
1108 #endif
1109
1110 void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu);
1111 bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu);
1112
1113 #endif /* __ARM64_KVM_HOST_H__ */