2 * Copyright (C) 2012 ARM Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 #ifndef __ASM_IRQFLAGS_H
17 #define __ASM_IRQFLAGS_H
21 #include <asm/alternative.h>
22 #include <asm/ptrace.h>
23 #include <asm/sysreg.h>
26 * Aarch64 has flags for masking: Debug, Asynchronous (serror), Interrupts and
27 * FIQ exceptions, in the 'daif' register. We mask and unmask them in 'dai'
29 * Masking debug exceptions causes all other exceptions to be masked too/
30 * Masking SError masks irq, but not debug exceptions. Masking irqs has no
31 * side effects for other flags. Keeping to this order makes it easier for
32 * entry.S to know which exceptions should be unmasked.
34 * FIQ is never expected, but we mask it when we disable debug exceptions, and
35 * unmask it at all other times.
39 * CPU interrupt mask handling.
41 static inline void arch_local_irq_enable(void)
43 asm volatile(ALTERNATIVE(
44 "msr daifclr, #2 // arch_local_irq_enable\n"
46 __msr_s(SYS_ICC_PMR_EL1, "%0")
48 ARM64_HAS_IRQ_PRIO_MASKING)
50 : "r" ((unsigned long) GIC_PRIO_IRQON)
54 static inline void arch_local_irq_disable(void)
56 asm volatile(ALTERNATIVE(
57 "msr daifset, #2 // arch_local_irq_disable",
58 __msr_s(SYS_ICC_PMR_EL1, "%0"),
59 ARM64_HAS_IRQ_PRIO_MASKING)
61 : "r" ((unsigned long) GIC_PRIO_IRQOFF)
66 * Save the current interrupt enable state.
68 static inline unsigned long arch_local_save_flags(void)
70 unsigned long daif_bits;
73 daif_bits = read_sysreg(daif);
76 * The asm is logically equivalent to:
78 * if (system_uses_irq_prio_masking())
79 * flags = (daif_bits & PSR_I_BIT) ?
81 * read_sysreg_s(SYS_ICC_PMR_EL1);
85 asm volatile(ALTERNATIVE(
89 __mrs_s("%0", SYS_ICC_PMR_EL1)
90 "ands %1, %1, " __stringify(PSR_I_BIT) "\n"
91 "csel %0, %0, %2, eq",
92 ARM64_HAS_IRQ_PRIO_MASKING)
93 : "=&r" (flags), "+r" (daif_bits)
94 : "r" ((unsigned long) GIC_PRIO_IRQOFF)
100 static inline unsigned long arch_local_irq_save(void)
104 flags = arch_local_save_flags();
106 arch_local_irq_disable();
112 * restore saved IRQ state
114 static inline void arch_local_irq_restore(unsigned long flags)
116 asm volatile(ALTERNATIVE(
119 __msr_s(SYS_ICC_PMR_EL1, "%0")
121 ARM64_HAS_IRQ_PRIO_MASKING)
127 static inline int arch_irqs_disabled_flags(unsigned long flags)
131 asm volatile(ALTERNATIVE(
132 "and %w0, %w1, #" __stringify(PSR_I_BIT) "\n"
134 "cmp %w1, #" __stringify(GIC_PRIO_IRQOFF) "\n"
136 ARM64_HAS_IRQ_PRIO_MASKING)