2 * Copyright (C) 2013 Huawei Ltd.
3 * Author: Jiang Liu <liuj97@gmail.com>
5 * Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/build_bug.h>
22 #include <linux/types.h>
24 /* A64 instructions are always 32 bits. */
25 #define AARCH64_INSN_SIZE 4
29 * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
30 * Section C3.1 "A64 instruction index by encoding":
31 * AArch64 main encoding table
33 * 28 27 26 25 Encoding Group
35 * 1 0 0 - Data processing, immediate
36 * 1 0 1 - Branch, exception generation and system instructions
37 * - 1 - 0 Loads and stores
38 * - 1 0 1 Data processing - register
39 * 0 1 1 1 Data processing - SIMD and floating point
40 * 1 1 1 1 Data processing - SIMD and floating point
41 * "-" means "don't care"
43 enum aarch64_insn_encoding_class {
44 AARCH64_INSN_CLS_UNKNOWN, /* UNALLOCATED */
45 AARCH64_INSN_CLS_DP_IMM, /* Data processing - immediate */
46 AARCH64_INSN_CLS_DP_REG, /* Data processing - register */
47 AARCH64_INSN_CLS_DP_FPSIMD, /* Data processing - SIMD and FP */
48 AARCH64_INSN_CLS_LDST, /* Loads and stores */
49 AARCH64_INSN_CLS_BR_SYS, /* Branch, exception generation and
50 * system instructions */
53 enum aarch64_insn_hint_op {
54 AARCH64_INSN_HINT_NOP = 0x0 << 5,
55 AARCH64_INSN_HINT_YIELD = 0x1 << 5,
56 AARCH64_INSN_HINT_WFE = 0x2 << 5,
57 AARCH64_INSN_HINT_WFI = 0x3 << 5,
58 AARCH64_INSN_HINT_SEV = 0x4 << 5,
59 AARCH64_INSN_HINT_SEVL = 0x5 << 5,
62 enum aarch64_insn_imm_type {
78 enum aarch64_insn_register_type {
79 AARCH64_INSN_REGTYPE_RT,
80 AARCH64_INSN_REGTYPE_RN,
81 AARCH64_INSN_REGTYPE_RT2,
82 AARCH64_INSN_REGTYPE_RM,
83 AARCH64_INSN_REGTYPE_RD,
84 AARCH64_INSN_REGTYPE_RA,
85 AARCH64_INSN_REGTYPE_RS,
88 enum aarch64_insn_register {
89 AARCH64_INSN_REG_0 = 0,
90 AARCH64_INSN_REG_1 = 1,
91 AARCH64_INSN_REG_2 = 2,
92 AARCH64_INSN_REG_3 = 3,
93 AARCH64_INSN_REG_4 = 4,
94 AARCH64_INSN_REG_5 = 5,
95 AARCH64_INSN_REG_6 = 6,
96 AARCH64_INSN_REG_7 = 7,
97 AARCH64_INSN_REG_8 = 8,
98 AARCH64_INSN_REG_9 = 9,
99 AARCH64_INSN_REG_10 = 10,
100 AARCH64_INSN_REG_11 = 11,
101 AARCH64_INSN_REG_12 = 12,
102 AARCH64_INSN_REG_13 = 13,
103 AARCH64_INSN_REG_14 = 14,
104 AARCH64_INSN_REG_15 = 15,
105 AARCH64_INSN_REG_16 = 16,
106 AARCH64_INSN_REG_17 = 17,
107 AARCH64_INSN_REG_18 = 18,
108 AARCH64_INSN_REG_19 = 19,
109 AARCH64_INSN_REG_20 = 20,
110 AARCH64_INSN_REG_21 = 21,
111 AARCH64_INSN_REG_22 = 22,
112 AARCH64_INSN_REG_23 = 23,
113 AARCH64_INSN_REG_24 = 24,
114 AARCH64_INSN_REG_25 = 25,
115 AARCH64_INSN_REG_26 = 26,
116 AARCH64_INSN_REG_27 = 27,
117 AARCH64_INSN_REG_28 = 28,
118 AARCH64_INSN_REG_29 = 29,
119 AARCH64_INSN_REG_FP = 29, /* Frame pointer */
120 AARCH64_INSN_REG_30 = 30,
121 AARCH64_INSN_REG_LR = 30, /* Link register */
122 AARCH64_INSN_REG_ZR = 31, /* Zero: as source register */
123 AARCH64_INSN_REG_SP = 31 /* Stack pointer: as load/store base reg */
126 enum aarch64_insn_special_register {
127 AARCH64_INSN_SPCLREG_SPSR_EL1 = 0xC200,
128 AARCH64_INSN_SPCLREG_ELR_EL1 = 0xC201,
129 AARCH64_INSN_SPCLREG_SP_EL0 = 0xC208,
130 AARCH64_INSN_SPCLREG_SPSEL = 0xC210,
131 AARCH64_INSN_SPCLREG_CURRENTEL = 0xC212,
132 AARCH64_INSN_SPCLREG_DAIF = 0xDA11,
133 AARCH64_INSN_SPCLREG_NZCV = 0xDA10,
134 AARCH64_INSN_SPCLREG_FPCR = 0xDA20,
135 AARCH64_INSN_SPCLREG_DSPSR_EL0 = 0xDA28,
136 AARCH64_INSN_SPCLREG_DLR_EL0 = 0xDA29,
137 AARCH64_INSN_SPCLREG_SPSR_EL2 = 0xE200,
138 AARCH64_INSN_SPCLREG_ELR_EL2 = 0xE201,
139 AARCH64_INSN_SPCLREG_SP_EL1 = 0xE208,
140 AARCH64_INSN_SPCLREG_SPSR_INQ = 0xE218,
141 AARCH64_INSN_SPCLREG_SPSR_ABT = 0xE219,
142 AARCH64_INSN_SPCLREG_SPSR_UND = 0xE21A,
143 AARCH64_INSN_SPCLREG_SPSR_FIQ = 0xE21B,
144 AARCH64_INSN_SPCLREG_SPSR_EL3 = 0xF200,
145 AARCH64_INSN_SPCLREG_ELR_EL3 = 0xF201,
146 AARCH64_INSN_SPCLREG_SP_EL2 = 0xF210
149 enum aarch64_insn_variant {
150 AARCH64_INSN_VARIANT_32BIT,
151 AARCH64_INSN_VARIANT_64BIT
154 enum aarch64_insn_condition {
155 AARCH64_INSN_COND_EQ = 0x0, /* == */
156 AARCH64_INSN_COND_NE = 0x1, /* != */
157 AARCH64_INSN_COND_CS = 0x2, /* unsigned >= */
158 AARCH64_INSN_COND_CC = 0x3, /* unsigned < */
159 AARCH64_INSN_COND_MI = 0x4, /* < 0 */
160 AARCH64_INSN_COND_PL = 0x5, /* >= 0 */
161 AARCH64_INSN_COND_VS = 0x6, /* overflow */
162 AARCH64_INSN_COND_VC = 0x7, /* no overflow */
163 AARCH64_INSN_COND_HI = 0x8, /* unsigned > */
164 AARCH64_INSN_COND_LS = 0x9, /* unsigned <= */
165 AARCH64_INSN_COND_GE = 0xa, /* signed >= */
166 AARCH64_INSN_COND_LT = 0xb, /* signed < */
167 AARCH64_INSN_COND_GT = 0xc, /* signed > */
168 AARCH64_INSN_COND_LE = 0xd, /* signed <= */
169 AARCH64_INSN_COND_AL = 0xe, /* always */
172 enum aarch64_insn_branch_type {
173 AARCH64_INSN_BRANCH_NOLINK,
174 AARCH64_INSN_BRANCH_LINK,
175 AARCH64_INSN_BRANCH_RETURN,
176 AARCH64_INSN_BRANCH_COMP_ZERO,
177 AARCH64_INSN_BRANCH_COMP_NONZERO,
180 enum aarch64_insn_size_type {
182 AARCH64_INSN_SIZE_16,
183 AARCH64_INSN_SIZE_32,
184 AARCH64_INSN_SIZE_64,
187 enum aarch64_insn_ldst_type {
188 AARCH64_INSN_LDST_LOAD_REG_OFFSET,
189 AARCH64_INSN_LDST_STORE_REG_OFFSET,
190 AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX,
191 AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX,
192 AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX,
193 AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX,
194 AARCH64_INSN_LDST_LOAD_EX,
195 AARCH64_INSN_LDST_STORE_EX,
198 enum aarch64_insn_adsb_type {
199 AARCH64_INSN_ADSB_ADD,
200 AARCH64_INSN_ADSB_SUB,
201 AARCH64_INSN_ADSB_ADD_SETFLAGS,
202 AARCH64_INSN_ADSB_SUB_SETFLAGS
205 enum aarch64_insn_movewide_type {
206 AARCH64_INSN_MOVEWIDE_ZERO,
207 AARCH64_INSN_MOVEWIDE_KEEP,
208 AARCH64_INSN_MOVEWIDE_INVERSE
211 enum aarch64_insn_bitfield_type {
212 AARCH64_INSN_BITFIELD_MOVE,
213 AARCH64_INSN_BITFIELD_MOVE_UNSIGNED,
214 AARCH64_INSN_BITFIELD_MOVE_SIGNED
217 enum aarch64_insn_data1_type {
218 AARCH64_INSN_DATA1_REVERSE_16,
219 AARCH64_INSN_DATA1_REVERSE_32,
220 AARCH64_INSN_DATA1_REVERSE_64,
223 enum aarch64_insn_data2_type {
224 AARCH64_INSN_DATA2_UDIV,
225 AARCH64_INSN_DATA2_SDIV,
226 AARCH64_INSN_DATA2_LSLV,
227 AARCH64_INSN_DATA2_LSRV,
228 AARCH64_INSN_DATA2_ASRV,
229 AARCH64_INSN_DATA2_RORV,
232 enum aarch64_insn_data3_type {
233 AARCH64_INSN_DATA3_MADD,
234 AARCH64_INSN_DATA3_MSUB,
237 enum aarch64_insn_logic_type {
238 AARCH64_INSN_LOGIC_AND,
239 AARCH64_INSN_LOGIC_BIC,
240 AARCH64_INSN_LOGIC_ORR,
241 AARCH64_INSN_LOGIC_ORN,
242 AARCH64_INSN_LOGIC_EOR,
243 AARCH64_INSN_LOGIC_EON,
244 AARCH64_INSN_LOGIC_AND_SETFLAGS,
245 AARCH64_INSN_LOGIC_BIC_SETFLAGS
248 enum aarch64_insn_prfm_type {
249 AARCH64_INSN_PRFM_TYPE_PLD,
250 AARCH64_INSN_PRFM_TYPE_PLI,
251 AARCH64_INSN_PRFM_TYPE_PST,
254 enum aarch64_insn_prfm_target {
255 AARCH64_INSN_PRFM_TARGET_L1,
256 AARCH64_INSN_PRFM_TARGET_L2,
257 AARCH64_INSN_PRFM_TARGET_L3,
260 enum aarch64_insn_prfm_policy {
261 AARCH64_INSN_PRFM_POLICY_KEEP,
262 AARCH64_INSN_PRFM_POLICY_STRM,
265 enum aarch64_insn_adr_type {
266 AARCH64_INSN_ADR_TYPE_ADRP,
267 AARCH64_INSN_ADR_TYPE_ADR,
270 #define __AARCH64_INSN_FUNCS(abbr, mask, val) \
271 static __always_inline bool aarch64_insn_is_##abbr(u32 code) \
273 BUILD_BUG_ON(~(mask) & (val)); \
274 return (code & (mask)) == (val); \
276 static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \
281 __AARCH64_INSN_FUNCS(adr, 0x9F000000, 0x10000000)
282 __AARCH64_INSN_FUNCS(adrp, 0x9F000000, 0x90000000)
283 __AARCH64_INSN_FUNCS(prfm, 0x3FC00000, 0x39800000)
284 __AARCH64_INSN_FUNCS(prfm_lit, 0xFF000000, 0xD8000000)
285 __AARCH64_INSN_FUNCS(str_reg, 0x3FE0EC00, 0x38206800)
286 __AARCH64_INSN_FUNCS(ldadd, 0x3F20FC00, 0x38200000)
287 __AARCH64_INSN_FUNCS(ldr_reg, 0x3FE0EC00, 0x38606800)
288 __AARCH64_INSN_FUNCS(ldr_lit, 0xBF000000, 0x18000000)
289 __AARCH64_INSN_FUNCS(ldrsw_lit, 0xFF000000, 0x98000000)
290 __AARCH64_INSN_FUNCS(exclusive, 0x3F800000, 0x08000000)
291 __AARCH64_INSN_FUNCS(load_ex, 0x3F400000, 0x08400000)
292 __AARCH64_INSN_FUNCS(store_ex, 0x3F400000, 0x08000000)
293 __AARCH64_INSN_FUNCS(stp_post, 0x7FC00000, 0x28800000)
294 __AARCH64_INSN_FUNCS(ldp_post, 0x7FC00000, 0x28C00000)
295 __AARCH64_INSN_FUNCS(stp_pre, 0x7FC00000, 0x29800000)
296 __AARCH64_INSN_FUNCS(ldp_pre, 0x7FC00000, 0x29C00000)
297 __AARCH64_INSN_FUNCS(add_imm, 0x7F000000, 0x11000000)
298 __AARCH64_INSN_FUNCS(adds_imm, 0x7F000000, 0x31000000)
299 __AARCH64_INSN_FUNCS(sub_imm, 0x7F000000, 0x51000000)
300 __AARCH64_INSN_FUNCS(subs_imm, 0x7F000000, 0x71000000)
301 __AARCH64_INSN_FUNCS(movn, 0x7F800000, 0x12800000)
302 __AARCH64_INSN_FUNCS(sbfm, 0x7F800000, 0x13000000)
303 __AARCH64_INSN_FUNCS(bfm, 0x7F800000, 0x33000000)
304 __AARCH64_INSN_FUNCS(movz, 0x7F800000, 0x52800000)
305 __AARCH64_INSN_FUNCS(ubfm, 0x7F800000, 0x53000000)
306 __AARCH64_INSN_FUNCS(movk, 0x7F800000, 0x72800000)
307 __AARCH64_INSN_FUNCS(add, 0x7F200000, 0x0B000000)
308 __AARCH64_INSN_FUNCS(adds, 0x7F200000, 0x2B000000)
309 __AARCH64_INSN_FUNCS(sub, 0x7F200000, 0x4B000000)
310 __AARCH64_INSN_FUNCS(subs, 0x7F200000, 0x6B000000)
311 __AARCH64_INSN_FUNCS(madd, 0x7FE08000, 0x1B000000)
312 __AARCH64_INSN_FUNCS(msub, 0x7FE08000, 0x1B008000)
313 __AARCH64_INSN_FUNCS(udiv, 0x7FE0FC00, 0x1AC00800)
314 __AARCH64_INSN_FUNCS(sdiv, 0x7FE0FC00, 0x1AC00C00)
315 __AARCH64_INSN_FUNCS(lslv, 0x7FE0FC00, 0x1AC02000)
316 __AARCH64_INSN_FUNCS(lsrv, 0x7FE0FC00, 0x1AC02400)
317 __AARCH64_INSN_FUNCS(asrv, 0x7FE0FC00, 0x1AC02800)
318 __AARCH64_INSN_FUNCS(rorv, 0x7FE0FC00, 0x1AC02C00)
319 __AARCH64_INSN_FUNCS(rev16, 0x7FFFFC00, 0x5AC00400)
320 __AARCH64_INSN_FUNCS(rev32, 0x7FFFFC00, 0x5AC00800)
321 __AARCH64_INSN_FUNCS(rev64, 0x7FFFFC00, 0x5AC00C00)
322 __AARCH64_INSN_FUNCS(and, 0x7F200000, 0x0A000000)
323 __AARCH64_INSN_FUNCS(bic, 0x7F200000, 0x0A200000)
324 __AARCH64_INSN_FUNCS(orr, 0x7F200000, 0x2A000000)
325 __AARCH64_INSN_FUNCS(orn, 0x7F200000, 0x2A200000)
326 __AARCH64_INSN_FUNCS(eor, 0x7F200000, 0x4A000000)
327 __AARCH64_INSN_FUNCS(eon, 0x7F200000, 0x4A200000)
328 __AARCH64_INSN_FUNCS(ands, 0x7F200000, 0x6A000000)
329 __AARCH64_INSN_FUNCS(bics, 0x7F200000, 0x6A200000)
330 __AARCH64_INSN_FUNCS(and_imm, 0x7F800000, 0x12000000)
331 __AARCH64_INSN_FUNCS(orr_imm, 0x7F800000, 0x32000000)
332 __AARCH64_INSN_FUNCS(eor_imm, 0x7F800000, 0x52000000)
333 __AARCH64_INSN_FUNCS(ands_imm, 0x7F800000, 0x72000000)
334 __AARCH64_INSN_FUNCS(extr, 0x7FA00000, 0x13800000)
335 __AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000)
336 __AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000)
337 __AARCH64_INSN_FUNCS(cbz, 0x7F000000, 0x34000000)
338 __AARCH64_INSN_FUNCS(cbnz, 0x7F000000, 0x35000000)
339 __AARCH64_INSN_FUNCS(tbz, 0x7F000000, 0x36000000)
340 __AARCH64_INSN_FUNCS(tbnz, 0x7F000000, 0x37000000)
341 __AARCH64_INSN_FUNCS(bcond, 0xFF000010, 0x54000000)
342 __AARCH64_INSN_FUNCS(svc, 0xFFE0001F, 0xD4000001)
343 __AARCH64_INSN_FUNCS(hvc, 0xFFE0001F, 0xD4000002)
344 __AARCH64_INSN_FUNCS(smc, 0xFFE0001F, 0xD4000003)
345 __AARCH64_INSN_FUNCS(brk, 0xFFE0001F, 0xD4200000)
346 __AARCH64_INSN_FUNCS(exception, 0xFF000000, 0xD4000000)
347 __AARCH64_INSN_FUNCS(hint, 0xFFFFF01F, 0xD503201F)
348 __AARCH64_INSN_FUNCS(br, 0xFFFFFC1F, 0xD61F0000)
349 __AARCH64_INSN_FUNCS(blr, 0xFFFFFC1F, 0xD63F0000)
350 __AARCH64_INSN_FUNCS(ret, 0xFFFFFC1F, 0xD65F0000)
351 __AARCH64_INSN_FUNCS(eret, 0xFFFFFFFF, 0xD69F03E0)
352 __AARCH64_INSN_FUNCS(mrs, 0xFFF00000, 0xD5300000)
353 __AARCH64_INSN_FUNCS(msr_imm, 0xFFF8F01F, 0xD500401F)
354 __AARCH64_INSN_FUNCS(msr_reg, 0xFFF00000, 0xD5100000)
356 #undef __AARCH64_INSN_FUNCS
358 bool aarch64_insn_is_nop(u32 insn);
359 bool aarch64_insn_is_branch_imm(u32 insn);
361 static inline bool aarch64_insn_is_adr_adrp(u32 insn)
363 return aarch64_insn_is_adr(insn) || aarch64_insn_is_adrp(insn);
366 int aarch64_insn_read(void *addr, u32 *insnp);
367 int aarch64_insn_write(void *addr, u32 insn);
368 enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn);
369 bool aarch64_insn_uses_literal(u32 insn);
370 bool aarch64_insn_is_branch(u32 insn);
371 u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn);
372 u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
374 u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type,
376 u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
377 enum aarch64_insn_branch_type type);
378 u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
379 enum aarch64_insn_register reg,
380 enum aarch64_insn_variant variant,
381 enum aarch64_insn_branch_type type);
382 u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
383 enum aarch64_insn_condition cond);
384 u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_op op);
385 u32 aarch64_insn_gen_nop(void);
386 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
387 enum aarch64_insn_branch_type type);
388 u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
389 enum aarch64_insn_register base,
390 enum aarch64_insn_register offset,
391 enum aarch64_insn_size_type size,
392 enum aarch64_insn_ldst_type type);
393 u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
394 enum aarch64_insn_register reg2,
395 enum aarch64_insn_register base,
397 enum aarch64_insn_variant variant,
398 enum aarch64_insn_ldst_type type);
399 u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,
400 enum aarch64_insn_register base,
401 enum aarch64_insn_register state,
402 enum aarch64_insn_size_type size,
403 enum aarch64_insn_ldst_type type);
404 u32 aarch64_insn_gen_ldadd(enum aarch64_insn_register result,
405 enum aarch64_insn_register address,
406 enum aarch64_insn_register value,
407 enum aarch64_insn_size_type size);
408 u32 aarch64_insn_gen_stadd(enum aarch64_insn_register address,
409 enum aarch64_insn_register value,
410 enum aarch64_insn_size_type size);
411 u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
412 enum aarch64_insn_register src,
413 int imm, enum aarch64_insn_variant variant,
414 enum aarch64_insn_adsb_type type);
415 u32 aarch64_insn_gen_adr(unsigned long pc, unsigned long addr,
416 enum aarch64_insn_register reg,
417 enum aarch64_insn_adr_type type);
418 u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
419 enum aarch64_insn_register src,
421 enum aarch64_insn_variant variant,
422 enum aarch64_insn_bitfield_type type);
423 u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
425 enum aarch64_insn_variant variant,
426 enum aarch64_insn_movewide_type type);
427 u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
428 enum aarch64_insn_register src,
429 enum aarch64_insn_register reg,
431 enum aarch64_insn_variant variant,
432 enum aarch64_insn_adsb_type type);
433 u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
434 enum aarch64_insn_register src,
435 enum aarch64_insn_variant variant,
436 enum aarch64_insn_data1_type type);
437 u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
438 enum aarch64_insn_register src,
439 enum aarch64_insn_register reg,
440 enum aarch64_insn_variant variant,
441 enum aarch64_insn_data2_type type);
442 u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
443 enum aarch64_insn_register src,
444 enum aarch64_insn_register reg1,
445 enum aarch64_insn_register reg2,
446 enum aarch64_insn_variant variant,
447 enum aarch64_insn_data3_type type);
448 u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
449 enum aarch64_insn_register src,
450 enum aarch64_insn_register reg,
452 enum aarch64_insn_variant variant,
453 enum aarch64_insn_logic_type type);
454 u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type,
455 enum aarch64_insn_variant variant,
456 enum aarch64_insn_register Rn,
457 enum aarch64_insn_register Rd,
459 u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant,
460 enum aarch64_insn_register Rm,
461 enum aarch64_insn_register Rn,
462 enum aarch64_insn_register Rd,
464 u32 aarch64_insn_gen_prefetch(enum aarch64_insn_register base,
465 enum aarch64_insn_prfm_type type,
466 enum aarch64_insn_prfm_target target,
467 enum aarch64_insn_prfm_policy policy);
468 s32 aarch64_get_branch_offset(u32 insn);
469 u32 aarch64_set_branch_offset(u32 insn, s32 offset);
471 int aarch64_insn_patch_text_nosync(void *addr, u32 insn);
472 int aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt);
474 s32 aarch64_insn_adrp_get_offset(u32 insn);
475 u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset);
477 bool aarch32_insn_is_wide(u32 insn);
479 #define A32_RN_OFFSET 16
480 #define A32_RT_OFFSET 12
481 #define A32_RT2_OFFSET 0
483 u32 aarch64_insn_extract_system_reg(u32 insn);
484 u32 aarch32_insn_extract_reg_num(u32 insn, int offset);
485 u32 aarch32_insn_mcr_extract_opc2(u32 insn);
486 u32 aarch32_insn_mcr_extract_crm(u32 insn);
488 typedef bool (pstate_check_t)(unsigned long);
489 extern pstate_check_t * const aarch32_opcode_cond_checks[16];
490 #endif /* __ASSEMBLY__ */
492 #endif /* __ASM_INSN_H */