1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
7 #ifndef __ARM_KVM_INIT_H__
8 #define __ARM_KVM_INIT_H__
11 #error Assembly-only header
14 #include <asm/kvm_arm.h>
15 #include <asm/ptrace.h>
16 #include <asm/sysreg.h>
17 #include <linux/irqchip/arm-gic-v3.h>
19 .macro __init_el2_sctlr
20 mov_q x0, INIT_SCTLR_EL2_MMU_OFF
26 * Allow Non-secure EL1 and EL0 to access physical timer and counter.
27 * This is not necessary for VHE, since the host kernel runs in EL2,
28 * and EL0 accesses are configured in the later stage of boot process.
29 * Note that when HCR_EL2.E2H == 1, CNTHCTL_EL2 has the same bit layout
30 * as CNTKCTL_EL1, and CNTKCTL_EL1 accessing instructions are redefined
31 * to access CNTHCTL_EL2. This allows the kernel designed to run at EL1
32 * to transparently mess with the EL0 bits via CNTKCTL_EL1 access in
35 .macro __init_el2_timers
37 orr x0, x0, #3 // Enable EL1 physical timers
39 msr cntvoff_el2, xzr // Clear virtual offset
42 .macro __init_el2_debug
43 mrs x1, id_aa64dfr0_el1
44 sbfx x0, x1, #ID_AA64DFR0_PMUVER_SHIFT, #4
46 b.lt .Lskip_pmu_\@ // Skip if no PMU present
47 mrs x0, pmcr_el0 // Disable debug access traps
48 ubfx x0, x0, #11, #5 // to EL2 and allow access to
50 csel x2, xzr, x0, lt // all PMU counters from EL1
52 /* Statistical profiling */
53 ubfx x0, x1, #ID_AA64DFR0_PMSVER_SHIFT, #4
54 cbz x0, .Lskip_spe_\@ // Skip if SPE not present
56 mrs_s x0, SYS_PMBIDR_EL1 // If SPE available at EL2,
57 and x0, x0, #(1 << SYS_PMBIDR_EL1_P_SHIFT)
58 cbnz x0, .Lskip_spe_el2_\@ // then permit sampling of physical
59 mov x0, #(1 << SYS_PMSCR_EL2_PCT_SHIFT | \
60 1 << SYS_PMSCR_EL2_PA_SHIFT)
61 msr_s SYS_PMSCR_EL2, x0 // addresses and physical counter
63 mov x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)
64 orr x2, x2, x0 // If we don't have VHE, then
65 // use EL1&0 translation.
68 msr mdcr_el2, x2 // Configure debug traps
73 mrs x1, id_aa64mmfr1_el1
74 ubfx x0, x1, #ID_AA64MMFR1_LOR_SHIFT, 4
76 msr_s SYS_LORC_EL1, xzr
80 /* Stage-2 translation */
81 .macro __init_el2_stage2
85 /* GICv3 system register access */
86 .macro __init_el2_gicv3
87 mrs x0, id_aa64pfr0_el1
88 ubfx x0, x0, #ID_AA64PFR0_GIC_SHIFT, #4
89 cbz x0, .Lskip_gicv3_\@
91 mrs_s x0, SYS_ICC_SRE_EL2
92 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
93 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
94 msr_s SYS_ICC_SRE_EL2, x0
95 isb // Make sure SRE is now set
96 mrs_s x0, SYS_ICC_SRE_EL2 // Read SRE back,
97 tbz x0, #0, 1f // and check that it sticks
98 msr_s SYS_ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults
102 .macro __init_el2_hstr
103 msr hstr_el2, xzr // Disable CP15 traps to EL2
106 /* Virtual CPU ID registers */
107 .macro __init_el2_nvhe_idregs
114 /* Coprocessor traps */
115 .macro __init_el2_nvhe_cptr
117 msr cptr_el2, x0 // Disable copro. traps to EL2
120 /* SVE register access */
121 .macro __init_el2_nvhe_sve
122 mrs x1, id_aa64pfr0_el1
123 ubfx x1, x1, #ID_AA64PFR0_SVE_SHIFT, #4
124 cbz x1, .Lskip_sve_\@
126 bic x0, x0, #CPTR_EL2_TZ // Also disable SVE traps
127 msr cptr_el2, x0 // Disable copro. traps to EL2
129 mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector
130 msr_s SYS_ZCR_EL2, x1 // length for EL1.
134 .macro __init_el2_nvhe_prepare_eret
135 mov x0, #INIT_PSTATE_EL1
140 * Initialize EL2 registers to sane values. This should be called early on all
141 * cores that were booted in EL2. Note that everything gets initialised as
142 * if VHE was not evailable. The kernel context will be upgraded to VHE
143 * if possible later on in the boot process
145 * Regs: x0, x1 and x2 are clobbered.
147 .macro init_el2_state
155 __init_el2_nvhe_idregs
158 __init_el2_nvhe_prepare_eret
161 #endif /* __ARM_KVM_INIT_H__ */