1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
6 #ifndef __ASM_CPUFEATURE_H
7 #define __ASM_CPUFEATURE_H
9 #include <asm/alternative-macros.h>
10 #include <asm/cpucaps.h>
11 #include <asm/cputype.h>
12 #include <asm/hwcap.h>
13 #include <asm/sysreg.h>
15 #define MAX_CPU_FEATURES 128
16 #define cpu_feature(x) KERNEL_HWCAP_ ## x
18 #define ARM64_SW_FEATURE_OVERRIDE_NOKASLR 0
19 #define ARM64_SW_FEATURE_OVERRIDE_HVHE 4
20 #define ARM64_SW_FEATURE_OVERRIDE_RODATA_OFF 8
24 #include <linux/bug.h>
25 #include <linux/jump_label.h>
26 #include <linux/kernel.h>
27 #include <linux/cpumask.h>
30 * CPU feature register tracking
32 * The safe value of a CPUID feature field is dependent on the implications
33 * of the values assigned to it by the architecture. Based on the relationship
34 * between the values, the features are classified into 3 types - LOWER_SAFE,
35 * HIGHER_SAFE and EXACT.
37 * The lowest value of all the CPUs is chosen for LOWER_SAFE and highest
38 * for HIGHER_SAFE. It is expected that all CPUs have the same value for
39 * a field when EXACT is specified, failing which, the safe value specified
40 * in the table is chosen.
44 FTR_EXACT, /* Use a predefined safe value */
45 FTR_LOWER_SAFE, /* Smaller value is safe */
46 FTR_HIGHER_SAFE, /* Bigger value is safe */
47 FTR_HIGHER_OR_ZERO_SAFE, /* Bigger value is safe, but 0 is biggest */
50 #define FTR_STRICT true /* SANITY check strict matching required */
51 #define FTR_NONSTRICT false /* SANITY check ignored */
53 #define FTR_SIGNED true /* Value should be treated as signed */
54 #define FTR_UNSIGNED false /* Value should be treated as unsigned */
56 #define FTR_VISIBLE true /* Feature visible to the user space */
57 #define FTR_HIDDEN false /* Feature is hidden from the user */
59 #define FTR_VISIBLE_IF_IS_ENABLED(config) \
60 (IS_ENABLED(config) ? FTR_VISIBLE : FTR_HIDDEN)
62 struct arm64_ftr_bits {
63 bool sign; /* Value is signed ? */
65 bool strict; /* CPU Sanity check: strict matching required ? */
69 s64 safe_val; /* safe value for FTR_EXACT features */
73 * Describe the early feature override to the core override code:
75 * @val Values that are to be merged into the final
76 * sanitised value of the register. Only the bitfields
77 * set to 1 in @mask are valid
78 * @mask Mask of the features that are overridden by @val
80 * A @mask field set to full-1 indicates that the corresponding field
81 * in @val is a valid override.
83 * A @mask field set to full-0 with the corresponding @val field set
84 * to full-0 denotes that this field has no override
86 * A @mask field set to full-0 with the corresponding @val field set
87 * to full-1 denotes that this field has an invalid override.
89 struct arm64_ftr_override {
95 * @arm64_ftr_reg - Feature register
96 * @strict_mask Bits which should match across all CPUs for sanity.
97 * @sys_val Safe value across the CPUs (system view)
99 struct arm64_ftr_reg {
105 struct arm64_ftr_override *override;
106 const struct arm64_ftr_bits *ftr_bits;
109 extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0;
114 * We use arm64_cpu_capabilities to represent system features, errata work
115 * arounds (both used internally by kernel and tracked in system_cpucaps) and
116 * ELF HWCAPs (which are exposed to user).
118 * To support systems with heterogeneous CPUs, we need to make sure that we
119 * detect the capabilities correctly on the system and take appropriate
120 * measures to ensure there are no incompatibilities.
122 * This comment tries to explain how we treat the capabilities.
123 * Each capability has the following list of attributes :
125 * 1) Scope of Detection : The system detects a given capability by
126 * performing some checks at runtime. This could be, e.g, checking the
127 * value of a field in CPU ID feature register or checking the cpu
128 * model. The capability provides a call back ( @matches() ) to
129 * perform the check. Scope defines how the checks should be performed.
130 * There are three cases:
132 * a) SCOPE_LOCAL_CPU: check all the CPUs and "detect" if at least one
133 * matches. This implies, we have to run the check on all the
134 * booting CPUs, until the system decides that state of the
135 * capability is finalised. (See section 2 below)
137 * b) SCOPE_SYSTEM: check all the CPUs and "detect" if all the CPUs
138 * matches. This implies, we run the check only once, when the
139 * system decides to finalise the state of the capability. If the
140 * capability relies on a field in one of the CPU ID feature
141 * registers, we use the sanitised value of the register from the
142 * CPU feature infrastructure to make the decision.
144 * c) SCOPE_BOOT_CPU: Check only on the primary boot CPU to detect the
145 * feature. This category is for features that are "finalised"
146 * (or used) by the kernel very early even before the SMP cpus
149 * The process of detection is usually denoted by "update" capability
152 * 2) Finalise the state : The kernel should finalise the state of a
153 * capability at some point during its execution and take necessary
154 * actions if any. Usually, this is done, after all the boot-time
155 * enabled CPUs are brought up by the kernel, so that it can make
156 * better decision based on the available set of CPUs. However, there
157 * are some special cases, where the action is taken during the early
158 * boot by the primary boot CPU. (e.g, running the kernel at EL2 with
159 * Virtualisation Host Extensions). The kernel usually disallows any
160 * changes to the state of a capability once it finalises the capability
161 * and takes any action, as it may be impossible to execute the actions
162 * safely. A CPU brought up after a capability is "finalised" is
163 * referred to as "Late CPU" w.r.t the capability. e.g, all secondary
164 * CPUs are treated "late CPUs" for capabilities determined by the boot
167 * At the moment there are two passes of finalising the capabilities.
168 * a) Boot CPU scope capabilities - Finalised by primary boot CPU via
169 * setup_boot_cpu_capabilities().
170 * b) Everything except (a) - Run via setup_system_capabilities().
172 * 3) Verification: When a CPU is brought online (e.g, by user or by the
173 * kernel), the kernel should make sure that it is safe to use the CPU,
174 * by verifying that the CPU is compliant with the state of the
175 * capabilities finalised already. This happens via :
177 * secondary_start_kernel()-> check_local_cpu_capabilities()
179 * As explained in (2) above, capabilities could be finalised at
180 * different points in the execution. Each newly booted CPU is verified
181 * against the capabilities that have been finalised by the time it
184 * a) SCOPE_BOOT_CPU : All CPUs are verified against the capability
185 * except for the primary boot CPU.
187 * b) SCOPE_LOCAL_CPU, SCOPE_SYSTEM: All CPUs hotplugged on by the
188 * user after the kernel boot are verified against the capability.
190 * If there is a conflict, the kernel takes an action, based on the
191 * severity (e.g, a CPU could be prevented from booting or cause a
192 * kernel panic). The CPU is allowed to "affect" the state of the
193 * capability, if it has not been finalised already. See section 5
194 * for more details on conflicts.
196 * 4) Action: As mentioned in (2), the kernel can take an action for each
197 * detected capability, on all CPUs on the system. Appropriate actions
198 * include, turning on an architectural feature, modifying the control
199 * registers (e.g, SCTLR, TCR etc.) or patching the kernel via
200 * alternatives. The kernel patching is batched and performed at later
201 * point. The actions are always initiated only after the capability
202 * is finalised. This is usally denoted by "enabling" the capability.
203 * The actions are initiated as follows :
204 * a) Action is triggered on all online CPUs, after the capability is
205 * finalised, invoked within the stop_machine() context from
206 * enable_cpu_capabilitie().
208 * b) Any late CPU, brought up after (1), the action is triggered via:
210 * check_local_cpu_capabilities() -> verify_local_cpu_capabilities()
212 * 5) Conflicts: Based on the state of the capability on a late CPU vs.
213 * the system state, we could have the following combinations :
215 * x-----------------------------x
216 * | Type | System | Late CPU |
217 * |-----------------------------|
219 * |-----------------------------|
221 * x-----------------------------x
223 * Two separate flag bits are defined to indicate whether each kind of
224 * conflict can be allowed:
225 * ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU - Case(a) is allowed
226 * ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU - Case(b) is allowed
228 * Case (a) is not permitted for a capability that the system requires
229 * all CPUs to have in order for the capability to be enabled. This is
230 * typical for capabilities that represent enhanced functionality.
232 * Case (b) is not permitted for a capability that must be enabled
233 * during boot if any CPU in the system requires it in order to run
234 * safely. This is typical for erratum work arounds that cannot be
235 * enabled after the corresponding capability is finalised.
237 * In some non-typical cases either both (a) and (b), or neither,
238 * should be permitted. This can be described by including neither
239 * or both flags in the capability's type field.
241 * In case of a conflict, the CPU is prevented from booting. If the
242 * ARM64_CPUCAP_PANIC_ON_CONFLICT flag is specified for the capability,
243 * then a kernel panic is triggered.
248 * Decide how the capability is detected.
249 * On any local CPU vs System wide vs the primary boot CPU
251 #define ARM64_CPUCAP_SCOPE_LOCAL_CPU ((u16)BIT(0))
252 #define ARM64_CPUCAP_SCOPE_SYSTEM ((u16)BIT(1))
254 * The capabilitiy is detected on the Boot CPU and is used by kernel
255 * during early boot. i.e, the capability should be "detected" and
256 * "enabled" as early as possibly on all booting CPUs.
258 #define ARM64_CPUCAP_SCOPE_BOOT_CPU ((u16)BIT(2))
259 #define ARM64_CPUCAP_SCOPE_MASK \
260 (ARM64_CPUCAP_SCOPE_SYSTEM | \
261 ARM64_CPUCAP_SCOPE_LOCAL_CPU | \
262 ARM64_CPUCAP_SCOPE_BOOT_CPU)
264 #define SCOPE_SYSTEM ARM64_CPUCAP_SCOPE_SYSTEM
265 #define SCOPE_LOCAL_CPU ARM64_CPUCAP_SCOPE_LOCAL_CPU
266 #define SCOPE_BOOT_CPU ARM64_CPUCAP_SCOPE_BOOT_CPU
267 #define SCOPE_ALL ARM64_CPUCAP_SCOPE_MASK
270 * Is it permitted for a late CPU to have this capability when system
271 * hasn't already enabled it ?
273 #define ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU ((u16)BIT(4))
274 /* Is it safe for a late CPU to miss this capability when system has it */
275 #define ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU ((u16)BIT(5))
276 /* Panic when a conflict is detected */
277 #define ARM64_CPUCAP_PANIC_ON_CONFLICT ((u16)BIT(6))
280 * CPU errata workarounds that need to be enabled at boot time if one or
281 * more CPUs in the system requires it. When one of these capabilities
282 * has been enabled, it is safe to allow any CPU to boot that doesn't
283 * require the workaround. However, it is not safe if a "late" CPU
284 * requires a workaround and the system hasn't enabled it already.
286 #define ARM64_CPUCAP_LOCAL_CPU_ERRATUM \
287 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU)
289 * CPU feature detected at boot time based on system-wide value of a
290 * feature. It is safe for a late CPU to have this feature even though
291 * the system hasn't enabled it, although the feature will not be used
292 * by Linux in this case. If the system has enabled this feature already,
293 * then every late CPU must have it.
295 #define ARM64_CPUCAP_SYSTEM_FEATURE \
296 (ARM64_CPUCAP_SCOPE_SYSTEM | ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
298 * CPU feature detected at boot time based on feature of one or more CPUs.
299 * All possible conflicts for a late CPU are ignored.
300 * NOTE: this means that a late CPU with the feature will *not* cause the
301 * capability to be advertised by cpus_have_*cap()!
303 #define ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE \
304 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | \
305 ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU | \
306 ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
309 * CPU feature detected at boot time, on one or more CPUs. A late CPU
310 * is not allowed to have the capability when the system doesn't have it.
311 * It is Ok for a late CPU to miss the feature.
313 #define ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE \
314 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | \
315 ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU)
318 * CPU feature used early in the boot based on the boot CPU. All secondary
319 * CPUs must match the state of the capability as detected by the boot CPU. In
320 * case of a conflict, a kernel panic is triggered.
322 #define ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE \
323 (ARM64_CPUCAP_SCOPE_BOOT_CPU | ARM64_CPUCAP_PANIC_ON_CONFLICT)
326 * CPU feature used early in the boot based on the boot CPU. It is safe for a
327 * late CPU to have this feature even though the boot CPU hasn't enabled it,
328 * although the feature will not be used by Linux in this case. If the boot CPU
329 * has enabled this feature already, then every late CPU must have it.
331 #define ARM64_CPUCAP_BOOT_CPU_FEATURE \
332 (ARM64_CPUCAP_SCOPE_BOOT_CPU | ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
334 struct arm64_cpu_capabilities {
338 bool (*matches)(const struct arm64_cpu_capabilities *caps, int scope);
340 * Take the appropriate actions to configure this capability
341 * for this CPU. If the capability is detected by the kernel
342 * this will be called on all the CPUs in the system,
343 * including the hotplugged CPUs, regardless of whether the
344 * capability is available on that specific CPU. This is
345 * useful for some capabilities (e.g, working around CPU
346 * errata), where all the CPUs must take some action (e.g,
347 * changing system control/configuration). Thus, if an action
348 * is required only if the CPU has the capability, then the
349 * routine must check it before taking any action.
351 void (*cpu_enable)(const struct arm64_cpu_capabilities *cap);
353 struct { /* To be used for erratum handling only */
354 struct midr_range midr_range;
355 const struct arm64_midr_revidr {
356 u32 midr_rv; /* revision/variant */
358 } * const fixed_revs;
361 const struct midr_range *midr_range_list;
362 struct { /* Feature register checking */
374 * An optional list of "matches/cpu_enable" pair for the same
375 * "capability" of the same "type" as described by the parent.
376 * Only matches(), cpu_enable() and fields relevant to these
377 * methods are significant in the list. The cpu_enable is
378 * invoked only if the corresponding entry "matches()".
379 * However, if a cpu_enable() method is associated
380 * with multiple matches(), care should be taken that either
381 * the match criteria are mutually exclusive, or that the
382 * method is robust against being called multiple times.
384 const struct arm64_cpu_capabilities *match_list;
385 const struct cpumask *cpus;
388 static inline int cpucap_default_scope(const struct arm64_cpu_capabilities *cap)
390 return cap->type & ARM64_CPUCAP_SCOPE_MASK;
394 * Generic helper for handling capabilities with multiple (match,enable) pairs
395 * of call backs, sharing the same capability bit.
396 * Iterate over each entry to see if at least one matches.
399 cpucap_multi_entry_cap_matches(const struct arm64_cpu_capabilities *entry,
402 const struct arm64_cpu_capabilities *caps;
404 for (caps = entry->match_list; caps->matches; caps++)
405 if (caps->matches(caps, scope))
411 static __always_inline bool is_vhe_hyp_code(void)
413 /* Only defined for code run in VHE hyp context */
414 return __is_defined(__KVM_VHE_HYPERVISOR__);
417 static __always_inline bool is_nvhe_hyp_code(void)
419 /* Only defined for code run in NVHE hyp context */
420 return __is_defined(__KVM_NVHE_HYPERVISOR__);
423 static __always_inline bool is_hyp_code(void)
425 return is_vhe_hyp_code() || is_nvhe_hyp_code();
428 extern DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS);
430 extern DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS);
432 #define for_each_available_cap(cap) \
433 for_each_set_bit(cap, system_cpucaps, ARM64_NCAPS)
435 bool this_cpu_has_cap(unsigned int cap);
436 void cpu_set_feature(unsigned int num);
437 bool cpu_have_feature(unsigned int num);
438 unsigned long cpu_get_elf_hwcap(void);
439 unsigned long cpu_get_elf_hwcap2(void);
441 #define cpu_set_named_feature(name) cpu_set_feature(cpu_feature(name))
442 #define cpu_have_named_feature(name) cpu_have_feature(cpu_feature(name))
444 static __always_inline bool boot_capabilities_finalized(void)
446 return alternative_has_cap_likely(ARM64_ALWAYS_BOOT);
449 static __always_inline bool system_capabilities_finalized(void)
451 return alternative_has_cap_likely(ARM64_ALWAYS_SYSTEM);
455 * Test for a capability with a runtime check.
457 * Before the capability is detected, this returns false.
459 static __always_inline bool cpus_have_cap(unsigned int num)
461 if (__builtin_constant_p(num) && !cpucap_is_possible(num))
463 if (num >= ARM64_NCAPS)
465 return arch_test_bit(num, system_cpucaps);
469 * Test for a capability without a runtime check.
471 * Before boot capabilities are finalized, this will BUG().
472 * After boot capabilities are finalized, this is patched to avoid a runtime
475 * @num must be a compile-time constant.
477 static __always_inline bool cpus_have_final_boot_cap(int num)
479 if (boot_capabilities_finalized())
480 return alternative_has_cap_unlikely(num);
486 * Test for a capability without a runtime check.
488 * Before system capabilities are finalized, this will BUG().
489 * After system capabilities are finalized, this is patched to avoid a runtime
492 * @num must be a compile-time constant.
494 static __always_inline bool cpus_have_final_cap(int num)
496 if (system_capabilities_finalized())
497 return alternative_has_cap_unlikely(num);
502 static inline int __attribute_const__
503 cpuid_feature_extract_signed_field_width(u64 features, int field, int width)
505 return (s64)(features << (64 - width - field)) >> (64 - width);
508 static inline int __attribute_const__
509 cpuid_feature_extract_signed_field(u64 features, int field)
511 return cpuid_feature_extract_signed_field_width(features, field, 4);
514 static __always_inline unsigned int __attribute_const__
515 cpuid_feature_extract_unsigned_field_width(u64 features, int field, int width)
517 return (u64)(features << (64 - width - field)) >> (64 - width);
520 static __always_inline unsigned int __attribute_const__
521 cpuid_feature_extract_unsigned_field(u64 features, int field)
523 return cpuid_feature_extract_unsigned_field_width(features, field, 4);
527 * Fields that identify the version of the Performance Monitors Extension do
528 * not follow the standard ID scheme. See ARM DDI 0487E.a page D13-2825,
529 * "Alternative ID scheme used for the Performance Monitors Extension version".
531 static inline u64 __attribute_const__
532 cpuid_feature_cap_perfmon_field(u64 features, int field, u64 cap)
534 u64 val = cpuid_feature_extract_unsigned_field(features, field);
535 u64 mask = GENMASK_ULL(field + 3, field);
537 /* Treat IMPLEMENTATION DEFINED functionality as unimplemented */
538 if (val == ID_AA64DFR0_EL1_PMUVer_IMP_DEF)
543 features |= (cap << field) & mask;
549 static inline u64 arm64_ftr_mask(const struct arm64_ftr_bits *ftrp)
551 return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift);
554 static inline u64 arm64_ftr_reg_user_value(const struct arm64_ftr_reg *reg)
556 return (reg->user_val | (reg->sys_val & reg->user_mask));
559 static inline int __attribute_const__
560 cpuid_feature_extract_field_width(u64 features, int field, int width, bool sign)
562 if (WARN_ON_ONCE(!width))
565 cpuid_feature_extract_signed_field_width(features, field, width) :
566 cpuid_feature_extract_unsigned_field_width(features, field, width);
569 static inline int __attribute_const__
570 cpuid_feature_extract_field(u64 features, int field, bool sign)
572 return cpuid_feature_extract_field_width(features, field, 4, sign);
575 static inline s64 arm64_ftr_value(const struct arm64_ftr_bits *ftrp, u64 val)
577 return (s64)cpuid_feature_extract_field_width(val, ftrp->shift, ftrp->width, ftrp->sign);
580 static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)
582 return cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_EL1_BIGEND_SHIFT) == 0x1 ||
583 cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT) == 0x1;
586 static inline bool id_aa64pfr0_32bit_el1(u64 pfr0)
588 u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_EL1_SHIFT);
590 return val == ID_AA64PFR0_EL1_ELx_32BIT_64BIT;
593 static inline bool id_aa64pfr0_32bit_el0(u64 pfr0)
595 u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_EL0_SHIFT);
597 return val == ID_AA64PFR0_EL1_ELx_32BIT_64BIT;
600 static inline bool id_aa64pfr0_sve(u64 pfr0)
602 u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_SVE_SHIFT);
607 static inline bool id_aa64pfr1_sme(u64 pfr1)
609 u32 val = cpuid_feature_extract_unsigned_field(pfr1, ID_AA64PFR1_EL1_SME_SHIFT);
614 static inline bool id_aa64pfr1_mte(u64 pfr1)
616 u32 val = cpuid_feature_extract_unsigned_field(pfr1, ID_AA64PFR1_EL1_MTE_SHIFT);
618 return val >= ID_AA64PFR1_EL1_MTE_MTE2;
621 void __init setup_boot_cpu_features(void);
622 void __init setup_system_features(void);
623 void __init setup_user_features(void);
625 void check_local_cpu_capabilities(void);
627 u64 read_sanitised_ftr_reg(u32 id);
628 u64 __read_sysreg_by_encoding(u32 sys_id);
630 static inline bool cpu_supports_mixed_endian_el0(void)
632 return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1));
636 static inline bool supports_csv2p3(int scope)
641 if (scope == SCOPE_LOCAL_CPU)
642 pfr0 = read_sysreg_s(SYS_ID_AA64PFR0_EL1);
644 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
646 csv2_val = cpuid_feature_extract_unsigned_field(pfr0,
647 ID_AA64PFR0_EL1_CSV2_SHIFT);
648 return csv2_val == 3;
651 static inline bool supports_clearbhb(int scope)
655 if (scope == SCOPE_LOCAL_CPU)
656 isar2 = read_sysreg_s(SYS_ID_AA64ISAR2_EL1);
658 isar2 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1);
660 return cpuid_feature_extract_unsigned_field(isar2,
661 ID_AA64ISAR2_EL1_CLRBHB_SHIFT);
664 const struct cpumask *system_32bit_el0_cpumask(void);
665 DECLARE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0);
667 static inline bool system_supports_32bit_el0(void)
669 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
671 return static_branch_unlikely(&arm64_mismatched_32bit_el0) ||
672 id_aa64pfr0_32bit_el0(pfr0);
675 static inline bool system_supports_4kb_granule(void)
680 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
681 val = cpuid_feature_extract_unsigned_field(mmfr0,
682 ID_AA64MMFR0_EL1_TGRAN4_SHIFT);
684 return (val >= ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN) &&
685 (val <= ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX);
688 static inline bool system_supports_64kb_granule(void)
693 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
694 val = cpuid_feature_extract_unsigned_field(mmfr0,
695 ID_AA64MMFR0_EL1_TGRAN64_SHIFT);
697 return (val >= ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN) &&
698 (val <= ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX);
701 static inline bool system_supports_16kb_granule(void)
706 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
707 val = cpuid_feature_extract_unsigned_field(mmfr0,
708 ID_AA64MMFR0_EL1_TGRAN16_SHIFT);
710 return (val >= ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN) &&
711 (val <= ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX);
714 static inline bool system_supports_mixed_endian_el0(void)
716 return id_aa64mmfr0_mixed_endian_el0(read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1));
719 static inline bool system_supports_mixed_endian(void)
724 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
725 val = cpuid_feature_extract_unsigned_field(mmfr0,
726 ID_AA64MMFR0_EL1_BIGEND_SHIFT);
731 static __always_inline bool system_supports_fpsimd(void)
733 return alternative_has_cap_likely(ARM64_HAS_FPSIMD);
736 static inline bool system_uses_hw_pan(void)
738 return alternative_has_cap_unlikely(ARM64_HAS_PAN);
741 static inline bool system_uses_ttbr0_pan(void)
743 return IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN) &&
744 !system_uses_hw_pan();
747 static __always_inline bool system_supports_sve(void)
749 return alternative_has_cap_unlikely(ARM64_SVE);
752 static __always_inline bool system_supports_sme(void)
754 return alternative_has_cap_unlikely(ARM64_SME);
757 static __always_inline bool system_supports_sme2(void)
759 return alternative_has_cap_unlikely(ARM64_SME2);
762 static __always_inline bool system_supports_fa64(void)
764 return alternative_has_cap_unlikely(ARM64_SME_FA64);
767 static __always_inline bool system_supports_tpidr2(void)
769 return system_supports_sme();
772 static __always_inline bool system_supports_fpmr(void)
774 return alternative_has_cap_unlikely(ARM64_HAS_FPMR);
777 static __always_inline bool system_supports_cnp(void)
779 return alternative_has_cap_unlikely(ARM64_HAS_CNP);
782 static inline bool system_supports_address_auth(void)
784 return cpus_have_final_boot_cap(ARM64_HAS_ADDRESS_AUTH);
787 static inline bool system_supports_generic_auth(void)
789 return alternative_has_cap_unlikely(ARM64_HAS_GENERIC_AUTH);
792 static inline bool system_has_full_ptr_auth(void)
794 return system_supports_address_auth() && system_supports_generic_auth();
797 static __always_inline bool system_uses_irq_prio_masking(void)
799 return alternative_has_cap_unlikely(ARM64_HAS_GIC_PRIO_MASKING);
802 static inline bool system_supports_mte(void)
804 return alternative_has_cap_unlikely(ARM64_MTE);
807 static inline bool system_has_prio_mask_debugging(void)
809 return IS_ENABLED(CONFIG_ARM64_DEBUG_PRIORITY_MASKING) &&
810 system_uses_irq_prio_masking();
813 static inline bool system_supports_bti(void)
815 return cpus_have_final_cap(ARM64_BTI);
818 static inline bool system_supports_bti_kernel(void)
820 return IS_ENABLED(CONFIG_ARM64_BTI_KERNEL) &&
821 cpus_have_final_boot_cap(ARM64_BTI);
824 static inline bool system_supports_tlb_range(void)
826 return alternative_has_cap_unlikely(ARM64_HAS_TLB_RANGE);
829 static inline bool system_supports_lpa2(void)
831 return cpus_have_final_cap(ARM64_HAS_LPA2);
834 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt);
835 bool try_emulate_mrs(struct pt_regs *regs, u32 isn);
837 static inline u32 id_aa64mmfr0_parange_to_phys_shift(int parange)
840 case ID_AA64MMFR0_EL1_PARANGE_32: return 32;
841 case ID_AA64MMFR0_EL1_PARANGE_36: return 36;
842 case ID_AA64MMFR0_EL1_PARANGE_40: return 40;
843 case ID_AA64MMFR0_EL1_PARANGE_42: return 42;
844 case ID_AA64MMFR0_EL1_PARANGE_44: return 44;
845 case ID_AA64MMFR0_EL1_PARANGE_48: return 48;
846 case ID_AA64MMFR0_EL1_PARANGE_52: return 52;
848 * A future PE could use a value unknown to the kernel.
849 * However, by the "D10.1.4 Principles of the ID scheme
850 * for fields in ID registers", ARM DDI 0487C.a, any new
851 * value is guaranteed to be higher than what we know already.
852 * As a safe limit, we return the limit supported by the kernel.
854 default: return CONFIG_ARM64_PA_BITS;
858 /* Check whether hardware update of the Access flag is supported */
859 static inline bool cpu_has_hw_af(void)
863 if (!IS_ENABLED(CONFIG_ARM64_HW_AFDBM))
867 * Use cached version to avoid emulated msr operation on KVM
870 mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
871 return cpuid_feature_extract_unsigned_field(mmfr1,
872 ID_AA64MMFR1_EL1_HAFDBS_SHIFT);
875 static inline bool cpu_has_pan(void)
877 u64 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
878 return cpuid_feature_extract_unsigned_field(mmfr1,
879 ID_AA64MMFR1_EL1_PAN_SHIFT);
882 #ifdef CONFIG_ARM64_AMU_EXTN
883 /* Check whether the cpu supports the Activity Monitors Unit (AMU) */
884 extern bool cpu_has_amu_feat(int cpu);
886 static inline bool cpu_has_amu_feat(int cpu)
892 /* Get a cpu that supports the Activity Monitors Unit (AMU) */
893 extern int get_cpu_with_amu_feat(void);
895 static inline unsigned int get_vmid_bits(u64 mmfr1)
899 vmid_bits = cpuid_feature_extract_unsigned_field(mmfr1,
900 ID_AA64MMFR1_EL1_VMIDBits_SHIFT);
901 if (vmid_bits == ID_AA64MMFR1_EL1_VMIDBits_16)
905 * Return the default here even if any reserved
906 * value is fetched from the system register.
911 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, s64 cur);
912 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id);
914 extern struct arm64_ftr_override id_aa64mmfr0_override;
915 extern struct arm64_ftr_override id_aa64mmfr1_override;
916 extern struct arm64_ftr_override id_aa64mmfr2_override;
917 extern struct arm64_ftr_override id_aa64pfr0_override;
918 extern struct arm64_ftr_override id_aa64pfr1_override;
919 extern struct arm64_ftr_override id_aa64zfr0_override;
920 extern struct arm64_ftr_override id_aa64smfr0_override;
921 extern struct arm64_ftr_override id_aa64isar1_override;
922 extern struct arm64_ftr_override id_aa64isar2_override;
924 extern struct arm64_ftr_override arm64_sw_feature_override;
927 u64 arm64_apply_feature_override(u64 val, int feat, int width,
928 const struct arm64_ftr_override *override)
930 u64 oval = override->val;
933 * When it encounters an invalid override (e.g., an override that
934 * cannot be honoured due to a missing CPU feature), the early idreg
935 * override code will set the mask to 0x0 and the value to non-zero for
936 * the field in question. In order to determine whether the override is
937 * valid or not for the field we are interested in, we first need to
938 * disregard bits belonging to other fields.
940 oval &= GENMASK_ULL(feat + width - 1, feat);
943 * The override is valid if all value bits are accounted for in the
944 * mask. If so, replace the masked bits with the override value.
946 if (oval == (oval & override->mask)) {
947 val &= ~override->mask;
951 /* Extract the field from the updated value */
952 return cpuid_feature_extract_unsigned_field(val, feat);
955 static inline bool arm64_test_sw_feature_override(int feat)
958 * Software features are pseudo CPU features that have no underlying
959 * CPUID system register value to apply the override to.
961 return arm64_apply_feature_override(0, feat, 4,
962 &arm64_sw_feature_override);
965 static inline bool kaslr_disabled_cmdline(void)
967 return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_NOKASLR);
970 u32 get_kvm_ipa_limit(void);
971 void dump_cpu_features(void);
973 static inline bool cpu_has_bti(void)
975 if (!IS_ENABLED(CONFIG_ARM64_BTI))
978 return arm64_apply_feature_override(read_cpuid(ID_AA64PFR1_EL1),
979 ID_AA64PFR1_EL1_BT_SHIFT, 4,
980 &id_aa64pfr1_override);
983 static inline bool cpu_has_pac(void)
987 if (!IS_ENABLED(CONFIG_ARM64_PTR_AUTH))
990 isar1 = read_cpuid(ID_AA64ISAR1_EL1);
991 isar2 = read_cpuid(ID_AA64ISAR2_EL1);
993 if (arm64_apply_feature_override(isar1, ID_AA64ISAR1_EL1_APA_SHIFT, 4,
994 &id_aa64isar1_override))
997 if (arm64_apply_feature_override(isar1, ID_AA64ISAR1_EL1_API_SHIFT, 4,
998 &id_aa64isar1_override))
1001 return arm64_apply_feature_override(isar2, ID_AA64ISAR2_EL1_APA3_SHIFT, 4,
1002 &id_aa64isar2_override);
1005 static inline bool cpu_has_lva(void)
1009 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1);
1010 mmfr2 &= ~id_aa64mmfr2_override.mask;
1011 mmfr2 |= id_aa64mmfr2_override.val;
1012 return cpuid_feature_extract_unsigned_field(mmfr2,
1013 ID_AA64MMFR2_EL1_VARange_SHIFT);
1016 static inline bool cpu_has_lpa2(void)
1018 #ifdef CONFIG_ARM64_LPA2
1022 mmfr0 = read_sysreg(id_aa64mmfr0_el1);
1023 mmfr0 &= ~id_aa64mmfr0_override.mask;
1024 mmfr0 |= id_aa64mmfr0_override.val;
1025 feat = cpuid_feature_extract_signed_field(mmfr0,
1026 ID_AA64MMFR0_EL1_TGRAN_SHIFT);
1028 return feat >= ID_AA64MMFR0_EL1_TGRAN_LPA2;
1034 #endif /* __ASSEMBLY__ */