1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
6 #ifndef __ASM_CPUFEATURE_H
7 #define __ASM_CPUFEATURE_H
9 #include <asm/cpucaps.h>
10 #include <asm/cputype.h>
11 #include <asm/hwcap.h>
12 #include <asm/sysreg.h>
14 #define MAX_CPU_FEATURES 64
15 #define cpu_feature(x) KERNEL_HWCAP_ ## x
19 #include <linux/bug.h>
20 #include <linux/jump_label.h>
21 #include <linux/kernel.h>
24 * CPU feature register tracking
26 * The safe value of a CPUID feature field is dependent on the implications
27 * of the values assigned to it by the architecture. Based on the relationship
28 * between the values, the features are classified into 3 types - LOWER_SAFE,
29 * HIGHER_SAFE and EXACT.
31 * The lowest value of all the CPUs is chosen for LOWER_SAFE and highest
32 * for HIGHER_SAFE. It is expected that all CPUs have the same value for
33 * a field when EXACT is specified, failing which, the safe value specified
34 * in the table is chosen.
38 FTR_EXACT, /* Use a predefined safe value */
39 FTR_LOWER_SAFE, /* Smaller value is safe */
40 FTR_HIGHER_SAFE, /* Bigger value is safe */
41 FTR_HIGHER_OR_ZERO_SAFE, /* Bigger value is safe, but 0 is biggest */
44 #define FTR_STRICT true /* SANITY check strict matching required */
45 #define FTR_NONSTRICT false /* SANITY check ignored */
47 #define FTR_SIGNED true /* Value should be treated as signed */
48 #define FTR_UNSIGNED false /* Value should be treated as unsigned */
50 #define FTR_VISIBLE true /* Feature visible to the user space */
51 #define FTR_HIDDEN false /* Feature is hidden from the user */
53 #define FTR_VISIBLE_IF_IS_ENABLED(config) \
54 (IS_ENABLED(config) ? FTR_VISIBLE : FTR_HIDDEN)
56 struct arm64_ftr_bits {
57 bool sign; /* Value is signed ? */
59 bool strict; /* CPU Sanity check: strict matching required ? */
63 s64 safe_val; /* safe value for FTR_EXACT features */
66 struct arm64_ftr_override {
72 * @arm64_ftr_reg - Feature register
73 * @strict_mask Bits which should match across all CPUs for sanity.
74 * @sys_val Safe value across the CPUs (system view)
76 struct arm64_ftr_reg {
82 struct arm64_ftr_override *override;
83 const struct arm64_ftr_bits *ftr_bits;
86 extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0;
91 * We use arm64_cpu_capabilities to represent system features, errata work
92 * arounds (both used internally by kernel and tracked in cpu_hwcaps) and
93 * ELF HWCAPs (which are exposed to user).
95 * To support systems with heterogeneous CPUs, we need to make sure that we
96 * detect the capabilities correctly on the system and take appropriate
97 * measures to ensure there are no incompatibilities.
99 * This comment tries to explain how we treat the capabilities.
100 * Each capability has the following list of attributes :
102 * 1) Scope of Detection : The system detects a given capability by
103 * performing some checks at runtime. This could be, e.g, checking the
104 * value of a field in CPU ID feature register or checking the cpu
105 * model. The capability provides a call back ( @matches() ) to
106 * perform the check. Scope defines how the checks should be performed.
107 * There are three cases:
109 * a) SCOPE_LOCAL_CPU: check all the CPUs and "detect" if at least one
110 * matches. This implies, we have to run the check on all the
111 * booting CPUs, until the system decides that state of the
112 * capability is finalised. (See section 2 below)
114 * b) SCOPE_SYSTEM: check all the CPUs and "detect" if all the CPUs
115 * matches. This implies, we run the check only once, when the
116 * system decides to finalise the state of the capability. If the
117 * capability relies on a field in one of the CPU ID feature
118 * registers, we use the sanitised value of the register from the
119 * CPU feature infrastructure to make the decision.
121 * c) SCOPE_BOOT_CPU: Check only on the primary boot CPU to detect the
122 * feature. This category is for features that are "finalised"
123 * (or used) by the kernel very early even before the SMP cpus
126 * The process of detection is usually denoted by "update" capability
129 * 2) Finalise the state : The kernel should finalise the state of a
130 * capability at some point during its execution and take necessary
131 * actions if any. Usually, this is done, after all the boot-time
132 * enabled CPUs are brought up by the kernel, so that it can make
133 * better decision based on the available set of CPUs. However, there
134 * are some special cases, where the action is taken during the early
135 * boot by the primary boot CPU. (e.g, running the kernel at EL2 with
136 * Virtualisation Host Extensions). The kernel usually disallows any
137 * changes to the state of a capability once it finalises the capability
138 * and takes any action, as it may be impossible to execute the actions
139 * safely. A CPU brought up after a capability is "finalised" is
140 * referred to as "Late CPU" w.r.t the capability. e.g, all secondary
141 * CPUs are treated "late CPUs" for capabilities determined by the boot
144 * At the moment there are two passes of finalising the capabilities.
145 * a) Boot CPU scope capabilities - Finalised by primary boot CPU via
146 * setup_boot_cpu_capabilities().
147 * b) Everything except (a) - Run via setup_system_capabilities().
149 * 3) Verification: When a CPU is brought online (e.g, by user or by the
150 * kernel), the kernel should make sure that it is safe to use the CPU,
151 * by verifying that the CPU is compliant with the state of the
152 * capabilities finalised already. This happens via :
154 * secondary_start_kernel()-> check_local_cpu_capabilities()
156 * As explained in (2) above, capabilities could be finalised at
157 * different points in the execution. Each newly booted CPU is verified
158 * against the capabilities that have been finalised by the time it
161 * a) SCOPE_BOOT_CPU : All CPUs are verified against the capability
162 * except for the primary boot CPU.
164 * b) SCOPE_LOCAL_CPU, SCOPE_SYSTEM: All CPUs hotplugged on by the
165 * user after the kernel boot are verified against the capability.
167 * If there is a conflict, the kernel takes an action, based on the
168 * severity (e.g, a CPU could be prevented from booting or cause a
169 * kernel panic). The CPU is allowed to "affect" the state of the
170 * capability, if it has not been finalised already. See section 5
171 * for more details on conflicts.
173 * 4) Action: As mentioned in (2), the kernel can take an action for each
174 * detected capability, on all CPUs on the system. Appropriate actions
175 * include, turning on an architectural feature, modifying the control
176 * registers (e.g, SCTLR, TCR etc.) or patching the kernel via
177 * alternatives. The kernel patching is batched and performed at later
178 * point. The actions are always initiated only after the capability
179 * is finalised. This is usally denoted by "enabling" the capability.
180 * The actions are initiated as follows :
181 * a) Action is triggered on all online CPUs, after the capability is
182 * finalised, invoked within the stop_machine() context from
183 * enable_cpu_capabilitie().
185 * b) Any late CPU, brought up after (1), the action is triggered via:
187 * check_local_cpu_capabilities() -> verify_local_cpu_capabilities()
189 * 5) Conflicts: Based on the state of the capability on a late CPU vs.
190 * the system state, we could have the following combinations :
192 * x-----------------------------x
193 * | Type | System | Late CPU |
194 * |-----------------------------|
196 * |-----------------------------|
198 * x-----------------------------x
200 * Two separate flag bits are defined to indicate whether each kind of
201 * conflict can be allowed:
202 * ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU - Case(a) is allowed
203 * ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU - Case(b) is allowed
205 * Case (a) is not permitted for a capability that the system requires
206 * all CPUs to have in order for the capability to be enabled. This is
207 * typical for capabilities that represent enhanced functionality.
209 * Case (b) is not permitted for a capability that must be enabled
210 * during boot if any CPU in the system requires it in order to run
211 * safely. This is typical for erratum work arounds that cannot be
212 * enabled after the corresponding capability is finalised.
214 * In some non-typical cases either both (a) and (b), or neither,
215 * should be permitted. This can be described by including neither
216 * or both flags in the capability's type field.
218 * In case of a conflict, the CPU is prevented from booting. If the
219 * ARM64_CPUCAP_PANIC_ON_CONFLICT flag is specified for the capability,
220 * then a kernel panic is triggered.
225 * Decide how the capability is detected.
226 * On any local CPU vs System wide vs the primary boot CPU
228 #define ARM64_CPUCAP_SCOPE_LOCAL_CPU ((u16)BIT(0))
229 #define ARM64_CPUCAP_SCOPE_SYSTEM ((u16)BIT(1))
231 * The capabilitiy is detected on the Boot CPU and is used by kernel
232 * during early boot. i.e, the capability should be "detected" and
233 * "enabled" as early as possibly on all booting CPUs.
235 #define ARM64_CPUCAP_SCOPE_BOOT_CPU ((u16)BIT(2))
236 #define ARM64_CPUCAP_SCOPE_MASK \
237 (ARM64_CPUCAP_SCOPE_SYSTEM | \
238 ARM64_CPUCAP_SCOPE_LOCAL_CPU | \
239 ARM64_CPUCAP_SCOPE_BOOT_CPU)
241 #define SCOPE_SYSTEM ARM64_CPUCAP_SCOPE_SYSTEM
242 #define SCOPE_LOCAL_CPU ARM64_CPUCAP_SCOPE_LOCAL_CPU
243 #define SCOPE_BOOT_CPU ARM64_CPUCAP_SCOPE_BOOT_CPU
244 #define SCOPE_ALL ARM64_CPUCAP_SCOPE_MASK
247 * Is it permitted for a late CPU to have this capability when system
248 * hasn't already enabled it ?
250 #define ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU ((u16)BIT(4))
251 /* Is it safe for a late CPU to miss this capability when system has it */
252 #define ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU ((u16)BIT(5))
253 /* Panic when a conflict is detected */
254 #define ARM64_CPUCAP_PANIC_ON_CONFLICT ((u16)BIT(6))
257 * CPU errata workarounds that need to be enabled at boot time if one or
258 * more CPUs in the system requires it. When one of these capabilities
259 * has been enabled, it is safe to allow any CPU to boot that doesn't
260 * require the workaround. However, it is not safe if a "late" CPU
261 * requires a workaround and the system hasn't enabled it already.
263 #define ARM64_CPUCAP_LOCAL_CPU_ERRATUM \
264 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU)
266 * CPU feature detected at boot time based on system-wide value of a
267 * feature. It is safe for a late CPU to have this feature even though
268 * the system hasn't enabled it, although the feature will not be used
269 * by Linux in this case. If the system has enabled this feature already,
270 * then every late CPU must have it.
272 #define ARM64_CPUCAP_SYSTEM_FEATURE \
273 (ARM64_CPUCAP_SCOPE_SYSTEM | ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
275 * CPU feature detected at boot time based on feature of one or more CPUs.
276 * All possible conflicts for a late CPU are ignored.
277 * NOTE: this means that a late CPU with the feature will *not* cause the
278 * capability to be advertised by cpus_have_*cap()!
280 #define ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE \
281 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | \
282 ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU | \
283 ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
286 * CPU feature detected at boot time, on one or more CPUs. A late CPU
287 * is not allowed to have the capability when the system doesn't have it.
288 * It is Ok for a late CPU to miss the feature.
290 #define ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE \
291 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | \
292 ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU)
295 * CPU feature used early in the boot based on the boot CPU. All secondary
296 * CPUs must match the state of the capability as detected by the boot CPU. In
297 * case of a conflict, a kernel panic is triggered.
299 #define ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE \
300 (ARM64_CPUCAP_SCOPE_BOOT_CPU | ARM64_CPUCAP_PANIC_ON_CONFLICT)
303 * CPU feature used early in the boot based on the boot CPU. It is safe for a
304 * late CPU to have this feature even though the boot CPU hasn't enabled it,
305 * although the feature will not be used by Linux in this case. If the boot CPU
306 * has enabled this feature already, then every late CPU must have it.
308 #define ARM64_CPUCAP_BOOT_CPU_FEATURE \
309 (ARM64_CPUCAP_SCOPE_BOOT_CPU | ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
311 struct arm64_cpu_capabilities {
315 bool (*matches)(const struct arm64_cpu_capabilities *caps, int scope);
317 * Take the appropriate actions to configure this capability
318 * for this CPU. If the capability is detected by the kernel
319 * this will be called on all the CPUs in the system,
320 * including the hotplugged CPUs, regardless of whether the
321 * capability is available on that specific CPU. This is
322 * useful for some capabilities (e.g, working around CPU
323 * errata), where all the CPUs must take some action (e.g,
324 * changing system control/configuration). Thus, if an action
325 * is required only if the CPU has the capability, then the
326 * routine must check it before taking any action.
328 void (*cpu_enable)(const struct arm64_cpu_capabilities *cap);
330 struct { /* To be used for erratum handling only */
331 struct midr_range midr_range;
332 const struct arm64_midr_revidr {
333 u32 midr_rv; /* revision/variant */
335 } * const fixed_revs;
338 const struct midr_range *midr_range_list;
339 struct { /* Feature register checking */
350 * An optional list of "matches/cpu_enable" pair for the same
351 * "capability" of the same "type" as described by the parent.
352 * Only matches(), cpu_enable() and fields relevant to these
353 * methods are significant in the list. The cpu_enable is
354 * invoked only if the corresponding entry "matches()".
355 * However, if a cpu_enable() method is associated
356 * with multiple matches(), care should be taken that either
357 * the match criteria are mutually exclusive, or that the
358 * method is robust against being called multiple times.
360 const struct arm64_cpu_capabilities *match_list;
363 static inline int cpucap_default_scope(const struct arm64_cpu_capabilities *cap)
365 return cap->type & ARM64_CPUCAP_SCOPE_MASK;
369 * Generic helper for handling capabilities with multiple (match,enable) pairs
370 * of call backs, sharing the same capability bit.
371 * Iterate over each entry to see if at least one matches.
374 cpucap_multi_entry_cap_matches(const struct arm64_cpu_capabilities *entry,
377 const struct arm64_cpu_capabilities *caps;
379 for (caps = entry->match_list; caps->matches; caps++)
380 if (caps->matches(caps, scope))
386 static __always_inline bool is_vhe_hyp_code(void)
388 /* Only defined for code run in VHE hyp context */
389 return __is_defined(__KVM_VHE_HYPERVISOR__);
392 static __always_inline bool is_nvhe_hyp_code(void)
394 /* Only defined for code run in NVHE hyp context */
395 return __is_defined(__KVM_NVHE_HYPERVISOR__);
398 static __always_inline bool is_hyp_code(void)
400 return is_vhe_hyp_code() || is_nvhe_hyp_code();
403 extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
404 extern struct static_key_false cpu_hwcap_keys[ARM64_NCAPS];
405 extern struct static_key_false arm64_const_caps_ready;
407 /* ARM64 CAPS + alternative_cb */
408 #define ARM64_NPATCHABLE (ARM64_NCAPS + 1)
409 extern DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
411 #define for_each_available_cap(cap) \
412 for_each_set_bit(cap, cpu_hwcaps, ARM64_NCAPS)
414 bool this_cpu_has_cap(unsigned int cap);
415 void cpu_set_feature(unsigned int num);
416 bool cpu_have_feature(unsigned int num);
417 unsigned long cpu_get_elf_hwcap(void);
418 unsigned long cpu_get_elf_hwcap2(void);
420 #define cpu_set_named_feature(name) cpu_set_feature(cpu_feature(name))
421 #define cpu_have_named_feature(name) cpu_have_feature(cpu_feature(name))
423 static __always_inline bool system_capabilities_finalized(void)
425 return static_branch_likely(&arm64_const_caps_ready);
429 * Test for a capability with a runtime check.
431 * Before the capability is detected, this returns false.
433 static inline bool cpus_have_cap(unsigned int num)
435 if (num >= ARM64_NCAPS)
437 return test_bit(num, cpu_hwcaps);
441 * Test for a capability without a runtime check.
443 * Before capabilities are finalized, this returns false.
444 * After capabilities are finalized, this is patched to avoid a runtime check.
446 * @num must be a compile-time constant.
448 static __always_inline bool __cpus_have_const_cap(int num)
450 if (num >= ARM64_NCAPS)
452 return static_branch_unlikely(&cpu_hwcap_keys[num]);
456 * Test for a capability without a runtime check.
458 * Before capabilities are finalized, this will BUG().
459 * After capabilities are finalized, this is patched to avoid a runtime check.
461 * @num must be a compile-time constant.
463 static __always_inline bool cpus_have_final_cap(int num)
465 if (system_capabilities_finalized())
466 return __cpus_have_const_cap(num);
472 * Test for a capability, possibly with a runtime check for non-hyp code.
474 * For hyp code, this behaves the same as cpus_have_final_cap().
477 * Before capabilities are finalized, this behaves as cpus_have_cap().
478 * After capabilities are finalized, this is patched to avoid a runtime check.
480 * @num must be a compile-time constant.
482 static __always_inline bool cpus_have_const_cap(int num)
485 return cpus_have_final_cap(num);
486 else if (system_capabilities_finalized())
487 return __cpus_have_const_cap(num);
489 return cpus_have_cap(num);
492 static inline void cpus_set_cap(unsigned int num)
494 if (num >= ARM64_NCAPS) {
495 pr_warn("Attempt to set an illegal CPU capability (%d >= %d)\n",
498 __set_bit(num, cpu_hwcaps);
502 static inline int __attribute_const__
503 cpuid_feature_extract_signed_field_width(u64 features, int field, int width)
505 return (s64)(features << (64 - width - field)) >> (64 - width);
508 static inline int __attribute_const__
509 cpuid_feature_extract_signed_field(u64 features, int field)
511 return cpuid_feature_extract_signed_field_width(features, field, 4);
514 static __always_inline unsigned int __attribute_const__
515 cpuid_feature_extract_unsigned_field_width(u64 features, int field, int width)
517 return (u64)(features << (64 - width - field)) >> (64 - width);
520 static __always_inline unsigned int __attribute_const__
521 cpuid_feature_extract_unsigned_field(u64 features, int field)
523 return cpuid_feature_extract_unsigned_field_width(features, field, 4);
527 * Fields that identify the version of the Performance Monitors Extension do
528 * not follow the standard ID scheme. See ARM DDI 0487E.a page D13-2825,
529 * "Alternative ID scheme used for the Performance Monitors Extension version".
531 static inline u64 __attribute_const__
532 cpuid_feature_cap_perfmon_field(u64 features, int field, u64 cap)
534 u64 val = cpuid_feature_extract_unsigned_field(features, field);
535 u64 mask = GENMASK_ULL(field + 3, field);
537 /* Treat IMPLEMENTATION DEFINED functionality as unimplemented */
543 features |= (cap << field) & mask;
549 static inline u64 arm64_ftr_mask(const struct arm64_ftr_bits *ftrp)
551 return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift);
554 static inline u64 arm64_ftr_reg_user_value(const struct arm64_ftr_reg *reg)
556 return (reg->user_val | (reg->sys_val & reg->user_mask));
559 static inline int __attribute_const__
560 cpuid_feature_extract_field_width(u64 features, int field, int width, bool sign)
563 cpuid_feature_extract_signed_field_width(features, field, width) :
564 cpuid_feature_extract_unsigned_field_width(features, field, width);
567 static inline int __attribute_const__
568 cpuid_feature_extract_field(u64 features, int field, bool sign)
570 return cpuid_feature_extract_field_width(features, field, 4, sign);
573 static inline s64 arm64_ftr_value(const struct arm64_ftr_bits *ftrp, u64 val)
575 return (s64)cpuid_feature_extract_field_width(val, ftrp->shift, ftrp->width, ftrp->sign);
578 static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)
580 return cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL_SHIFT) == 0x1 ||
581 cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL0_SHIFT) == 0x1;
584 static inline bool id_aa64pfr0_32bit_el1(u64 pfr0)
586 u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_SHIFT);
588 return val == ID_AA64PFR0_EL1_32BIT_64BIT;
591 static inline bool id_aa64pfr0_32bit_el0(u64 pfr0)
593 u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL0_SHIFT);
595 return val == ID_AA64PFR0_EL0_32BIT_64BIT;
598 static inline bool id_aa64pfr0_sve(u64 pfr0)
600 u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_SVE_SHIFT);
605 void __init setup_cpu_features(void);
606 void check_local_cpu_capabilities(void);
608 u64 read_sanitised_ftr_reg(u32 id);
609 u64 __read_sysreg_by_encoding(u32 sys_id);
611 static inline bool cpu_supports_mixed_endian_el0(void)
613 return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1));
616 static inline bool system_supports_32bit_el0(void)
618 return cpus_have_const_cap(ARM64_HAS_32BIT_EL0);
621 static inline bool system_supports_4kb_granule(void)
626 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
627 val = cpuid_feature_extract_unsigned_field(mmfr0,
628 ID_AA64MMFR0_TGRAN4_SHIFT);
630 return val == ID_AA64MMFR0_TGRAN4_SUPPORTED;
633 static inline bool system_supports_64kb_granule(void)
638 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
639 val = cpuid_feature_extract_unsigned_field(mmfr0,
640 ID_AA64MMFR0_TGRAN64_SHIFT);
642 return val == ID_AA64MMFR0_TGRAN64_SUPPORTED;
645 static inline bool system_supports_16kb_granule(void)
650 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
651 val = cpuid_feature_extract_unsigned_field(mmfr0,
652 ID_AA64MMFR0_TGRAN16_SHIFT);
654 return val == ID_AA64MMFR0_TGRAN16_SUPPORTED;
657 static inline bool system_supports_mixed_endian_el0(void)
659 return id_aa64mmfr0_mixed_endian_el0(read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1));
662 static inline bool system_supports_mixed_endian(void)
667 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
668 val = cpuid_feature_extract_unsigned_field(mmfr0,
669 ID_AA64MMFR0_BIGENDEL_SHIFT);
674 static __always_inline bool system_supports_fpsimd(void)
676 return !cpus_have_const_cap(ARM64_HAS_NO_FPSIMD);
679 static inline bool system_uses_hw_pan(void)
681 return IS_ENABLED(CONFIG_ARM64_PAN) &&
682 cpus_have_const_cap(ARM64_HAS_PAN);
685 static inline bool system_uses_ttbr0_pan(void)
687 return IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN) &&
688 !system_uses_hw_pan();
691 static __always_inline bool system_supports_sve(void)
693 return IS_ENABLED(CONFIG_ARM64_SVE) &&
694 cpus_have_const_cap(ARM64_SVE);
697 static __always_inline bool system_supports_cnp(void)
699 return IS_ENABLED(CONFIG_ARM64_CNP) &&
700 cpus_have_const_cap(ARM64_HAS_CNP);
703 static inline bool system_supports_address_auth(void)
705 return IS_ENABLED(CONFIG_ARM64_PTR_AUTH) &&
706 cpus_have_const_cap(ARM64_HAS_ADDRESS_AUTH);
709 static inline bool system_supports_generic_auth(void)
711 return IS_ENABLED(CONFIG_ARM64_PTR_AUTH) &&
712 cpus_have_const_cap(ARM64_HAS_GENERIC_AUTH);
715 static inline bool system_has_full_ptr_auth(void)
717 return system_supports_address_auth() && system_supports_generic_auth();
720 static __always_inline bool system_uses_irq_prio_masking(void)
722 return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) &&
723 cpus_have_const_cap(ARM64_HAS_IRQ_PRIO_MASKING);
726 static inline bool system_supports_mte(void)
728 return IS_ENABLED(CONFIG_ARM64_MTE) &&
729 cpus_have_const_cap(ARM64_MTE);
732 static inline bool system_has_prio_mask_debugging(void)
734 return IS_ENABLED(CONFIG_ARM64_DEBUG_PRIORITY_MASKING) &&
735 system_uses_irq_prio_masking();
738 static inline bool system_supports_bti(void)
740 return IS_ENABLED(CONFIG_ARM64_BTI) && cpus_have_const_cap(ARM64_BTI);
743 static inline bool system_supports_tlb_range(void)
745 return IS_ENABLED(CONFIG_ARM64_TLB_RANGE) &&
746 cpus_have_const_cap(ARM64_HAS_TLB_RANGE);
749 extern int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt);
751 static inline u32 id_aa64mmfr0_parange_to_phys_shift(int parange)
762 * A future PE could use a value unknown to the kernel.
763 * However, by the "D10.1.4 Principles of the ID scheme
764 * for fields in ID registers", ARM DDI 0487C.a, any new
765 * value is guaranteed to be higher than what we know already.
766 * As a safe limit, we return the limit supported by the kernel.
768 default: return CONFIG_ARM64_PA_BITS;
772 /* Check whether hardware update of the Access flag is supported */
773 static inline bool cpu_has_hw_af(void)
777 if (!IS_ENABLED(CONFIG_ARM64_HW_AFDBM))
780 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
781 return cpuid_feature_extract_unsigned_field(mmfr1,
782 ID_AA64MMFR1_HADBS_SHIFT);
785 static inline bool cpu_has_pan(void)
787 u64 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
788 return cpuid_feature_extract_unsigned_field(mmfr1,
789 ID_AA64MMFR1_PAN_SHIFT);
792 #ifdef CONFIG_ARM64_AMU_EXTN
793 /* Check whether the cpu supports the Activity Monitors Unit (AMU) */
794 extern bool cpu_has_amu_feat(int cpu);
796 static inline bool cpu_has_amu_feat(int cpu)
802 /* Get a cpu that supports the Activity Monitors Unit (AMU) */
803 extern int get_cpu_with_amu_feat(void);
805 static inline unsigned int get_vmid_bits(u64 mmfr1)
809 vmid_bits = cpuid_feature_extract_unsigned_field(mmfr1,
810 ID_AA64MMFR1_VMIDBITS_SHIFT);
811 if (vmid_bits == ID_AA64MMFR1_VMIDBITS_16)
815 * Return the default here even if any reserved
816 * value is fetched from the system register.
821 extern struct arm64_ftr_override id_aa64mmfr1_override;
822 extern struct arm64_ftr_override id_aa64pfr1_override;
823 extern struct arm64_ftr_override id_aa64isar1_override;
825 u32 get_kvm_ipa_limit(void);
826 void dump_cpu_features(void);
828 #endif /* __ASSEMBLY__ */