1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Based on arch/arm/include/asm/atomic.h
5 * Copyright (C) 1996 Russell King.
6 * Copyright (C) 2002 Deep Blue Solutions Ltd.
7 * Copyright (C) 2012 ARM Ltd.
10 #ifndef __ASM_ATOMIC_LL_SC_H
11 #define __ASM_ATOMIC_LL_SC_H
13 #include <linux/stringify.h>
15 #ifdef CONFIG_ARM64_LSE_ATOMICS
16 #define __LL_SC_FALLBACK(asm_ops) \
25 #define __LL_SC_FALLBACK(asm_ops) asm_ops
28 #ifndef CONFIG_CC_HAS_K_CONSTRAINT
33 * AArch64 UP and SMP safe atomic ops. We use load exclusive and
34 * store exclusive to ensure that these are atomic. We may loop
35 * to ensure that the update happens.
38 #define ATOMIC_OP(op, asm_op, constraint) \
40 __ll_sc_atomic_##op(int i, atomic_t *v) \
45 asm volatile("// atomic_" #op "\n" \
47 " prfm pstl1strm, %2\n" \
49 " " #asm_op " %w0, %w0, %w3\n" \
50 " stxr %w1, %w0, %2\n" \
52 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
53 : __stringify(constraint) "r" (i)); \
56 #define ATOMIC_OP_RETURN(name, mb, acq, rel, cl, op, asm_op, constraint)\
58 __ll_sc_atomic_##op##_return##name(int i, atomic_t *v) \
63 asm volatile("// atomic_" #op "_return" #name "\n" \
65 " prfm pstl1strm, %2\n" \
66 "1: ld" #acq "xr %w0, %2\n" \
67 " " #asm_op " %w0, %w0, %w3\n" \
68 " st" #rel "xr %w1, %w0, %2\n" \
71 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
72 : __stringify(constraint) "r" (i) \
78 #define ATOMIC_FETCH_OP(name, mb, acq, rel, cl, op, asm_op, constraint) \
80 __ll_sc_atomic_fetch_##op##name(int i, atomic_t *v) \
85 asm volatile("// atomic_fetch_" #op #name "\n" \
87 " prfm pstl1strm, %3\n" \
88 "1: ld" #acq "xr %w0, %3\n" \
89 " " #asm_op " %w1, %w0, %w4\n" \
90 " st" #rel "xr %w2, %w1, %3\n" \
93 : "=&r" (result), "=&r" (val), "=&r" (tmp), "+Q" (v->counter) \
94 : __stringify(constraint) "r" (i) \
100 #define ATOMIC_OPS(...) \
101 ATOMIC_OP(__VA_ARGS__) \
102 ATOMIC_OP_RETURN( , dmb ish, , l, "memory", __VA_ARGS__)\
103 ATOMIC_OP_RETURN(_relaxed, , , , , __VA_ARGS__)\
104 ATOMIC_OP_RETURN(_acquire, , a, , "memory", __VA_ARGS__)\
105 ATOMIC_OP_RETURN(_release, , , l, "memory", __VA_ARGS__)\
106 ATOMIC_FETCH_OP ( , dmb ish, , l, "memory", __VA_ARGS__)\
107 ATOMIC_FETCH_OP (_relaxed, , , , , __VA_ARGS__)\
108 ATOMIC_FETCH_OP (_acquire, , a, , "memory", __VA_ARGS__)\
109 ATOMIC_FETCH_OP (_release, , , l, "memory", __VA_ARGS__)
111 ATOMIC_OPS(add, add, I)
112 ATOMIC_OPS(sub, sub, J)
115 #define ATOMIC_OPS(...) \
116 ATOMIC_OP(__VA_ARGS__) \
117 ATOMIC_FETCH_OP ( , dmb ish, , l, "memory", __VA_ARGS__)\
118 ATOMIC_FETCH_OP (_relaxed, , , , , __VA_ARGS__)\
119 ATOMIC_FETCH_OP (_acquire, , a, , "memory", __VA_ARGS__)\
120 ATOMIC_FETCH_OP (_release, , , l, "memory", __VA_ARGS__)
122 ATOMIC_OPS(and, and, K)
123 ATOMIC_OPS(or, orr, K)
124 ATOMIC_OPS(xor, eor, K)
126 * GAS converts the mysterious and undocumented BIC (immediate) alias to
127 * an AND (immediate) instruction with the immediate inverted. We don't
128 * have a constraint for this, so fall back to register.
130 ATOMIC_OPS(andnot, bic, )
133 #undef ATOMIC_FETCH_OP
134 #undef ATOMIC_OP_RETURN
137 #define ATOMIC64_OP(op, asm_op, constraint) \
139 __ll_sc_atomic64_##op(s64 i, atomic64_t *v) \
144 asm volatile("// atomic64_" #op "\n" \
146 " prfm pstl1strm, %2\n" \
148 " " #asm_op " %0, %0, %3\n" \
149 " stxr %w1, %0, %2\n" \
151 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
152 : __stringify(constraint) "r" (i)); \
155 #define ATOMIC64_OP_RETURN(name, mb, acq, rel, cl, op, asm_op, constraint)\
157 __ll_sc_atomic64_##op##_return##name(s64 i, atomic64_t *v) \
162 asm volatile("// atomic64_" #op "_return" #name "\n" \
164 " prfm pstl1strm, %2\n" \
165 "1: ld" #acq "xr %0, %2\n" \
166 " " #asm_op " %0, %0, %3\n" \
167 " st" #rel "xr %w1, %0, %2\n" \
170 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
171 : __stringify(constraint) "r" (i) \
177 #define ATOMIC64_FETCH_OP(name, mb, acq, rel, cl, op, asm_op, constraint)\
179 __ll_sc_atomic64_fetch_##op##name(s64 i, atomic64_t *v) \
184 asm volatile("// atomic64_fetch_" #op #name "\n" \
186 " prfm pstl1strm, %3\n" \
187 "1: ld" #acq "xr %0, %3\n" \
188 " " #asm_op " %1, %0, %4\n" \
189 " st" #rel "xr %w2, %1, %3\n" \
192 : "=&r" (result), "=&r" (val), "=&r" (tmp), "+Q" (v->counter) \
193 : __stringify(constraint) "r" (i) \
199 #define ATOMIC64_OPS(...) \
200 ATOMIC64_OP(__VA_ARGS__) \
201 ATOMIC64_OP_RETURN(, dmb ish, , l, "memory", __VA_ARGS__) \
202 ATOMIC64_OP_RETURN(_relaxed,, , , , __VA_ARGS__) \
203 ATOMIC64_OP_RETURN(_acquire,, a, , "memory", __VA_ARGS__) \
204 ATOMIC64_OP_RETURN(_release,, , l, "memory", __VA_ARGS__) \
205 ATOMIC64_FETCH_OP (, dmb ish, , l, "memory", __VA_ARGS__) \
206 ATOMIC64_FETCH_OP (_relaxed,, , , , __VA_ARGS__) \
207 ATOMIC64_FETCH_OP (_acquire,, a, , "memory", __VA_ARGS__) \
208 ATOMIC64_FETCH_OP (_release,, , l, "memory", __VA_ARGS__)
210 ATOMIC64_OPS(add, add, I)
211 ATOMIC64_OPS(sub, sub, J)
214 #define ATOMIC64_OPS(...) \
215 ATOMIC64_OP(__VA_ARGS__) \
216 ATOMIC64_FETCH_OP (, dmb ish, , l, "memory", __VA_ARGS__) \
217 ATOMIC64_FETCH_OP (_relaxed,, , , , __VA_ARGS__) \
218 ATOMIC64_FETCH_OP (_acquire,, a, , "memory", __VA_ARGS__) \
219 ATOMIC64_FETCH_OP (_release,, , l, "memory", __VA_ARGS__)
221 ATOMIC64_OPS(and, and, L)
222 ATOMIC64_OPS(or, orr, L)
223 ATOMIC64_OPS(xor, eor, L)
225 * GAS converts the mysterious and undocumented BIC (immediate) alias to
226 * an AND (immediate) instruction with the immediate inverted. We don't
227 * have a constraint for this, so fall back to register.
229 ATOMIC64_OPS(andnot, bic, )
232 #undef ATOMIC64_FETCH_OP
233 #undef ATOMIC64_OP_RETURN
237 __ll_sc_atomic64_dec_if_positive(atomic64_t *v)
242 asm volatile("// atomic64_dec_if_positive\n"
244 " prfm pstl1strm, %2\n"
248 " stlxr %w1, %0, %2\n"
252 : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
259 #define __CMPXCHG_CASE(w, sfx, name, sz, mb, acq, rel, cl, constraint) \
260 static inline u##sz \
261 __ll_sc__cmpxchg_case_##name##sz(volatile void *ptr, \
269 * Sub-word sizes require explicit casting so that the compare \
270 * part of the cmpxchg doesn't end up interpreting non-zero \
271 * upper bits of the register containing "old". \
278 " prfm pstl1strm, %[v]\n" \
279 "1: ld" #acq "xr" #sfx "\t%" #w "[oldval], %[v]\n" \
280 " eor %" #w "[tmp], %" #w "[oldval], %" #w "[old]\n" \
281 " cbnz %" #w "[tmp], 2f\n" \
282 " st" #rel "xr" #sfx "\t%w[tmp], %" #w "[new], %[v]\n" \
283 " cbnz %w[tmp], 1b\n" \
286 : [tmp] "=&r" (tmp), [oldval] "=&r" (oldval), \
287 [v] "+Q" (*(u##sz *)ptr) \
288 : [old] __stringify(constraint) "r" (old), [new] "r" (new) \
295 * Earlier versions of GCC (no later than 8.1.0) appear to incorrectly
296 * handle the 'K' constraint for the value 4294967295 - thus we use no
297 * constraint for 32 bit operations.
299 __CMPXCHG_CASE(w, b, , 8, , , , , K)
300 __CMPXCHG_CASE(w, h, , 16, , , , , K)
301 __CMPXCHG_CASE(w, , , 32, , , , , K)
302 __CMPXCHG_CASE( , , , 64, , , , , L)
303 __CMPXCHG_CASE(w, b, acq_, 8, , a, , "memory", K)
304 __CMPXCHG_CASE(w, h, acq_, 16, , a, , "memory", K)
305 __CMPXCHG_CASE(w, , acq_, 32, , a, , "memory", K)
306 __CMPXCHG_CASE( , , acq_, 64, , a, , "memory", L)
307 __CMPXCHG_CASE(w, b, rel_, 8, , , l, "memory", K)
308 __CMPXCHG_CASE(w, h, rel_, 16, , , l, "memory", K)
309 __CMPXCHG_CASE(w, , rel_, 32, , , l, "memory", K)
310 __CMPXCHG_CASE( , , rel_, 64, , , l, "memory", L)
311 __CMPXCHG_CASE(w, b, mb_, 8, dmb ish, , l, "memory", K)
312 __CMPXCHG_CASE(w, h, mb_, 16, dmb ish, , l, "memory", K)
313 __CMPXCHG_CASE(w, , mb_, 32, dmb ish, , l, "memory", K)
314 __CMPXCHG_CASE( , , mb_, 64, dmb ish, , l, "memory", L)
316 #undef __CMPXCHG_CASE
318 #define __CMPXCHG_DBL(name, mb, rel, cl) \
320 __ll_sc__cmpxchg_double##name(unsigned long old1, \
321 unsigned long old2, \
322 unsigned long new1, \
323 unsigned long new2, \
324 volatile void *ptr) \
326 unsigned long tmp, ret; \
328 asm volatile("// __cmpxchg_double" #name "\n" \
330 " prfm pstl1strm, %2\n" \
331 "1: ldxp %0, %1, %2\n" \
332 " eor %0, %0, %3\n" \
333 " eor %1, %1, %4\n" \
334 " orr %1, %0, %1\n" \
336 " st" #rel "xp %w0, %5, %6, %2\n" \
340 : "=&r" (tmp), "=&r" (ret), "+Q" (*(unsigned long *)ptr) \
341 : "r" (old1), "r" (old2), "r" (new1), "r" (new2) \
347 __CMPXCHG_DBL( , , , )
348 __CMPXCHG_DBL(_mb, dmb ish, l, "memory")
353 #endif /* __ASM_ATOMIC_LL_SC_H */