2 * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S
4 * Copyright (C) 1996-2000 Russell King
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #error "Only include this from assembly code"
23 #ifndef __ASM_ASSEMBLER_H
24 #define __ASM_ASSEMBLER_H
26 #include <asm-generic/export.h>
28 #include <asm/asm-offsets.h>
29 #include <asm/cpufeature.h>
30 #include <asm/debug-monitors.h>
32 #include <asm/pgtable-hwdef.h>
33 #include <asm/ptrace.h>
34 #include <asm/thread_info.h>
36 .macro save_and_disable_daif, flags
49 .macro restore_daif, flags:req
53 /* Only on aarch64 pstate, PSR_D_BIT is different for aarch32 */
54 .macro inherit_daif, pstate:req, tmp:req
55 and \tmp, \pstate, #(PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
59 /* IRQ is the lowest priority flag, unconditionally unmask the rest. */
61 msr daifclr, #(8 | 4 | 1)
65 * Enable and disable interrupts.
75 .macro save_and_disable_irq, flags
80 .macro restore_irq, flags
88 .macro disable_step_tsk, flgs, tmp
89 tbz \flgs, #TIF_SINGLESTEP, 9990f
91 bic \tmp, \tmp, #DBG_MDSCR_SS
93 isb // Synchronise with enable_dbg
97 /* call with daif masked */
98 .macro enable_step_tsk, flgs, tmp
99 tbz \flgs, #TIF_SINGLESTEP, 9990f
101 orr \tmp, \tmp, #DBG_MDSCR_SS
107 * SMP data memory barrier
114 * RAS Error Synchronization barrier
121 * Value prediction barrier
128 * Speculation barrier
131 alternative_if_not ARM64_HAS_SB
141 * Sanitise a 64-bit bounded index wrt speculation, returning zero if out
144 .macro mask_nospec64, idx, limit, tmp
145 sub \tmp, \idx, \limit
147 and \idx, \idx, \tmp, asr #63
161 * Emit an entry into the exception table
163 .macro _asm_extable, from, to
164 .pushsection __ex_table, "a"
166 .long (\from - .), (\to - .)
170 #define USER(l, x...) \
172 _asm_extable 9999b, l
177 lr .req x30 // link register
188 * Select code when configured for BE.
190 #ifdef CONFIG_CPU_BIG_ENDIAN
191 #define CPU_BE(code...) code
193 #define CPU_BE(code...)
197 * Select code when configured for LE.
199 #ifdef CONFIG_CPU_BIG_ENDIAN
200 #define CPU_LE(code...)
202 #define CPU_LE(code...) code
206 * Define a macro that constructs a 64-bit value by concatenating two
207 * 32-bit registers. Note that on big endian systems the order of the
208 * registers is swapped.
210 #ifndef CONFIG_CPU_BIG_ENDIAN
211 .macro regs_to_64, rd, lbits, hbits
213 .macro regs_to_64, rd, hbits, lbits
215 orr \rd, \lbits, \hbits, lsl #32
219 * Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where
220 * <symbol> is within the range +/- 4 GB of the PC.
223 * @dst: destination register (64 bit wide)
224 * @sym: name of the symbol
226 .macro adr_l, dst, sym
228 add \dst, \dst, :lo12:\sym
232 * @dst: destination register (32 or 64 bit wide)
233 * @sym: name of the symbol
234 * @tmp: optional 64-bit scratch register to be used if <dst> is a
235 * 32-bit wide register, in which case it cannot be used to hold
238 .macro ldr_l, dst, sym, tmp=
241 ldr \dst, [\dst, :lo12:\sym]
244 ldr \dst, [\tmp, :lo12:\sym]
249 * @src: source register (32 or 64 bit wide)
250 * @sym: name of the symbol
251 * @tmp: mandatory 64-bit scratch register to calculate the address
252 * while <src> needs to be preserved.
254 .macro str_l, src, sym, tmp
256 str \src, [\tmp, :lo12:\sym]
260 * @dst: Result of per_cpu(sym, smp_processor_id()) (can be SP)
261 * @sym: The name of the per-cpu variable
262 * @tmp: scratch register
264 .macro adr_this_cpu, dst, sym, tmp
266 add \dst, \tmp, #:lo12:\sym
267 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
276 * @dst: Result of READ_ONCE(per_cpu(sym, smp_processor_id()))
277 * @sym: The name of the per-cpu variable
278 * @tmp: scratch register
280 .macro ldr_this_cpu dst, sym, tmp
282 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
287 ldr \dst, [\dst, \tmp]
291 * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
293 .macro vma_vm_mm, rd, rn
294 ldr \rd, [\rn, #VMA_VM_MM]
298 * mmid - get context id from mm pointer (mm->context.id)
301 ldr \rd, [\rn, #MM_CONTEXT_ID]
304 * read_ctr - read CTR_EL0. If the system has mismatched register fields,
305 * provide the system wide safe value from arm64_ftr_reg_ctrel0.sys_val
308 alternative_if_not ARM64_MISMATCHED_CACHE_TYPE
309 mrs \reg, ctr_el0 // read CTR
312 ldr_l \reg, arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL
318 * raw_dcache_line_size - get the minimum D-cache line size on this CPU
319 * from the CTR register.
321 .macro raw_dcache_line_size, reg, tmp
322 mrs \tmp, ctr_el0 // read CTR
323 ubfm \tmp, \tmp, #16, #19 // cache line size encoding
324 mov \reg, #4 // bytes per word
325 lsl \reg, \reg, \tmp // actual cache line size
329 * dcache_line_size - get the safe D-cache line size across all CPUs
331 .macro dcache_line_size, reg, tmp
333 ubfm \tmp, \tmp, #16, #19 // cache line size encoding
334 mov \reg, #4 // bytes per word
335 lsl \reg, \reg, \tmp // actual cache line size
339 * raw_icache_line_size - get the minimum I-cache line size on this CPU
340 * from the CTR register.
342 .macro raw_icache_line_size, reg, tmp
343 mrs \tmp, ctr_el0 // read CTR
344 and \tmp, \tmp, #0xf // cache line size encoding
345 mov \reg, #4 // bytes per word
346 lsl \reg, \reg, \tmp // actual cache line size
350 * icache_line_size - get the safe I-cache line size across all CPUs
352 .macro icache_line_size, reg, tmp
354 and \tmp, \tmp, #0xf // cache line size encoding
355 mov \reg, #4 // bytes per word
356 lsl \reg, \reg, \tmp // actual cache line size
360 * tcr_set_t0sz - update TCR.T0SZ so that we can load the ID map
362 .macro tcr_set_t0sz, valreg, t0sz
363 bfi \valreg, \t0sz, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH
367 * tcr_compute_pa_size - set TCR.(I)PS to the highest supported
368 * ID_AA64MMFR0_EL1.PARange value
370 * tcr: register with the TCR_ELx value to be updated
371 * pos: IPS or PS bitfield position
372 * tmp{0,1}: temporary registers
374 .macro tcr_compute_pa_size, tcr, pos, tmp0, tmp1
375 mrs \tmp0, ID_AA64MMFR0_EL1
376 // Narrow PARange to fit the PS field in TCR_ELx
377 ubfx \tmp0, \tmp0, #ID_AA64MMFR0_PARANGE_SHIFT, #3
378 mov \tmp1, #ID_AA64MMFR0_PARANGE_MAX
380 csel \tmp0, \tmp1, \tmp0, hi
381 bfi \tcr, \tmp0, \pos, #3
385 * Macro to perform a data cache maintenance for the interval
386 * [kaddr, kaddr + size)
388 * op: operation passed to dc instruction
389 * domain: domain used in dsb instruciton
390 * kaddr: starting virtual address of the region
391 * size: size of the region
392 * Corrupts: kaddr, size, tmp1, tmp2
394 .macro __dcache_op_workaround_clean_cache, op, kaddr
395 alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE
402 .macro dcache_by_line_op op, domain, kaddr, size, tmp1, tmp2
403 dcache_line_size \tmp1, \tmp2
404 add \size, \kaddr, \size
406 bic \kaddr, \kaddr, \tmp2
409 __dcache_op_workaround_clean_cache \op, \kaddr
412 __dcache_op_workaround_clean_cache \op, \kaddr
415 sys 3, c7, c12, 1, \kaddr // dc cvap
421 add \kaddr, \kaddr, \tmp1
428 * Macro to perform an instruction cache maintenance for the interval
431 * start, end: virtual addresses describing the region
432 * label: A label to branch to on user fault.
433 * Corrupts: tmp1, tmp2
435 .macro invalidate_icache_by_line start, end, tmp1, tmp2, label
436 icache_line_size \tmp1, \tmp2
438 bic \tmp2, \start, \tmp2
440 USER(\label, ic ivau, \tmp2) // invalidate I line PoU
441 add \tmp2, \tmp2, \tmp1
449 * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present
451 .macro reset_pmuserenr_el0, tmpreg
452 mrs \tmpreg, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer
453 sbfx \tmpreg, \tmpreg, #8, #4
454 cmp \tmpreg, #1 // Skip if no PMU present
456 msr pmuserenr_el0, xzr // Disable PMU access from EL0
461 * copy_page - copy src to dest using temp registers t1-t8
463 .macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req
464 9998: ldp \t1, \t2, [\src]
465 ldp \t3, \t4, [\src, #16]
466 ldp \t5, \t6, [\src, #32]
467 ldp \t7, \t8, [\src, #48]
469 stnp \t1, \t2, [\dest]
470 stnp \t3, \t4, [\dest, #16]
471 stnp \t5, \t6, [\dest, #32]
472 stnp \t7, \t8, [\dest, #48]
473 add \dest, \dest, #64
474 tst \src, #(PAGE_SIZE - 1)
479 * Annotate a function as position independent, i.e., safe to be called before
480 * the kernel virtual mapping is activated.
482 #define ENDPIPROC(x) \
484 .type __pi_##x, %function; \
486 .size __pi_##x, . - x; \
490 * Annotate a function as being unsuitable for kprobes.
492 #ifdef CONFIG_KPROBES
493 #define NOKPROBE(x) \
494 .pushsection "_kprobe_blacklist", "aw"; \
502 #define EXPORT_SYMBOL_NOKASAN(name)
504 #define EXPORT_SYMBOL_NOKASAN(name) EXPORT_SYMBOL(name)
508 * Emit a 64-bit absolute little endian symbol reference in a way that
509 * ensures that it will be resolved at build time, even when building a
510 * PIE binary. This requires cooperation from the linker script, which
511 * must emit the lo32/hi32 halves individually.
519 * mov_q - move an immediate constant into a 64-bit register using
520 * between 2 and 4 movz/movk instructions (depending on the
521 * magnitude and sign of the operand)
523 .macro mov_q, reg, val
524 .if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff)
525 movz \reg, :abs_g1_s:\val
527 .if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff)
528 movz \reg, :abs_g2_s:\val
530 movz \reg, :abs_g3:\val
531 movk \reg, :abs_g2_nc:\val
533 movk \reg, :abs_g1_nc:\val
535 movk \reg, :abs_g0_nc:\val
539 * Return the current thread_info.
541 .macro get_thread_info, rd
546 * Offset ttbr1 to allow for 48-bit kernel VAs set with 52-bit PTRS_PER_PGD.
547 * orr is used as it can cover the immediate value (and is idempotent).
548 * In future this may be nop'ed out when dealing with 52-bit kernel VAs.
549 * ttbr: Value of ttbr to set, modified.
551 .macro offset_ttbr1, ttbr
552 #ifdef CONFIG_ARM64_USER_VA_BITS_52
553 orr \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET
558 * Perform the reverse of offset_ttbr1.
559 * bic is used as it can cover the immediate value and, in future, won't need
560 * to be nop'ed out when dealing with 52-bit kernel VAs.
562 .macro restore_ttbr1, ttbr
563 #ifdef CONFIG_ARM64_USER_VA_BITS_52
564 bic \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET
569 * Arrange a physical address in a TTBR register, taking care of 52-bit
572 * phys: physical address, preserved
573 * ttbr: returns the TTBR value
575 .macro phys_to_ttbr, ttbr, phys
576 #ifdef CONFIG_ARM64_PA_BITS_52
577 orr \ttbr, \phys, \phys, lsr #46
578 and \ttbr, \ttbr, #TTBR_BADDR_MASK_52
584 .macro phys_to_pte, pte, phys
585 #ifdef CONFIG_ARM64_PA_BITS_52
587 * We assume \phys is 64K aligned and this is guaranteed by only
588 * supporting this configuration with 64K pages.
590 orr \pte, \phys, \phys, lsr #36
591 and \pte, \pte, #PTE_ADDR_MASK
597 .macro pte_to_phys, phys, pte
598 #ifdef CONFIG_ARM64_PA_BITS_52
599 ubfiz \phys, \pte, #(48 - 16 - 12), #16
600 bfxil \phys, \pte, #16, #32
601 lsl \phys, \phys, #16
603 and \phys, \pte, #PTE_ADDR_MASK
608 * Errata workaround prior to disable MMU. Insert an ISB immediately prior
609 * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0.
611 .macro pre_disable_mmu_workaround
612 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1041
618 * frame_push - Push @regcount callee saved registers to the stack,
619 * starting at x19, as well as x29/x30, and set x29 to
620 * the new value of sp. Add @extra bytes of stack space
623 .macro frame_push, regcount:req, extra
624 __frame st, \regcount, \extra
628 * frame_pop - Pop the callee saved registers from the stack that were
629 * pushed in the most recent call to frame_push, as well
630 * as x29/x30 and any extra stack space that may have been
637 .macro __frame_regs, reg1, reg2, op, num
638 .if .Lframe_regcount == \num
639 \op\()r \reg1, [sp, #(\num + 1) * 8]
640 .elseif .Lframe_regcount > \num
641 \op\()p \reg1, \reg2, [sp, #(\num + 1) * 8]
645 .macro __frame, op, regcount, extra=0
647 .if (\regcount) < 0 || (\regcount) > 10
648 .error "regcount should be in the range [0 ... 10]"
650 .if ((\extra) % 16) != 0
651 .error "extra should be a multiple of 16 bytes"
653 .ifdef .Lframe_regcount
654 .if .Lframe_regcount != -1
655 .error "frame_push/frame_pop may not be nested"
658 .set .Lframe_regcount, \regcount
659 .set .Lframe_extra, \extra
660 .set .Lframe_local_offset, ((\regcount + 3) / 2) * 16
661 stp x29, x30, [sp, #-.Lframe_local_offset - .Lframe_extra]!
665 __frame_regs x19, x20, \op, 1
666 __frame_regs x21, x22, \op, 3
667 __frame_regs x23, x24, \op, 5
668 __frame_regs x25, x26, \op, 7
669 __frame_regs x27, x28, \op, 9
672 .if .Lframe_regcount == -1
673 .error "frame_push/frame_pop may not be nested"
675 ldp x29, x30, [sp], #.Lframe_local_offset + .Lframe_extra
676 .set .Lframe_regcount, -1
681 * Check whether to yield to another runnable task from kernel mode NEON code
682 * (which runs with preemption disabled).
684 * if_will_cond_yield_neon
685 * // pre-yield patchup code
687 * // post-yield patchup code
688 * endif_yield_neon <label>
690 * where <label> is optional, and marks the point where execution will resume
691 * after a yield has been performed. If omitted, execution resumes right after
692 * the endif_yield_neon invocation. Note that the entire sequence, including
693 * the provided patchup code, will be omitted from the image if CONFIG_PREEMPT
696 * As a convenience, in the case where no patchup code is required, the above
697 * sequence may be abbreviated to
699 * cond_yield_neon <label>
701 * Note that the patchup code does not support assembler directives that change
702 * the output section, any use of such directives is undefined.
704 * The yield itself consists of the following:
705 * - Check whether the preempt count is exactly 1, in which case disabling
706 * preemption once will make the task preemptible. If this is not the case,
707 * yielding is pointless.
708 * - Check whether TIF_NEED_RESCHED is set, and if so, disable and re-enable
709 * kernel mode NEON (which will trigger a reschedule), and branch to the
712 * This macro sequence may clobber all CPU state that is not guaranteed by the
713 * AAPCS to be preserved across an ordinary function call.
716 .macro cond_yield_neon, lbl
717 if_will_cond_yield_neon
719 endif_yield_neon \lbl
722 .macro if_will_cond_yield_neon
723 #ifdef CONFIG_PREEMPT
725 ldr x0, [x0, #TSK_TI_PREEMPT]
726 sub x0, x0, #PREEMPT_DISABLE_OFFSET
728 /* fall through to endif_yield_neon */
732 .section ".discard.cond_yield_neon", "ax"
736 .macro do_cond_yield_neon
741 .macro endif_yield_neon, lbl
751 #endif /* __ASM_ASSEMBLER_H */