2 * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S
4 * Copyright (C) 1996-2000 Russell King
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #error "Only include this from assembly code"
23 #ifndef __ASM_ASSEMBLER_H
24 #define __ASM_ASSEMBLER_H
26 #include <asm-generic/export.h>
28 #include <asm/asm-offsets.h>
29 #include <asm/cpufeature.h>
30 #include <asm/cputype.h>
31 #include <asm/debug-monitors.h>
33 #include <asm/pgtable-hwdef.h>
34 #include <asm/ptrace.h>
35 #include <asm/thread_info.h>
37 .macro save_and_disable_daif, flags
50 .macro restore_daif, flags:req
54 /* Only on aarch64 pstate, PSR_D_BIT is different for aarch32 */
55 .macro inherit_daif, pstate:req, tmp:req
56 and \tmp, \pstate, #(PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
60 /* IRQ is the lowest priority flag, unconditionally unmask the rest. */
62 msr daifclr, #(8 | 4 | 1)
66 * Save/restore interrupts.
68 .macro save_and_disable_irq, flags
73 .macro restore_irq, flags
81 .macro disable_step_tsk, flgs, tmp
82 tbz \flgs, #TIF_SINGLESTEP, 9990f
84 bic \tmp, \tmp, #DBG_MDSCR_SS
86 isb // Synchronise with enable_dbg
90 /* call with daif masked */
91 .macro enable_step_tsk, flgs, tmp
92 tbz \flgs, #TIF_SINGLESTEP, 9990f
94 orr \tmp, \tmp, #DBG_MDSCR_SS
100 * SMP data memory barrier
107 * RAS Error Synchronization barrier
114 * Value prediction barrier
121 * Speculation barrier
124 alternative_if_not ARM64_HAS_SB
134 * Sanitise a 64-bit bounded index wrt speculation, returning zero if out
137 .macro mask_nospec64, idx, limit, tmp
138 sub \tmp, \idx, \limit
140 and \idx, \idx, \tmp, asr #63
154 * Emit an entry into the exception table
156 .macro _asm_extable, from, to
157 .pushsection __ex_table, "a"
159 .long (\from - .), (\to - .)
163 #define USER(l, x...) \
165 _asm_extable 9999b, l
170 lr .req x30 // link register
181 * Select code when configured for BE.
183 #ifdef CONFIG_CPU_BIG_ENDIAN
184 #define CPU_BE(code...) code
186 #define CPU_BE(code...)
190 * Select code when configured for LE.
192 #ifdef CONFIG_CPU_BIG_ENDIAN
193 #define CPU_LE(code...)
195 #define CPU_LE(code...) code
199 * Define a macro that constructs a 64-bit value by concatenating two
200 * 32-bit registers. Note that on big endian systems the order of the
201 * registers is swapped.
203 #ifndef CONFIG_CPU_BIG_ENDIAN
204 .macro regs_to_64, rd, lbits, hbits
206 .macro regs_to_64, rd, hbits, lbits
208 orr \rd, \lbits, \hbits, lsl #32
212 * Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where
213 * <symbol> is within the range +/- 4 GB of the PC.
216 * @dst: destination register (64 bit wide)
217 * @sym: name of the symbol
219 .macro adr_l, dst, sym
221 add \dst, \dst, :lo12:\sym
225 * @dst: destination register (32 or 64 bit wide)
226 * @sym: name of the symbol
227 * @tmp: optional 64-bit scratch register to be used if <dst> is a
228 * 32-bit wide register, in which case it cannot be used to hold
231 .macro ldr_l, dst, sym, tmp=
234 ldr \dst, [\dst, :lo12:\sym]
237 ldr \dst, [\tmp, :lo12:\sym]
242 * @src: source register (32 or 64 bit wide)
243 * @sym: name of the symbol
244 * @tmp: mandatory 64-bit scratch register to calculate the address
245 * while <src> needs to be preserved.
247 .macro str_l, src, sym, tmp
249 str \src, [\tmp, :lo12:\sym]
253 * @dst: Result of per_cpu(sym, smp_processor_id()) (can be SP)
254 * @sym: The name of the per-cpu variable
255 * @tmp: scratch register
257 .macro adr_this_cpu, dst, sym, tmp
259 add \dst, \tmp, #:lo12:\sym
260 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
269 * @dst: Result of READ_ONCE(per_cpu(sym, smp_processor_id()))
270 * @sym: The name of the per-cpu variable
271 * @tmp: scratch register
273 .macro ldr_this_cpu dst, sym, tmp
275 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
280 ldr \dst, [\dst, \tmp]
284 * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
286 .macro vma_vm_mm, rd, rn
287 ldr \rd, [\rn, #VMA_VM_MM]
291 * mmid - get context id from mm pointer (mm->context.id)
294 ldr \rd, [\rn, #MM_CONTEXT_ID]
297 * read_ctr - read CTR_EL0. If the system has mismatched register fields,
298 * provide the system wide safe value from arm64_ftr_reg_ctrel0.sys_val
301 alternative_if_not ARM64_MISMATCHED_CACHE_TYPE
302 mrs \reg, ctr_el0 // read CTR
305 ldr_l \reg, arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL
311 * raw_dcache_line_size - get the minimum D-cache line size on this CPU
312 * from the CTR register.
314 .macro raw_dcache_line_size, reg, tmp
315 mrs \tmp, ctr_el0 // read CTR
316 ubfm \tmp, \tmp, #16, #19 // cache line size encoding
317 mov \reg, #4 // bytes per word
318 lsl \reg, \reg, \tmp // actual cache line size
322 * dcache_line_size - get the safe D-cache line size across all CPUs
324 .macro dcache_line_size, reg, tmp
326 ubfm \tmp, \tmp, #16, #19 // cache line size encoding
327 mov \reg, #4 // bytes per word
328 lsl \reg, \reg, \tmp // actual cache line size
332 * raw_icache_line_size - get the minimum I-cache line size on this CPU
333 * from the CTR register.
335 .macro raw_icache_line_size, reg, tmp
336 mrs \tmp, ctr_el0 // read CTR
337 and \tmp, \tmp, #0xf // cache line size encoding
338 mov \reg, #4 // bytes per word
339 lsl \reg, \reg, \tmp // actual cache line size
343 * icache_line_size - get the safe I-cache line size across all CPUs
345 .macro icache_line_size, reg, tmp
347 and \tmp, \tmp, #0xf // cache line size encoding
348 mov \reg, #4 // bytes per word
349 lsl \reg, \reg, \tmp // actual cache line size
353 * tcr_set_t0sz - update TCR.T0SZ so that we can load the ID map
355 .macro tcr_set_t0sz, valreg, t0sz
356 bfi \valreg, \t0sz, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH
360 * tcr_compute_pa_size - set TCR.(I)PS to the highest supported
361 * ID_AA64MMFR0_EL1.PARange value
363 * tcr: register with the TCR_ELx value to be updated
364 * pos: IPS or PS bitfield position
365 * tmp{0,1}: temporary registers
367 .macro tcr_compute_pa_size, tcr, pos, tmp0, tmp1
368 mrs \tmp0, ID_AA64MMFR0_EL1
369 // Narrow PARange to fit the PS field in TCR_ELx
370 ubfx \tmp0, \tmp0, #ID_AA64MMFR0_PARANGE_SHIFT, #3
371 mov \tmp1, #ID_AA64MMFR0_PARANGE_MAX
373 csel \tmp0, \tmp1, \tmp0, hi
374 bfi \tcr, \tmp0, \pos, #3
378 * Macro to perform a data cache maintenance for the interval
379 * [kaddr, kaddr + size)
381 * op: operation passed to dc instruction
382 * domain: domain used in dsb instruciton
383 * kaddr: starting virtual address of the region
384 * size: size of the region
385 * Corrupts: kaddr, size, tmp1, tmp2
387 .macro __dcache_op_workaround_clean_cache, op, kaddr
388 alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE
395 .macro dcache_by_line_op op, domain, kaddr, size, tmp1, tmp2
396 dcache_line_size \tmp1, \tmp2
397 add \size, \kaddr, \size
399 bic \kaddr, \kaddr, \tmp2
402 __dcache_op_workaround_clean_cache \op, \kaddr
405 __dcache_op_workaround_clean_cache \op, \kaddr
408 sys 3, c7, c12, 1, \kaddr // dc cvap
411 sys 3, c7, c13, 1, \kaddr // dc cvadp
418 add \kaddr, \kaddr, \tmp1
425 * Macro to perform an instruction cache maintenance for the interval
428 * start, end: virtual addresses describing the region
429 * label: A label to branch to on user fault.
430 * Corrupts: tmp1, tmp2
432 .macro invalidate_icache_by_line start, end, tmp1, tmp2, label
433 icache_line_size \tmp1, \tmp2
435 bic \tmp2, \start, \tmp2
437 USER(\label, ic ivau, \tmp2) // invalidate I line PoU
438 add \tmp2, \tmp2, \tmp1
446 * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present
448 .macro reset_pmuserenr_el0, tmpreg
449 mrs \tmpreg, id_aa64dfr0_el1
450 sbfx \tmpreg, \tmpreg, #ID_AA64DFR0_PMUVER_SHIFT, #4
451 cmp \tmpreg, #1 // Skip if no PMU present
453 msr pmuserenr_el0, xzr // Disable PMU access from EL0
458 * copy_page - copy src to dest using temp registers t1-t8
460 .macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req
461 9998: ldp \t1, \t2, [\src]
462 ldp \t3, \t4, [\src, #16]
463 ldp \t5, \t6, [\src, #32]
464 ldp \t7, \t8, [\src, #48]
466 stnp \t1, \t2, [\dest]
467 stnp \t3, \t4, [\dest, #16]
468 stnp \t5, \t6, [\dest, #32]
469 stnp \t7, \t8, [\dest, #48]
470 add \dest, \dest, #64
471 tst \src, #(PAGE_SIZE - 1)
476 * Annotate a function as position independent, i.e., safe to be called before
477 * the kernel virtual mapping is activated.
479 #define ENDPIPROC(x) \
481 .type __pi_##x, %function; \
483 .size __pi_##x, . - x; \
487 * Annotate a function as being unsuitable for kprobes.
489 #ifdef CONFIG_KPROBES
490 #define NOKPROBE(x) \
491 .pushsection "_kprobe_blacklist", "aw"; \
499 #define EXPORT_SYMBOL_NOKASAN(name)
501 #define EXPORT_SYMBOL_NOKASAN(name) EXPORT_SYMBOL(name)
505 * Emit a 64-bit absolute little endian symbol reference in a way that
506 * ensures that it will be resolved at build time, even when building a
507 * PIE binary. This requires cooperation from the linker script, which
508 * must emit the lo32/hi32 halves individually.
516 * mov_q - move an immediate constant into a 64-bit register using
517 * between 2 and 4 movz/movk instructions (depending on the
518 * magnitude and sign of the operand)
520 .macro mov_q, reg, val
521 .if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff)
522 movz \reg, :abs_g1_s:\val
524 .if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff)
525 movz \reg, :abs_g2_s:\val
527 movz \reg, :abs_g3:\val
528 movk \reg, :abs_g2_nc:\val
530 movk \reg, :abs_g1_nc:\val
532 movk \reg, :abs_g0_nc:\val
536 * Return the current task_struct.
538 .macro get_current_task, rd
543 * Offset ttbr1 to allow for 48-bit kernel VAs set with 52-bit PTRS_PER_PGD.
544 * orr is used as it can cover the immediate value (and is idempotent).
545 * In future this may be nop'ed out when dealing with 52-bit kernel VAs.
546 * ttbr: Value of ttbr to set, modified.
548 .macro offset_ttbr1, ttbr
549 #ifdef CONFIG_ARM64_USER_VA_BITS_52
550 orr \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET
555 * Perform the reverse of offset_ttbr1.
556 * bic is used as it can cover the immediate value and, in future, won't need
557 * to be nop'ed out when dealing with 52-bit kernel VAs.
559 .macro restore_ttbr1, ttbr
560 #ifdef CONFIG_ARM64_USER_VA_BITS_52
561 bic \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET
566 * Arrange a physical address in a TTBR register, taking care of 52-bit
569 * phys: physical address, preserved
570 * ttbr: returns the TTBR value
572 .macro phys_to_ttbr, ttbr, phys
573 #ifdef CONFIG_ARM64_PA_BITS_52
574 orr \ttbr, \phys, \phys, lsr #46
575 and \ttbr, \ttbr, #TTBR_BADDR_MASK_52
581 .macro phys_to_pte, pte, phys
582 #ifdef CONFIG_ARM64_PA_BITS_52
584 * We assume \phys is 64K aligned and this is guaranteed by only
585 * supporting this configuration with 64K pages.
587 orr \pte, \phys, \phys, lsr #36
588 and \pte, \pte, #PTE_ADDR_MASK
594 .macro pte_to_phys, phys, pte
595 #ifdef CONFIG_ARM64_PA_BITS_52
596 ubfiz \phys, \pte, #(48 - 16 - 12), #16
597 bfxil \phys, \pte, #16, #32
598 lsl \phys, \phys, #16
600 and \phys, \pte, #PTE_ADDR_MASK
605 * tcr_clear_errata_bits - Clear TCR bits that trigger an errata on this CPU.
607 .macro tcr_clear_errata_bits, tcr, tmp1, tmp2
608 #ifdef CONFIG_FUJITSU_ERRATUM_010001
611 mov_q \tmp2, MIDR_FUJITSU_ERRATUM_010001_MASK
612 and \tmp1, \tmp1, \tmp2
613 mov_q \tmp2, MIDR_FUJITSU_ERRATUM_010001
617 mov_q \tmp2, TCR_CLEAR_FUJITSU_ERRATUM_010001
618 bic \tcr, \tcr, \tmp2
620 #endif /* CONFIG_FUJITSU_ERRATUM_010001 */
624 * Errata workaround prior to disable MMU. Insert an ISB immediately prior
625 * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0.
627 .macro pre_disable_mmu_workaround
628 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1041
634 * frame_push - Push @regcount callee saved registers to the stack,
635 * starting at x19, as well as x29/x30, and set x29 to
636 * the new value of sp. Add @extra bytes of stack space
639 .macro frame_push, regcount:req, extra
640 __frame st, \regcount, \extra
644 * frame_pop - Pop the callee saved registers from the stack that were
645 * pushed in the most recent call to frame_push, as well
646 * as x29/x30 and any extra stack space that may have been
653 .macro __frame_regs, reg1, reg2, op, num
654 .if .Lframe_regcount == \num
655 \op\()r \reg1, [sp, #(\num + 1) * 8]
656 .elseif .Lframe_regcount > \num
657 \op\()p \reg1, \reg2, [sp, #(\num + 1) * 8]
661 .macro __frame, op, regcount, extra=0
663 .if (\regcount) < 0 || (\regcount) > 10
664 .error "regcount should be in the range [0 ... 10]"
666 .if ((\extra) % 16) != 0
667 .error "extra should be a multiple of 16 bytes"
669 .ifdef .Lframe_regcount
670 .if .Lframe_regcount != -1
671 .error "frame_push/frame_pop may not be nested"
674 .set .Lframe_regcount, \regcount
675 .set .Lframe_extra, \extra
676 .set .Lframe_local_offset, ((\regcount + 3) / 2) * 16
677 stp x29, x30, [sp, #-.Lframe_local_offset - .Lframe_extra]!
681 __frame_regs x19, x20, \op, 1
682 __frame_regs x21, x22, \op, 3
683 __frame_regs x23, x24, \op, 5
684 __frame_regs x25, x26, \op, 7
685 __frame_regs x27, x28, \op, 9
688 .if .Lframe_regcount == -1
689 .error "frame_push/frame_pop may not be nested"
691 ldp x29, x30, [sp], #.Lframe_local_offset + .Lframe_extra
692 .set .Lframe_regcount, -1
697 * Check whether to yield to another runnable task from kernel mode NEON code
698 * (which runs with preemption disabled).
700 * if_will_cond_yield_neon
701 * // pre-yield patchup code
703 * // post-yield patchup code
704 * endif_yield_neon <label>
706 * where <label> is optional, and marks the point where execution will resume
707 * after a yield has been performed. If omitted, execution resumes right after
708 * the endif_yield_neon invocation. Note that the entire sequence, including
709 * the provided patchup code, will be omitted from the image if CONFIG_PREEMPT
712 * As a convenience, in the case where no patchup code is required, the above
713 * sequence may be abbreviated to
715 * cond_yield_neon <label>
717 * Note that the patchup code does not support assembler directives that change
718 * the output section, any use of such directives is undefined.
720 * The yield itself consists of the following:
721 * - Check whether the preempt count is exactly 1, in which case disabling
722 * preemption once will make the task preemptible. If this is not the case,
723 * yielding is pointless.
724 * - Check whether TIF_NEED_RESCHED is set, and if so, disable and re-enable
725 * kernel mode NEON (which will trigger a reschedule), and branch to the
728 * This macro sequence may clobber all CPU state that is not guaranteed by the
729 * AAPCS to be preserved across an ordinary function call.
732 .macro cond_yield_neon, lbl
733 if_will_cond_yield_neon
735 endif_yield_neon \lbl
738 .macro if_will_cond_yield_neon
739 #ifdef CONFIG_PREEMPT
741 ldr x0, [x0, #TSK_TI_PREEMPT]
742 sub x0, x0, #PREEMPT_DISABLE_OFFSET
744 /* fall through to endif_yield_neon */
748 .section ".discard.cond_yield_neon", "ax"
752 .macro do_cond_yield_neon
757 .macro endif_yield_neon, lbl
767 #endif /* __ASM_ASSEMBLER_H */