arch/arm64/boot/dts/xilinx/zynqmp.dtsi

   1 /*
   2  * dts file for Xilinx ZynqMP
   3  *
   4  * (C) Copyright 2014 - 2015, Xilinx, Inc.
   5  *
   6  * Michal Simek <michal.simek@xilinx.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  */
  13
  14 / {
  15         compatible = "xlnx,zynqmp";
  16         #address-cells = <2>;
  17         #size-cells = <1>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 cpu@0 {
  24                         compatible = "arm,cortex-a53", "arm,armv8";
  25                         device_type = "cpu";
  26                         enable-method = "psci";
  27                         reg = <0x0>;
  28                 };
  29
  30                 cpu@1 {
  31                         compatible = "arm,cortex-a53", "arm,armv8";
  32                         device_type = "cpu";
  33                         enable-method = "psci";
  34                         reg = <0x1>;
  35                 };
  36
  37                 cpu@2 {
  38                         compatible = "arm,cortex-a53", "arm,armv8";
  39                         device_type = "cpu";
  40                         enable-method = "psci";
  41                         reg = <0x2>;
  42                 };
  43
  44                 cpu@3 {
  45                         compatible = "arm,cortex-a53", "arm,armv8";
  46                         device_type = "cpu";
  47                         enable-method = "psci";
  48                         reg = <0x3>;
  49                 };
  50         };
  51
  52         pmu {
  53                 compatible = "arm,armv8-pmuv3";
  54                 interrupts = <0 143 4>,
  55                              <0 144 4>,
  56                              <0 145 4>,
  57                              <0 146 4>;
  58         };
  59
  60         psci {
  61                 compatible = "arm,psci-0.2";
  62                 method = "smc";
  63         };
  64
  65         timer {
  66                 compatible = "arm,armv8-timer";
  67                 interrupt-parent = <&gic>;
  68                 interrupts = <1 13 0xf01>,
  69                              <1 14 0xf01>,
  70                              <1 11 0xf01>,
  71                              <1 10 0xf01>;
  72         };
  73
  74         amba_apu {
  75                 compatible = "simple-bus";
  76                 #address-cells = <2>;
  77                 #size-cells = <1>;
  78                 ranges;
  79
  80                 gic: interrupt-controller@f9010000 {
  81                         compatible = "arm,gic-400", "arm,cortex-a15-gic";
  82                         #interrupt-cells = <3>;
  83                         reg = <0x0 0xf9010000 0x10000>,
  84                               <0x0 0xf902f000 0x2000>,
  85                               <0x0 0xf9040000 0x20000>,
  86                               <0x0 0xf906f000 0x2000>;
  87                         interrupt-controller;
  88                         interrupt-parent = <&gic>;
  89                         interrupts = <1 9 0xf04>;
  90                 };
  91         };
  92
  93         amba {
  94                 compatible = "simple-bus";
  95                 #address-cells = <2>;
  96                 #size-cells = <1>;
  97                 ranges;
  98
  99                 can0: can@ff060000 {
 100                         compatible = "xlnx,zynq-can-1.0";
 101                         status = "disabled";
 102                         clocks = <&misc_clk &misc_clk>;
 103                         clock-names = "can_clk", "pclk";
 104                         reg = <0x0 0xff060000 0x1000>;
 105                         interrupts = <0 23 4>;
 106                         interrupt-parent = <&gic>;
 107                         tx-fifo-depth = <0x40>;
 108                         rx-fifo-depth = <0x40>;
 109                 };
 110
 111                 can1: can@ff070000 {
 112                         compatible = "xlnx,zynq-can-1.0";
 113                         status = "disabled";
 114                         clocks = <&misc_clk &misc_clk>;
 115                         clock-names = "can_clk", "pclk";
 116                         reg = <0x0 0xff070000 0x1000>;
 117                         interrupts = <0 24 4>;
 118                         interrupt-parent = <&gic>;
 119                         tx-fifo-depth = <0x40>;
 120                         rx-fifo-depth = <0x40>;
 121                 };
 122
 123                 misc_clk: misc_clk {
 124                         compatible = "fixed-clock";
 125                         #clock-cells = <0>;
 126                         clock-frequency = <25000000>;
 127                 };
 128
 129                 ttc0: timer@ff110000 {
 130                         compatible = "cdns,ttc";
 131                         status = "disabled";
 132                         interrupt-parent = <&gic>;
 133                         interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
 134                         reg = <0x0 0xff110000 0x1000>;
 135                         clocks = <&misc_clk>;
 136                         timer-width = <32>;
 137                 };
 138
 139                 ttc1: timer@ff120000 {
 140                         compatible = "cdns,ttc";
 141                         status = "disabled";
 142                         interrupt-parent = <&gic>;
 143                         interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
 144                         reg = <0x0 0xff120000 0x1000>;
 145                         clocks = <&misc_clk>;
 146                         timer-width = <32>;
 147                 };
 148
 149                 ttc2: timer@ff130000 {
 150                         compatible = "cdns,ttc";
 151                         status = "disabled";
 152                         interrupt-parent = <&gic>;
 153                         interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
 154                         reg = <0x0 0xff130000 0x1000>;
 155                         clocks = <&misc_clk>;
 156                         timer-width = <32>;
 157                 };
 158
 159                 ttc3: timer@ff140000 {
 160                         compatible = "cdns,ttc";
 161                         status = "disabled";
 162                         interrupt-parent = <&gic>;
 163                         interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
 164                         reg = <0x0 0xff140000 0x1000>;
 165                         clocks = <&misc_clk>;
 166                         timer-width = <32>;
 167                 };
 168
 169                 uart0: serial@ff000000 {
 170                         compatible = "cdns,uart-r1p8";
 171                         status = "disabled";
 172                         interrupt-parent = <&gic>;
 173                         interrupts = <0 21 4>;
 174                         reg = <0x0 0xff000000 0x1000>;
 175                         clock-names = "uart_clk", "pclk";
 176                         clocks = <&misc_clk &misc_clk>;
 177                 };
 178
 179                 uart1: serial@ff010000 {
 180                         compatible = "cdns,uart-r1p8";
 181                         status = "disabled";
 182                         interrupt-parent = <&gic>;
 183                         interrupts = <0 22 4>;
 184                         reg = <0x0 0xff010000 0x1000>;
 185                         clock-names = "uart_clk", "pclk";
 186                         clocks = <&misc_clk &misc_clk>;
 187                 };
 188
 189                 gpio: gpio@ff0a0000 {
 190                         compatible = "xlnx,zynqmp-gpio-1.0";
 191                         status = "disabled";
 192                         #gpio-cells = <0x2>;
 193                         clocks = <&misc_clk>;
 194                         interrupt-parent = <&gic>;
 195                         interrupts = <0 16 4>;
 196                         reg = <0x0 0xff0a0000 0x1000>;
 197                 };
 198
 199                 gem0: ethernet@ff0b0000 {
 200                         compatible = "cdns,gem";
 201                         status = "disabled";
 202                         interrupt-parent = <&gic>;
 203                         interrupts = <0 57 4>, <0 57 4>;
 204                         reg = <0x0 0xff0b0000 0x1000>;
 205                         clock-names = "pclk", "hclk", "tx_clk";
 206                         clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
 207                         #address-cells = <1>;
 208                         #size-cells = <0>;
 209                 };
 210
 211                 gem1: ethernet@ff0c0000 {
 212                         compatible = "cdns,gem";
 213                         status = "disabled";
 214                         interrupt-parent = <&gic>;
 215                         interrupts = <0 59 4>, <0 59 4>;
 216                         reg = <0x0 0xff0c0000 0x1000>;
 217                         clock-names = "pclk", "hclk", "tx_clk";
 218                         clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
 219                         #address-cells = <1>;
 220                         #size-cells = <0>;
 221                 };
 222
 223                 gem2: ethernet@ff0d0000 {
 224                         compatible = "cdns,gem";
 225                         status = "disabled";
 226                         interrupt-parent = <&gic>;
 227                         interrupts = <0 61 4>, <0 61 4>;
 228                         reg = <0x0 0xff0d0000 0x1000>;
 229                         clock-names = "pclk", "hclk", "tx_clk";
 230                         clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
 231                         #address-cells = <1>;
 232                         #size-cells = <0>;
 233                 };
 234
 235                 gem3: ethernet@ff0e0000 {
 236                         compatible = "cdns,gem";
 237                         status = "disabled";
 238                         interrupt-parent = <&gic>;
 239                         interrupts = <0 63 4>, <0 63 4>;
 240                         reg = <0x0 0xff0e0000 0x1000>;
 241                         clock-names = "pclk", "hclk", "tx_clk";
 242                         clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
 243                         #address-cells = <1>;
 244                         #size-cells = <0>;
 245                 };
 246
 247                 spi0: spi@ff040000 {
 248                         compatible = "cdns,spi-r1p6";
 249                         status = "disabled";
 250                         interrupt-parent = <&gic>;
 251                         interrupts = <0 19 4>;
 252                         reg = <0x0 0xff040000 0x1000>;
 253                         clock-names = "ref_clk", "pclk";
 254                         clocks = <&misc_clk &misc_clk>;
 255                         #address-cells = <1>;
 256                         #size-cells = <0>;
 257                 };
 258
 259                 spi1: spi@ff050000 {
 260                         compatible = "cdns,spi-r1p6";
 261                         status = "disabled";
 262                         interrupt-parent = <&gic>;
 263                         interrupts = <0 20 4>;
 264                         reg = <0x0 0xff050000 0x1000>;
 265                         clock-names = "ref_clk", "pclk";
 266                         clocks = <&misc_clk &misc_clk>;
 267                         #address-cells = <1>;
 268                         #size-cells = <0>;
 269                 };
 270
 271                 i2c_clk: i2c_clk {
 272                         compatible = "fixed-clock";
 273                         #clock-cells = <0x0>;
 274                         clock-frequency = <111111111>;
 275                 };
 276
 277                 i2c0: i2c@ff020000 {
 278                         compatible = "cdns,i2c-r1p10";
 279                         status = "disabled";
 280                         interrupt-parent = <&gic>;
 281                         interrupts = <0 17 4>;
 282                         reg = <0x0 0xff020000 0x1000>;
 283                         clocks = <&i2c_clk>;
 284                         #address-cells = <1>;
 285                         #size-cells = <0>;
 286                 };
 287
 288                 i2c1: i2c@ff030000 {
 289                         compatible = "cdns,i2c-r1p10";
 290                         status = "disabled";
 291                         interrupt-parent = <&gic>;
 292                         interrupts = <0 18 4>;
 293                         reg = <0x0 0xff030000 0x1000>;
 294                         clocks = <&i2c_clk>;
 295                         #address-cells = <1>;
 296                         #size-cells = <0>;
 297                 };
 298
 299                 sata_clk: sata_clk {
 300                         compatible = "fixed-clock";
 301                         #clock-cells = <0>;
 302                         clock-frequency = <75000000>;
 303                 };
 304
 305                 sata: ahci@fd0c0000 {
 306                         compatible = "ceva,ahci-1v84";
 307                         status = "disabled";
 308                         reg = <0x0 0xfd0c0000 0x2000>;
 309                         interrupt-parent = <&gic>;
 310                         interrupts = <0 133 4>;
 311                         clocks = <&sata_clk>;
 312                 };
 313
 314                 sdhci0: sdhci@ff160000 {
 315                         compatible = "arasan,sdhci-8.9a";
 316                         status = "disabled";
 317                         interrupt-parent = <&gic>;
 318                         interrupts = <0 48 4>;
 319                         reg = <0x0 0xff160000 0x1000>;
 320                         clock-names = "clk_xin", "clk_ahb";
 321                         clocks = <&misc_clk>, <&misc_clk>;
 322                 };
 323
 324                 sdhci1: sdhci@ff170000 {
 325                         compatible = "arasan,sdhci-8.9a";
 326                         status = "disabled";
 327                         interrupt-parent = <&gic>;
 328                         interrupts = <0 49 4>;
 329                         reg = <0x0 0xff170000 0x1000>;
 330                         clock-names = "clk_xin", "clk_ahb";
 331                         clocks = <&misc_clk>, <&misc_clk>;
 332                 };
 333
 334                 watchdog0: watchdog@fd4d0000 {
 335                         compatible = "cdns,wdt-r1p2";
 336                         status = "disabled";
 337                         clocks= <&misc_clk>;
 338                         interrupt-parent = <&gic>;
 339                         interrupts = <0 52 1>;
 340                         reg = <0x0 0xfd4d0000 0x1000>;
 341                         timeout-sec = <10>;
 342                 };
 343         };
 344 };