arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU104
   4  *
   5  * (C) Copyright 2017 - 2019, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/phy/phy.h>
  16
  17 / {
  18         model = "ZynqMP ZCU104 RevA";
  19         compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
  20
  21         aliases {
  22                 ethernet0 = &gem3;
  23                 i2c0 = &i2c1;
  24                 mmc0 = &sdhci1;
  25                 rtc0 = &rtc;
  26                 serial0 = &uart0;
  27                 serial1 = &uart1;
  28                 serial2 = &dcc;
  29         };
  30
  31         chosen {
  32                 bootargs = "earlycon";
  33                 stdout-path = "serial0:115200n8";
  34         };
  35
  36         memory@0 {
  37                 device_type = "memory";
  38                 reg = <0x0 0x0 0x0 0x80000000>;
  39         };
  40
  41         clock_8t49n287_5: clk125 {
  42                 compatible = "fixed-clock";
  43                 #clock-cells = <0>;
  44                 clock-frequency = <125000000>;
  45         };
  46
  47         clock_8t49n287_2: clk26 {
  48                 compatible = "fixed-clock";
  49                 #clock-cells = <0>;
  50                 clock-frequency = <26000000>;
  51         };
  52
  53         clock_8t49n287_3: clk27 {
  54                 compatible = "fixed-clock";
  55                 #clock-cells = <0>;
  56                 clock-frequency = <27000000>;
  57         };
  58 };
  59
  60 &can1 {
  61         status = "okay";
  62 };
  63
  64 &dcc {
  65         status = "okay";
  66 };
  67
  68 &gem3 {
  69         status = "okay";
  70         phy-handle = <&phy0>;
  71         phy-mode = "rgmii-id";
  72         phy0: ethernet-phy@c {
  73                 reg = <0xc>;
  74                 ti,rx-internal-delay = <0x8>;
  75                 ti,tx-internal-delay = <0xa>;
  76                 ti,fifo-depth = <0x1>;
  77                 ti,dp83867-rxctrl-strap-quirk;
  78         };
  79 };
  80
  81 &gpio {
  82         status = "okay";
  83 };
  84
  85 &i2c1 {
  86         status = "okay";
  87         clock-frequency = <400000>;
  88
  89         /* Another connection to this bus via PL i2c via PCA9306 - u45 */
  90         i2c-mux@74 { /* u34 */
  91                 compatible = "nxp,pca9548";
  92                 #address-cells = <1>;
  93                 #size-cells = <0>;
  94                 reg = <0x74>;
  95                 i2c@0 {
  96                         #address-cells = <1>;
  97                         #size-cells = <0>;
  98                         reg = <0>;
  99                         /*
 100                          * IIC_EEPROM 1kB memory which uses 256B blocks
 101                          * where every block has different address.
 102                          *    0 - 256B address 0x54
 103                          * 256B - 512B address 0x55
 104                          * 512B - 768B address 0x56
 105                          * 768B - 1024B address 0x57
 106                          */
 107                         eeprom@54 { /* u23 */
 108                                 compatible = "atmel,24c08";
 109                                 reg = <0x54>;
 110                                 #address-cells = <1>;
 111                                 #size-cells = <1>;
 112                         };
 113                 };
 114
 115                 i2c@1 {
 116                         #address-cells = <1>;
 117                         #size-cells = <0>;
 118                         reg = <1>;
 119                         clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
 120                                 reg = <0x6c>;
 121                         };
 122                 };
 123
 124                 i2c@2 {
 125                         #address-cells = <1>;
 126                         #size-cells = <0>;
 127                         reg = <2>;
 128                         irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
 129                                 reg = <0x43>;
 130                         };
 131                         irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
 132                                 reg = <0x4d>;
 133                         };
 134                 };
 135
 136                 i2c@4 {
 137                         #address-cells = <1>;
 138                         #size-cells = <0>;
 139                         reg = <4>;
 140                         tca6416_u97: gpio@20 {
 141                                 compatible = "ti,tca6416";
 142                                 reg = <0x20>;
 143                                 gpio-controller;
 144                                 #gpio-cells = <2>;
 145                                 /*
 146                                  * IRQ not connected
 147                                  * Lines:
 148                                  * 0 - IRPS5401_ALERT_B
 149                                  * 1 - HDMI_8T49N241_INT_ALM
 150                                  * 2 - MAX6643_OT_B
 151                                  * 3 - MAX6643_FANFAIL_B
 152                                  * 5 - IIC_MUX_RESET_B
 153                                  * 6 - GEM3_EXP_RESET_B
 154                                  * 7 - FMC_LPC_PRSNT_M2C_B
 155                                  * 4, 10 - 17 - not connected
 156                                  */
 157                         };
 158                 };
 159
 160                 i2c@5 {
 161                         #address-cells = <1>;
 162                         #size-cells = <0>;
 163                         reg = <5>;
 164                 };
 165
 166                 i2c@7 {
 167                         #address-cells = <1>;
 168                         #size-cells = <0>;
 169                         reg = <7>;
 170                 };
 171
 172                 /* 3, 6 not connected */
 173         };
 174 };
 175
 176 &rtc {
 177         status = "okay";
 178 };
 179
 180 &psgtr {
 181         status = "okay";
 182         /* nc, sata, usb3, dp */
 183         clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
 184         clock-names = "ref1", "ref2", "ref3";
 185 };
 186
 187 &sata {
 188         status = "okay";
 189         /* SATA OOB timing settings */
 190         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 191         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 192         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 193         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 194         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 195         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 196         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 197         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 198         phy-names = "sata-phy";
 199         phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
 200 };
 201
 202 /* SD1 with level shifter */
 203 &sdhci1 {
 204         status = "okay";
 205         no-1-8-v;
 206         xlnx,mio-bank = <1>;
 207         disable-wp;
 208 };
 209
 210 &uart0 {
 211         status = "okay";
 212 };
 213
 214 &uart1 {
 215         status = "okay";
 216 };
 217
 218 /* ULPI SMSC USB3320 */
 219 &usb0 {
 220         status = "okay";
 221         dr_mode = "host";
 222 };
 223
 224 &watchdog0 {
 225         status = "okay";
 226 };
 227
 228 &zynqmp_dpdma {
 229         status = "okay";
 230 };
 231
 232 &zynqmp_dpsub {
 233         status = "okay";
 234         phy-names = "dp-phy0", "dp-phy1";
 235         phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
 236                <&psgtr 0 PHY_TYPE_DP 1 3>;
 237 };