arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP zc1751-xm015-dc1
   4  *
   5  * (C) Copyright 2015 - 2019, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/gpio/gpio.h>
  15
  16 / {
  17         model = "ZynqMP zc1751-xm015-dc1 RevA";
  18         compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
  19
  20         aliases {
  21                 ethernet0 = &gem3;
  22                 i2c0 = &i2c1;
  23                 mmc0 = &sdhci0;
  24                 mmc1 = &sdhci1;
  25                 rtc0 = &rtc;
  26                 serial0 = &uart0;
  27         };
  28
  29         chosen {
  30                 bootargs = "earlycon";
  31                 stdout-path = "serial0:115200n8";
  32         };
  33
  34         memory@0 {
  35                 device_type = "memory";
  36                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  37         };
  38 };
  39
  40 &fpd_dma_chan1 {
  41         status = "okay";
  42 };
  43
  44 &fpd_dma_chan2 {
  45         status = "okay";
  46 };
  47
  48 &fpd_dma_chan3 {
  49         status = "okay";
  50 };
  51
  52 &fpd_dma_chan4 {
  53         status = "okay";
  54 };
  55
  56 &fpd_dma_chan5 {
  57         status = "okay";
  58 };
  59
  60 &fpd_dma_chan6 {
  61         status = "okay";
  62 };
  63
  64 &fpd_dma_chan7 {
  65         status = "okay";
  66 };
  67
  68 &fpd_dma_chan8 {
  69         status = "okay";
  70 };
  71
  72 &gem3 {
  73         status = "okay";
  74         phy-handle = <&phy0>;
  75         phy-mode = "rgmii-id";
  76         phy0: ethernet-phy@0 {
  77                 reg = <0>;
  78         };
  79 };
  80
  81 &gpio {
  82         status = "okay";
  83 };
  84
  85
  86 &i2c1 {
  87         status = "okay";
  88         clock-frequency = <400000>;
  89
  90         eeprom: eeprom@55 {
  91                 compatible = "atmel,24c64"; /* 24AA64 */
  92                 reg = <0x55>;
  93         };
  94 };
  95
  96 &rtc {
  97         status = "okay";
  98 };
  99
 100 &sata {
 101         status = "okay";
 102         /* SATA phy OOB timing settings */
 103         ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
 104         ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
 105         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 106         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 107         ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
 108         ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
 109         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 110         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 111 };
 112
 113 /* eMMC */
 114 &sdhci0 {
 115         status = "okay";
 116         bus-width = <8>;
 117 };
 118
 119 /* SD1 with level shifter */
 120 &sdhci1 {
 121         status = "okay";
 122 };
 123
 124 &uart0 {
 125         status = "okay";
 126 };
 127
 128 /* ULPI SMSC USB3320 */
 129 &usb0 {
 130         status = "okay";
 131         dr_mode = "host";
 132 };