1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2019, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
17 model = "ZynqMP zc1751-xm015-dc1 RevA";
18 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
30 bootargs = "earlycon";
31 stdout-path = "serial0:115200n8";
35 device_type = "memory";
36 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
75 phy-mode = "rgmii-id";
76 phy0: ethernet-phy@0 {
88 clock-frequency = <400000>;
91 compatible = "atmel,24c64"; /* 24AA64 */
102 /* SATA phy OOB timing settings */
103 ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
104 ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
105 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
106 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
107 ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
108 ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
109 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
110 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
119 /* SD1 with level shifter */
128 /* ULPI SMSC USB3320 */