1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Source for the TMPV7708
5 * (C) Copyright 2018 - 2020, Toshiba Corporation.
6 * (C) Copyright 2020, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 /memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */
16 compatible = "toshiba,tmpv7708";
57 compatible = "arm,cortex-a53";
59 enable-method = "spin-table";
60 cpu-release-addr = <0x0 0x81100000>;
65 compatible = "arm,cortex-a53";
67 enable-method = "spin-table";
68 cpu-release-addr = <0x0 0x81100000>;
73 compatible = "arm,cortex-a53";
75 enable-method = "spin-table";
76 cpu-release-addr = <0x0 0x81100000>;
81 compatible = "arm,cortex-a53";
83 enable-method = "spin-table";
84 cpu-release-addr = <0x0 0x81100000>;
89 compatible = "arm,cortex-a53";
91 enable-method = "spin-table";
92 cpu-release-addr = <0x0 0x81100000>;
97 compatible = "arm,cortex-a53";
99 enable-method = "spin-table";
100 cpu-release-addr = <0x0 0x81100000>;
105 compatible = "arm,cortex-a53";
107 enable-method = "spin-table";
108 cpu-release-addr = <0x0 0x81100000>;
113 compatible = "arm,cortex-a53";
115 enable-method = "spin-table";
116 cpu-release-addr = <0x0 0x81100000>;
122 compatible = "arm,armv8-timer";
123 interrupt-parent = <&gic>;
125 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
126 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
127 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
128 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
132 compatible = "fixed-clock";
133 clock-frequency = <150000000>;
137 clk125mhz: clk125mhz {
138 compatible = "fixed-clock";
139 clock-frequency = <125000000>;
141 clock-output-names = "clk125mhz";
144 clk300mhz: clk300mhz {
145 compatible = "fixed-clock";
146 clock-frequency = <300000000>;
148 clock-output-names = "clk300mhz";
152 compatible = "fixed-clock";
153 clock-frequency = <150000000>;
158 #address-cells = <2>;
160 compatible = "simple-bus";
161 interrupt-parent = <&gic>;
164 gic: interrupt-controller@24001000 {
165 compatible = "arm,gic-400";
166 interrupt-controller;
167 #interrupt-cells = <3>;
168 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
169 reg = <0 0x24001000 0 0x1000>,
170 <0 0x24002000 0 0x2000>,
171 <0 0x24004000 0 0x2000>,
172 <0 0x24006000 0 0x2000>;
175 pmux: pmux@24190000 {
176 compatible = "toshiba,tmpv7708-pinctrl";
177 reg = <0 0x24190000 0 0x10000>;
180 gpio: gpio@28020000 {
181 compatible = "toshiba,gpio-tmpv7708";
182 reg = <0 0x28020000 0 0x1000>;
184 gpio-ranges = <&pmux 0 0 32>;
186 interrupt-controller;
187 #interrupt-cells = <2>;
188 interrupt-parent = <&gic>;
191 uart0: serial@28200000 {
192 compatible = "arm,pl011", "arm,primecell";
193 reg = <0 0x28200000 0 0x1000>;
194 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
195 pinctrl-names = "default";
196 pinctrl-0 = <&uart0_pins>;
200 uart1: serial@28201000 {
201 compatible = "arm,pl011", "arm,primecell";
202 reg = <0 0x28201000 0 0x1000>;
203 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
204 pinctrl-names = "default";
205 pinctrl-0 = <&uart1_pins>;
209 uart2: serial@28202000 {
210 compatible = "arm,pl011", "arm,primecell";
211 reg = <0 0x28202000 0 0x1000>;
212 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
213 pinctrl-names = "default";
214 pinctrl-0 = <&uart2_pins>;
218 uart3: serial@28203000 {
219 compatible = "arm,pl011", "arm,primecell";
220 reg = <0 0x28203000 0 0x1000>;
221 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
222 pinctrl-names = "default";
223 pinctrl-0 = <&uart3_pins>;
228 compatible = "snps,designware-i2c";
229 reg = <0 0x28030000 0 0x1000>;
230 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
231 pinctrl-names = "default";
232 pinctrl-0 = <&i2c0_pins>;
233 clock-frequency = <400000>;
234 #address-cells = <1>;
240 compatible = "snps,designware-i2c";
241 reg = <0 0x28031000 0 0x1000>;
242 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
243 pinctrl-names = "default";
244 pinctrl-0 = <&i2c1_pins>;
245 clock-frequency = <400000>;
246 #address-cells = <1>;
252 compatible = "snps,designware-i2c";
253 reg = <0 0x28032000 0 0x1000>;
254 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
255 pinctrl-names = "default";
256 pinctrl-0 = <&i2c2_pins>;
257 clock-frequency = <400000>;
258 #address-cells = <1>;
264 compatible = "snps,designware-i2c";
265 reg = <0 0x28033000 0 0x1000>;
266 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
267 pinctrl-names = "default";
268 pinctrl-0 = <&i2c3_pins>;
269 clock-frequency = <400000>;
270 #address-cells = <1>;
276 compatible = "snps,designware-i2c";
277 reg = <0 0x28034000 0 0x1000>;
278 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
279 pinctrl-names = "default";
280 pinctrl-0 = <&i2c4_pins>;
281 clock-frequency = <400000>;
282 #address-cells = <1>;
288 compatible = "snps,designware-i2c";
289 reg = <0 0x28035000 0 0x1000>;
290 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
291 pinctrl-names = "default";
292 pinctrl-0 = <&i2c5_pins>;
293 clock-frequency = <400000>;
294 #address-cells = <1>;
300 compatible = "snps,designware-i2c";
301 reg = <0 0x28036000 0 0x1000>;
302 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
303 pinctrl-names = "default";
304 pinctrl-0 = <&i2c6_pins>;
305 clock-frequency = <400000>;
306 #address-cells = <1>;
312 compatible = "snps,designware-i2c";
313 reg = <0 0x28037000 0 0x1000>;
314 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
315 pinctrl-names = "default";
316 pinctrl-0 = <&i2c7_pins>;
317 clock-frequency = <400000>;
318 #address-cells = <1>;
324 compatible = "snps,designware-i2c";
325 reg = <0 0x28038000 0 0x1000>;
326 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
327 pinctrl-names = "default";
328 pinctrl-0 = <&i2c8_pins>;
329 clock-frequency = <400000>;
330 #address-cells = <1>;
336 compatible = "arm,pl022", "arm,primecell";
337 reg = <0 0x28140000 0 0x1000>;
338 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
339 pinctrl-names = "default";
340 pinctrl-0 = <&spi0_pins>;
342 #address-cells = <1>;
348 compatible = "arm,pl022", "arm,primecell";
349 reg = <0 0x28141000 0 0x1000>;
350 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
351 pinctrl-names = "default";
352 pinctrl-0 = <&spi1_pins>;
354 #address-cells = <1>;
360 compatible = "arm,pl022", "arm,primecell";
361 reg = <0 0x28142000 0 0x1000>;
362 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
363 pinctrl-names = "default";
364 pinctrl-0 = <&spi2_pins>;
366 #address-cells = <1>;
372 compatible = "arm,pl022", "arm,primecell";
373 reg = <0 0x28143000 0 0x1000>;
374 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
375 pinctrl-names = "default";
376 pinctrl-0 = <&spi3_pins>;
378 #address-cells = <1>;
384 compatible = "arm,pl022", "arm,primecell";
385 reg = <0 0x28144000 0 0x1000>;
386 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
387 pinctrl-names = "default";
388 pinctrl-0 = <&spi4_pins>;
390 #address-cells = <1>;
396 compatible = "arm,pl022", "arm,primecell";
397 reg = <0 0x28145000 0 0x1000>;
398 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&spi5_pins>;
402 #address-cells = <1>;
408 compatible = "arm,pl022", "arm,primecell";
409 reg = <0 0x28146000 0 0x1000>;
410 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
411 pinctrl-names = "default";
412 pinctrl-0 = <&spi6_pins>;
414 #address-cells = <1>;
419 piether: ethernet@28000000 {
420 compatible = "toshiba,visconti-dwmac", "snps,dwmac-4.20a";
421 reg = <0 0x28000000 0 0x10000>;
422 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
423 interrupt-names = "macirq";
431 compatible = "toshiba,visconti-wdt";
432 reg = <0 0x28330000 0 0x1000>;
437 compatible = "toshiba,visconti-pwm";
438 reg = <0 0x241c0000 0 0x1000>;
439 pinctrl-names = "default";
440 pinctrl-0 = <&pwm_mux>;
447 #include "tmpv7708_pins.dtsi"